1*174a1cfeSYidi Lin /* 2*174a1cfeSYidi Lin * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. 3*174a1cfeSYidi Lin * 4*174a1cfeSYidi Lin * SPDX-License-Identifier: BSD-3-Clause 5*174a1cfeSYidi Lin */ 6*174a1cfeSYidi Lin 7*174a1cfeSYidi Lin #ifndef PLATFORM_DEF_H 8*174a1cfeSYidi Lin #define PLATFORM_DEF_H 9*174a1cfeSYidi Lin 10*174a1cfeSYidi Lin #define PLAT_PRIMARY_CPU 0x0 11*174a1cfeSYidi Lin 12*174a1cfeSYidi Lin #define MT_GIC_BASE (0x0C000000) 13*174a1cfeSYidi Lin #define MCUCFG_BASE (0x0C530000) 14*174a1cfeSYidi Lin #define IO_PHYS (0x10000000) 15*174a1cfeSYidi Lin 16*174a1cfeSYidi Lin /* Aggregate of all devices for MMU mapping */ 17*174a1cfeSYidi Lin #define MTK_DEV_RNG0_BASE IO_PHYS 18*174a1cfeSYidi Lin #define MTK_DEV_RNG0_SIZE 0x400000 19*174a1cfeSYidi Lin #define MTK_DEV_RNG1_BASE (IO_PHYS + 0x1000000) 20*174a1cfeSYidi Lin #define MTK_DEV_RNG1_SIZE 0xa110000 21*174a1cfeSYidi Lin #define MTK_DEV_RNG2_BASE MT_GIC_BASE 22*174a1cfeSYidi Lin #define MTK_DEV_RNG2_SIZE 0x600000 23*174a1cfeSYidi Lin 24*174a1cfeSYidi Lin 25*174a1cfeSYidi Lin /******************************************************************************* 26*174a1cfeSYidi Lin * UART related constants 27*174a1cfeSYidi Lin ******************************************************************************/ 28*174a1cfeSYidi Lin #define UART0_BASE (IO_PHYS + 0x01001100) 29*174a1cfeSYidi Lin #define UART1_BASE (IO_PHYS + 0x01001200) 30*174a1cfeSYidi Lin 31*174a1cfeSYidi Lin #define UART_BAUDRATE 115200 32*174a1cfeSYidi Lin 33*174a1cfeSYidi Lin /******************************************************************************* 34*174a1cfeSYidi Lin * System counter frequency related constants 35*174a1cfeSYidi Lin ******************************************************************************/ 36*174a1cfeSYidi Lin #define SYS_COUNTER_FREQ_IN_TICKS 13000000 37*174a1cfeSYidi Lin #define SYS_COUNTER_FREQ_IN_MHZ 13 38*174a1cfeSYidi Lin 39*174a1cfeSYidi Lin /******************************************************************************* 40*174a1cfeSYidi Lin * Platform binary types for linking 41*174a1cfeSYidi Lin ******************************************************************************/ 42*174a1cfeSYidi Lin #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 43*174a1cfeSYidi Lin #define PLATFORM_LINKER_ARCH aarch64 44*174a1cfeSYidi Lin 45*174a1cfeSYidi Lin /******************************************************************************* 46*174a1cfeSYidi Lin * Generic platform constants 47*174a1cfeSYidi Lin ******************************************************************************/ 48*174a1cfeSYidi Lin #define PLATFORM_STACK_SIZE 0x800 49*174a1cfeSYidi Lin 50*174a1cfeSYidi Lin #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 51*174a1cfeSYidi Lin 52*174a1cfeSYidi Lin #define PLAT_MAX_PWR_LVL U(3) 53*174a1cfeSYidi Lin #define PLAT_MAX_RET_STATE U(1) 54*174a1cfeSYidi Lin #define PLAT_MAX_OFF_STATE U(9) 55*174a1cfeSYidi Lin 56*174a1cfeSYidi Lin #define PLATFORM_SYSTEM_COUNT U(1) 57*174a1cfeSYidi Lin #define PLATFORM_MCUSYS_COUNT U(1) 58*174a1cfeSYidi Lin #define PLATFORM_CLUSTER_COUNT U(1) 59*174a1cfeSYidi Lin #define PLATFORM_CLUSTER0_CORE_COUNT U(8) 60*174a1cfeSYidi Lin #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 61*174a1cfeSYidi Lin 62*174a1cfeSYidi Lin #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 63*174a1cfeSYidi Lin #define PLATFORM_MAX_CPUS_PER_CLUSTER U(8) 64*174a1cfeSYidi Lin 65*174a1cfeSYidi Lin #define SOC_CHIP_ID U(0x8195) 66*174a1cfeSYidi Lin 67*174a1cfeSYidi Lin /******************************************************************************* 68*174a1cfeSYidi Lin * Platform memory map related constants 69*174a1cfeSYidi Lin ******************************************************************************/ 70*174a1cfeSYidi Lin #define TZRAM_BASE 0x54600000 71*174a1cfeSYidi Lin #define TZRAM_SIZE 0x00030000 72*174a1cfeSYidi Lin 73*174a1cfeSYidi Lin /******************************************************************************* 74*174a1cfeSYidi Lin * BL31 specific defines. 75*174a1cfeSYidi Lin ******************************************************************************/ 76*174a1cfeSYidi Lin /* 77*174a1cfeSYidi Lin * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 78*174a1cfeSYidi Lin * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 79*174a1cfeSYidi Lin * little space for growth. 80*174a1cfeSYidi Lin */ 81*174a1cfeSYidi Lin #define BL31_BASE (TZRAM_BASE + 0x1000) 82*174a1cfeSYidi Lin #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 83*174a1cfeSYidi Lin 84*174a1cfeSYidi Lin /******************************************************************************* 85*174a1cfeSYidi Lin * Platform specific page table and MMU setup constants 86*174a1cfeSYidi Lin ******************************************************************************/ 87*174a1cfeSYidi Lin #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 88*174a1cfeSYidi Lin #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 89*174a1cfeSYidi Lin #define MAX_XLAT_TABLES 16 90*174a1cfeSYidi Lin #define MAX_MMAP_REGIONS 16 91*174a1cfeSYidi Lin 92*174a1cfeSYidi Lin /******************************************************************************* 93*174a1cfeSYidi Lin * Declarations and constants to access the mailboxes safely. Each mailbox is 94*174a1cfeSYidi Lin * aligned on the biggest cache line size in the platform. This is known only 95*174a1cfeSYidi Lin * to the platform as it might have a combination of integrated and external 96*174a1cfeSYidi Lin * caches. Such alignment ensures that two maiboxes do not sit on the same cache 97*174a1cfeSYidi Lin * line at any cache level. They could belong to different cpus/clusters & 98*174a1cfeSYidi Lin * get written while being protected by different locks causing corruption of 99*174a1cfeSYidi Lin * a valid mailbox address. 100*174a1cfeSYidi Lin ******************************************************************************/ 101*174a1cfeSYidi Lin #define CACHE_WRITEBACK_SHIFT 6 102*174a1cfeSYidi Lin #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 103*174a1cfeSYidi Lin #endif /* PLATFORM_DEF_H */ 104