1 /* 2 * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <lib/xlat_tables/xlat_tables_v2.h> 8 9 #include <platform_def.h> 10 11 /* Table of regions to map using the MMU. */ 12 const mmap_region_t plat_mmap[] = { 13 /* for TF text, RO, RW */ 14 MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE, 15 MT_DEVICE | MT_RW | MT_SECURE), 16 MAP_REGION_FLAT(MTK_DEV_RNG2_BASE, MTK_DEV_RNG2_SIZE, 17 MT_DEVICE | MT_RW | MT_SECURE), 18 MAP_REGION_FLAT(MTK_MCDI_SRAM_BASE, MTK_MCDI_SRAM_MAP_SIZE, 19 MT_DEVICE | MT_RW | MT_SECURE), 20 MAP_REGION_FLAT(DP_SEC_BASE, DP_SEC_SIZE, 21 MT_DEVICE | MT_RW | MT_SECURE), 22 MAP_REGION_FLAT(EDP_SEC_BASE, EDP_SEC_SIZE, 23 MT_DEVICE | MT_RW | MT_SECURE), 24 MAP_REGION_FLAT(APUSYS_SCTRL_REVISER_BASE, APUSYS_SCTRL_REVISER_SIZE, 25 MT_DEVICE | MT_RW | MT_SECURE), 26 MAP_REGION_FLAT(APUSYS_APU_S_S_4_BASE, APUSYS_APU_S_S_4_SIZE, 27 MT_DEVICE | MT_RW | MT_SECURE), 28 MAP_REGION_FLAT(APUSYS_APU_PLL_BASE, APUSYS_APU_PLL_SIZE, 29 MT_DEVICE | MT_RW | MT_SECURE), 30 MAP_REGION_FLAT(APUSYS_APU_ACC_BASE, APUSYS_APU_ACC_SIZE, 31 MT_DEVICE | MT_RW | MT_SECURE), 32 { 0 } 33 }; 34 35 /******************************************************************************* 36 * Macro generating the code for the function setting up the pagetables as per 37 * the platform memory map & initialize the mmu, for the given exception level 38 ******************************************************************************/ 39 void plat_configure_mmu_el3(uintptr_t total_base, 40 uintptr_t total_size, 41 uintptr_t ro_start, 42 uintptr_t ro_limit) 43 { 44 mmap_add_region(total_base, total_base, total_size, 45 MT_RW_DATA | MT_SECURE); 46 mmap_add_region(ro_start, ro_start, ro_limit - ro_start, 47 MT_CODE | MT_SECURE); 48 mmap_add(plat_mmap); 49 init_xlat_tables(); 50 enable_mmu_el3(0); 51 } 52 53 unsigned int plat_get_syscnt_freq2(void) 54 { 55 return SYS_COUNTER_FREQ_IN_TICKS; 56 } 57