1 /* 2 * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch_def.h> 11 12 #define PLAT_PRIMARY_CPU (0x0) 13 14 #define MT_GIC_BASE (0x0C000000) 15 #define MCUCFG_BASE (0x0C530000) 16 #define MCUCFG_REG_SIZE (0x10000) 17 #define IO_PHYS (0x10000000) 18 19 /* Aggregate of all devices for MMU mapping */ 20 #define MTK_DEV_RNG0_BASE (MT_GIC_BASE) 21 #define MTK_DEV_RNG0_SIZE (0x600000) 22 #define MTK_DEV_RNG1_BASE (IO_PHYS) 23 #define MTK_DEV_RNG1_SIZE (0x10000000) 24 25 /******************************************************************************* 26 * GPIO related constants 27 ******************************************************************************/ 28 #define GPIO_BASE (IO_PHYS + 0x00005000) 29 #define RGU_BASE (IO_PHYS + 0x00007000) 30 #define DRM_BASE (IO_PHYS + 0x0000D000) 31 #define IOCFG_RM_BASE (IO_PHYS + 0x01C00000) 32 #define IOCFG_LT_BASE (IO_PHYS + 0x01E10000) 33 #define IOCFG_LM_BASE (IO_PHYS + 0x01E20000) 34 #define IOCFG_RT_BASE (IO_PHYS + 0x01EA0000) 35 36 /******************************************************************************* 37 * UART related constants 38 ******************************************************************************/ 39 #define UART0_BASE (IO_PHYS + 0x01002000) 40 #define UART_BAUDRATE (115200) 41 42 /******************************************************************************* 43 * PMIC related constants 44 ******************************************************************************/ 45 #define PMIC_WRAP_BASE (IO_PHYS + 0x00024000) 46 47 /******************************************************************************* 48 * Infra IOMMU related constants 49 ******************************************************************************/ 50 #define PERICFG_AO_BASE (IO_PHYS + 0x01003000) 51 #define PERICFG_AO_REG_SIZE (0x1000) 52 53 /******************************************************************************* 54 * GIC-600 & interrupt handling related constants 55 ******************************************************************************/ 56 /* Base MTK_platform compatible GIC memory map */ 57 #define BASE_GICD_BASE (MT_GIC_BASE) 58 #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) 59 60 /******************************************************************************* 61 * CIRQ related constants 62 ******************************************************************************/ 63 #define SYS_CIRQ_BASE (IO_PHYS + 0x204000) 64 #define MD_WDT_IRQ_BIT_ID (141) 65 #define CIRQ_IRQ_NUM (730) 66 #define CIRQ_REG_NUM (23) 67 #define CIRQ_SPI_START (96) 68 69 /******************************************************************************* 70 * MM IOMMU & SMI related constants 71 ******************************************************************************/ 72 #define SMI_LARB_0_BASE (IO_PHYS + 0x0c022000) 73 #define SMI_LARB_1_BASE (IO_PHYS + 0x0c023000) 74 #define SMI_LARB_2_BASE (IO_PHYS + 0x0c102000) 75 #define SMI_LARB_3_BASE (IO_PHYS + 0x0c103000) 76 #define SMI_LARB_4_BASE (IO_PHYS + 0x04013000) 77 #define SMI_LARB_5_BASE (IO_PHYS + 0x04f02000) 78 #define SMI_LARB_6_BASE (IO_PHYS + 0x04f03000) 79 #define SMI_LARB_7_BASE (IO_PHYS + 0x04e04000) 80 #define SMI_LARB_9_BASE (IO_PHYS + 0x05001000) 81 #define SMI_LARB_10_BASE (IO_PHYS + 0x05120000) 82 #define SMI_LARB_11A_BASE (IO_PHYS + 0x05230000) 83 #define SMI_LARB_11B_BASE (IO_PHYS + 0x05530000) 84 #define SMI_LARB_11C_BASE (IO_PHYS + 0x05630000) 85 #define SMI_LARB_12_BASE (IO_PHYS + 0x05340000) 86 #define SMI_LARB_13_BASE (IO_PHYS + 0x06001000) 87 #define SMI_LARB_14_BASE (IO_PHYS + 0x06002000) 88 #define SMI_LARB_15_BASE (IO_PHYS + 0x05140000) 89 #define SMI_LARB_16A_BASE (IO_PHYS + 0x06008000) 90 #define SMI_LARB_16B_BASE (IO_PHYS + 0x0600a000) 91 #define SMI_LARB_17A_BASE (IO_PHYS + 0x06009000) 92 #define SMI_LARB_17B_BASE (IO_PHYS + 0x0600b000) 93 #define SMI_LARB_19_BASE (IO_PHYS + 0x0a010000) 94 #define SMI_LARB_21_BASE (IO_PHYS + 0x0802e000) 95 #define SMI_LARB_23_BASE (IO_PHYS + 0x0800d000) 96 #define SMI_LARB_27_BASE (IO_PHYS + 0x07201000) 97 #define SMI_LARB_28_BASE (IO_PHYS + 0x00000000) 98 #define SMI_LARB_REG_RNG_SIZE (0x1000) 99 100 /******************************************************************************* 101 * DP related constants 102 ******************************************************************************/ 103 #define EDP_SEC_BASE (IO_PHYS + 0x0C504000) 104 #define DP_SEC_BASE (IO_PHYS + 0x0C604000) 105 #define EDP_SEC_SIZE (0x1000) 106 #define DP_SEC_SIZE (0x1000) 107 108 /******************************************************************************* 109 * EMI MPU related constants 110 *******************************************************************************/ 111 #define EMI_MPU_BASE (IO_PHYS + 0x00226000) 112 #define SUB_EMI_MPU_BASE (IO_PHYS + 0x00225000) 113 114 /******************************************************************************* 115 * System counter frequency related constants 116 ******************************************************************************/ 117 #define SYS_COUNTER_FREQ_IN_HZ (13000000) 118 #define SYS_COUNTER_FREQ_IN_MHZ (13) 119 120 /******************************************************************************* 121 * Platform binary types for linking 122 ******************************************************************************/ 123 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 124 #define PLATFORM_LINKER_ARCH aarch64 125 126 /******************************************************************************* 127 * Generic platform constants 128 ******************************************************************************/ 129 #define PLATFORM_STACK_SIZE (0x800) 130 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 131 #define SOC_CHIP_ID U(0x8188) 132 133 /******************************************************************************* 134 * Platform memory map related constants 135 ******************************************************************************/ 136 #define TZRAM_BASE (0x54600000) 137 #define TZRAM_SIZE (0x00030000) 138 139 /******************************************************************************* 140 * BL31 specific defines. 141 ******************************************************************************/ 142 /* 143 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 144 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 145 * little space for growth. 146 */ 147 #define BL31_BASE (TZRAM_BASE + 0x1000) 148 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 149 150 /******************************************************************************* 151 * Platform specific page table and MMU setup constants 152 ******************************************************************************/ 153 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 154 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 155 #define MAX_XLAT_TABLES (16) 156 #define MAX_MMAP_REGIONS (16) 157 158 #endif /* PLATFORM_DEF_H */ 159