1 /* 2 * Copyright (c) 2022-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch_def.h> 11 12 #define PLAT_PRIMARY_CPU (0x0) 13 14 #define MT_GIC_BASE (0x0C000000) 15 #define MCUCFG_BASE (0x0C530000) 16 #define MCUCFG_REG_SIZE (0x10000) 17 #define IO_PHYS (0x10000000) 18 19 /* Aggregate of all devices for MMU mapping */ 20 #define MTK_DEV_RNG0_BASE (MT_GIC_BASE) 21 #define MTK_DEV_RNG0_SIZE (0x600000) 22 #define MTK_DEV_RNG1_BASE (IO_PHYS) 23 #define MTK_DEV_RNG1_SIZE (0x10000000) 24 25 #define TOPCKGEN_BASE (IO_PHYS) 26 27 /******************************************************************************* 28 * APUSYS related constants 29 ******************************************************************************/ 30 #define BCRM_FMEM_PDN_BASE (IO_PHYS + 0x00276000) 31 #define APU_RCX_CONFIG (IO_PHYS + 0x09020000) 32 #define APU_RCX_VCORE_CONFIG (IO_PHYS + 0x090e0000) 33 #define APU_MBOX0 (IO_PHYS + 0x090e1000) 34 #define APU_RPCTOP (IO_PHYS + 0x090f0000) 35 #define APU_PCUTOP (IO_PHYS + 0x090f1000) 36 #define APU_AO_CTRL (IO_PHYS + 0x090f2000) 37 #define APU_PLL (IO_PHYS + 0x090f3000) 38 #define APU_ACC (IO_PHYS + 0x090f4000) 39 #define APU_ARETOP_ARE0 (IO_PHYS + 0x090f6000) 40 #define APU_ARETOP_ARE1 (IO_PHYS + 0x090f7000) 41 #define APU_ARETOP_ARE2 (IO_PHYS + 0x090f8000) 42 #define APU_ACX0_RPC_LITE (IO_PHYS + 0x09140000) 43 #define BCRM_FMEM_PDN_SIZE (0x1000) 44 45 /******************************************************************************* 46 * AUDIO related constants 47 ******************************************************************************/ 48 #define AUDIO_BASE (IO_PHYS + 0x00b10000) 49 50 /******************************************************************************* 51 * SPM related constants 52 ******************************************************************************/ 53 #define SPM_BASE (IO_PHYS + 0x00006000) 54 55 /******************************************************************************* 56 * GPIO related constants 57 ******************************************************************************/ 58 #define GPIO_BASE (IO_PHYS + 0x00005000) 59 #define RGU_BASE (IO_PHYS + 0x00007000) 60 #define DRM_BASE (IO_PHYS + 0x0000D000) 61 #define IOCFG_RM_BASE (IO_PHYS + 0x01C00000) 62 #define IOCFG_LT_BASE (IO_PHYS + 0x01E10000) 63 #define IOCFG_LM_BASE (IO_PHYS + 0x01E20000) 64 #define IOCFG_RT_BASE (IO_PHYS + 0x01EA0000) 65 66 /******************************************************************************* 67 * UART related constants 68 ******************************************************************************/ 69 #define UART0_BASE (IO_PHYS + 0x01002000) 70 #define UART_BAUDRATE (115200) 71 72 /******************************************************************************* 73 * PMIC related constants 74 ******************************************************************************/ 75 #define PMIC_WRAP_BASE (IO_PHYS + 0x00024000) 76 77 /******************************************************************************* 78 * Infra IOMMU related constants 79 ******************************************************************************/ 80 #define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) 81 #define INFRACFG_AO_MEM_BASE (IO_PHYS + 0x00002000) 82 #define PERICFG_AO_BASE (IO_PHYS + 0x01003000) 83 #define PERICFG_AO_REG_SIZE (0x1000) 84 85 /******************************************************************************* 86 * GIC-600 & interrupt handling related constants 87 ******************************************************************************/ 88 /* Base MTK_platform compatible GIC memory map */ 89 #define BASE_GICD_BASE (MT_GIC_BASE) 90 #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) 91 92 /******************************************************************************* 93 * CIRQ related constants 94 ******************************************************************************/ 95 #define SYS_CIRQ_BASE (IO_PHYS + 0x204000) 96 #define MD_WDT_IRQ_BIT_ID (141) 97 #define CIRQ_IRQ_NUM (730) 98 #define CIRQ_REG_NUM (23) 99 #define CIRQ_SPI_START (96) 100 101 /******************************************************************************* 102 * MM IOMMU & SMI related constants 103 ******************************************************************************/ 104 #define SMI_LARB_0_BASE (IO_PHYS + 0x0c022000) 105 #define SMI_LARB_1_BASE (IO_PHYS + 0x0c023000) 106 #define SMI_LARB_2_BASE (IO_PHYS + 0x0c102000) 107 #define SMI_LARB_3_BASE (IO_PHYS + 0x0c103000) 108 #define SMI_LARB_4_BASE (IO_PHYS + 0x04013000) 109 #define SMI_LARB_5_BASE (IO_PHYS + 0x04f02000) 110 #define SMI_LARB_6_BASE (IO_PHYS + 0x04f03000) 111 #define SMI_LARB_7_BASE (IO_PHYS + 0x04e04000) 112 #define SMI_LARB_9_BASE (IO_PHYS + 0x05001000) 113 #define SMI_LARB_10_BASE (IO_PHYS + 0x05120000) 114 #define SMI_LARB_11A_BASE (IO_PHYS + 0x05230000) 115 #define SMI_LARB_11B_BASE (IO_PHYS + 0x05530000) 116 #define SMI_LARB_11C_BASE (IO_PHYS + 0x05630000) 117 #define SMI_LARB_12_BASE (IO_PHYS + 0x05340000) 118 #define SMI_LARB_13_BASE (IO_PHYS + 0x06001000) 119 #define SMI_LARB_14_BASE (IO_PHYS + 0x06002000) 120 #define SMI_LARB_15_BASE (IO_PHYS + 0x05140000) 121 #define SMI_LARB_16A_BASE (IO_PHYS + 0x06008000) 122 #define SMI_LARB_16B_BASE (IO_PHYS + 0x0600a000) 123 #define SMI_LARB_17A_BASE (IO_PHYS + 0x06009000) 124 #define SMI_LARB_17B_BASE (IO_PHYS + 0x0600b000) 125 #define SMI_LARB_19_BASE (IO_PHYS + 0x0a010000) 126 #define SMI_LARB_21_BASE (IO_PHYS + 0x0802e000) 127 #define SMI_LARB_23_BASE (IO_PHYS + 0x0800d000) 128 #define SMI_LARB_27_BASE (IO_PHYS + 0x07201000) 129 #define SMI_LARB_28_BASE (IO_PHYS + 0x00000000) 130 #define SMI_LARB_REG_RNG_SIZE (0x1000) 131 132 /******************************************************************************* 133 * SPM related constants 134 ******************************************************************************/ 135 #define SPM_BASE (IO_PHYS + 0x00006000) 136 137 /******************************************************************************* 138 * APMIXEDSYS related constants 139 ******************************************************************************/ 140 #define APMIXEDSYS (IO_PHYS + 0x0000C000) 141 142 /******************************************************************************* 143 * VPPSYS related constants 144 ******************************************************************************/ 145 #define VPPSYS0_BASE (IO_PHYS + 0x04000000) 146 #define VPPSYS1_BASE (IO_PHYS + 0x04f00000) 147 148 /******************************************************************************* 149 * VDOSYS related constants 150 ******************************************************************************/ 151 #define VDOSYS0_BASE (IO_PHYS + 0x0C01D000) 152 #define VDOSYS1_BASE (IO_PHYS + 0x0C100000) 153 154 /******************************************************************************* 155 * SSPM_MBOX_3 related constants 156 ******************************************************************************/ 157 #define SSPM_MBOX_3_BASE (IO_PHYS + 0x00480000) 158 159 /******************************************************************************* 160 * DP related constants 161 ******************************************************************************/ 162 #define EDP_SEC_BASE (IO_PHYS + 0x0C504000) 163 #define DP_SEC_BASE (IO_PHYS + 0x0C604000) 164 #define EDP_SEC_SIZE (0x1000) 165 #define DP_SEC_SIZE (0x1000) 166 167 /******************************************************************************* 168 * EMI MPU related constants 169 *******************************************************************************/ 170 #define EMI_MPU_BASE (IO_PHYS + 0x00226000) 171 #define SUB_EMI_MPU_BASE (IO_PHYS + 0x00225000) 172 173 /******************************************************************************* 174 * System counter frequency related constants 175 ******************************************************************************/ 176 #define SYS_COUNTER_FREQ_IN_HZ (13000000) 177 #define SYS_COUNTER_FREQ_IN_MHZ (13) 178 179 /******************************************************************************* 180 * Platform binary types for linking 181 ******************************************************************************/ 182 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 183 #define PLATFORM_LINKER_ARCH aarch64 184 185 /******************************************************************************* 186 * Generic platform constants 187 ******************************************************************************/ 188 #define PLATFORM_STACK_SIZE (0x800) 189 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 190 #define SOC_CHIP_ID U(0x8188) 191 192 /******************************************************************************* 193 * Platform memory map related constants 194 ******************************************************************************/ 195 #define TZRAM_BASE (0x54600000) 196 #define TZRAM_SIZE (0x00030000) 197 198 /******************************************************************************* 199 * BL31 specific defines. 200 ******************************************************************************/ 201 /* 202 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 203 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 204 * little space for growth. 205 */ 206 #define BL31_BASE (TZRAM_BASE + 0x1000) 207 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 208 209 /******************************************************************************* 210 * Platform specific page table and MMU setup constants 211 ******************************************************************************/ 212 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 213 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 214 #define MAX_XLAT_TABLES (16) 215 #define MAX_MMAP_REGIONS (16) 216 217 /******************************************************************************* 218 * CPU_EB TCM handling related constants 219 ******************************************************************************/ 220 #define CPU_EB_TCM_BASE (0x0C550000) 221 #define CPU_EB_TCM_SIZE (0x10000) 222 #define CPU_EB_MBOX3_OFFSET (0xFCE0) 223 224 /******************************************************************************* 225 * CPU PM definitions 226 *******************************************************************************/ 227 #define PLAT_CPU_PM_B_BUCK_ISO_ID (6) 228 #define PLAT_CPU_PM_ILDO_ID (6) 229 #define CPU_IDLE_SRAM_BASE (0x11B000) 230 #define CPU_IDLE_SRAM_SIZE (0x1000) 231 232 #endif /* PLATFORM_DEF_H */ 233