1*a64d9f44SBo-Chen Chen /* 2*a64d9f44SBo-Chen Chen * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. 3*a64d9f44SBo-Chen Chen * 4*a64d9f44SBo-Chen Chen * SPDX-License-Identifier: BSD-3-Clause 5*a64d9f44SBo-Chen Chen */ 6*a64d9f44SBo-Chen Chen 7*a64d9f44SBo-Chen Chen #ifndef PLATFORM_DEF_H 8*a64d9f44SBo-Chen Chen #define PLATFORM_DEF_H 9*a64d9f44SBo-Chen Chen 10*a64d9f44SBo-Chen Chen #include <arch_def.h> 11*a64d9f44SBo-Chen Chen 12*a64d9f44SBo-Chen Chen #define PLAT_PRIMARY_CPU (0x0) 13*a64d9f44SBo-Chen Chen 14*a64d9f44SBo-Chen Chen #define MT_GIC_BASE (0x0C000000) 15*a64d9f44SBo-Chen Chen #define MCUCFG_BASE (0x0C530000) 16*a64d9f44SBo-Chen Chen #define MCUCFG_REG_SIZE (0x10000) 17*a64d9f44SBo-Chen Chen #define IO_PHYS (0x10000000) 18*a64d9f44SBo-Chen Chen 19*a64d9f44SBo-Chen Chen /* Aggregate of all devices for MMU mapping */ 20*a64d9f44SBo-Chen Chen #define MTK_DEV_RNG0_BASE (MT_GIC_BASE) 21*a64d9f44SBo-Chen Chen #define MTK_DEV_RNG0_SIZE (0x600000) 22*a64d9f44SBo-Chen Chen #define MTK_DEV_RNG1_BASE (IO_PHYS) 23*a64d9f44SBo-Chen Chen #define MTK_DEV_RNG1_SIZE (0x10000000) 24*a64d9f44SBo-Chen Chen 25*a64d9f44SBo-Chen Chen /******************************************************************************* 26*a64d9f44SBo-Chen Chen * GPIO related constants 27*a64d9f44SBo-Chen Chen ******************************************************************************/ 28*a64d9f44SBo-Chen Chen #define GPIO_BASE (IO_PHYS + 0x00005000) 29*a64d9f44SBo-Chen Chen #define RGU_BASE (IO_PHYS + 0x00007000) 30*a64d9f44SBo-Chen Chen #define DRM_BASE (IO_PHYS + 0x0000D000) 31*a64d9f44SBo-Chen Chen #define IOCFG_RM_BASE (IO_PHYS + 0x01C00000) 32*a64d9f44SBo-Chen Chen #define IOCFG_LT_BASE (IO_PHYS + 0x01E10000) 33*a64d9f44SBo-Chen Chen #define IOCFG_LM_BASE (IO_PHYS + 0x01E20000) 34*a64d9f44SBo-Chen Chen #define IOCFG_RT_BASE (IO_PHYS + 0x01EA0000) 35*a64d9f44SBo-Chen Chen 36*a64d9f44SBo-Chen Chen /******************************************************************************* 37*a64d9f44SBo-Chen Chen * UART related constants 38*a64d9f44SBo-Chen Chen ******************************************************************************/ 39*a64d9f44SBo-Chen Chen #define UART0_BASE (IO_PHYS + 0x01002000) 40*a64d9f44SBo-Chen Chen #define UART_BAUDRATE (115200) 41*a64d9f44SBo-Chen Chen 42*a64d9f44SBo-Chen Chen /******************************************************************************* 43*a64d9f44SBo-Chen Chen * PMIC related constants 44*a64d9f44SBo-Chen Chen ******************************************************************************/ 45*a64d9f44SBo-Chen Chen #define PMIC_WRAP_BASE (IO_PHYS + 0x00024000) 46*a64d9f44SBo-Chen Chen 47*a64d9f44SBo-Chen Chen /******************************************************************************* 48*a64d9f44SBo-Chen Chen * Infra IOMMU related constants 49*a64d9f44SBo-Chen Chen ******************************************************************************/ 50*a64d9f44SBo-Chen Chen #define PERICFG_AO_BASE (IO_PHYS + 0x01003000) 51*a64d9f44SBo-Chen Chen #define PERICFG_AO_REG_SIZE (0x1000) 52*a64d9f44SBo-Chen Chen 53*a64d9f44SBo-Chen Chen /******************************************************************************* 54*a64d9f44SBo-Chen Chen * GIC-600 & interrupt handling related constants 55*a64d9f44SBo-Chen Chen ******************************************************************************/ 56*a64d9f44SBo-Chen Chen /* Base MTK_platform compatible GIC memory map */ 57*a64d9f44SBo-Chen Chen #define BASE_GICD_BASE (MT_GIC_BASE) 58*a64d9f44SBo-Chen Chen #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) 59*a64d9f44SBo-Chen Chen 60*a64d9f44SBo-Chen Chen /******************************************************************************* 61*a64d9f44SBo-Chen Chen * CIRQ related constants 62*a64d9f44SBo-Chen Chen ******************************************************************************/ 63*a64d9f44SBo-Chen Chen #define SYS_CIRQ_BASE (IO_PHYS + 0x204000) 64*a64d9f44SBo-Chen Chen #define MD_WDT_IRQ_BIT_ID (141) 65*a64d9f44SBo-Chen Chen #define CIRQ_IRQ_NUM (730) 66*a64d9f44SBo-Chen Chen #define CIRQ_REG_NUM (23) 67*a64d9f44SBo-Chen Chen #define CIRQ_SPI_START (96) 68*a64d9f44SBo-Chen Chen 69*a64d9f44SBo-Chen Chen /******************************************************************************* 70*a64d9f44SBo-Chen Chen * MM IOMMU & SMI related constants 71*a64d9f44SBo-Chen Chen ******************************************************************************/ 72*a64d9f44SBo-Chen Chen #define SMI_LARB_0_BASE (IO_PHYS + 0x0c022000) 73*a64d9f44SBo-Chen Chen #define SMI_LARB_1_BASE (IO_PHYS + 0x0c023000) 74*a64d9f44SBo-Chen Chen #define SMI_LARB_2_BASE (IO_PHYS + 0x0c102000) 75*a64d9f44SBo-Chen Chen #define SMI_LARB_3_BASE (IO_PHYS + 0x0c103000) 76*a64d9f44SBo-Chen Chen #define SMI_LARB_4_BASE (IO_PHYS + 0x04013000) 77*a64d9f44SBo-Chen Chen #define SMI_LARB_5_BASE (IO_PHYS + 0x04f02000) 78*a64d9f44SBo-Chen Chen #define SMI_LARB_6_BASE (IO_PHYS + 0x04f03000) 79*a64d9f44SBo-Chen Chen #define SMI_LARB_7_BASE (IO_PHYS + 0x04e04000) 80*a64d9f44SBo-Chen Chen #define SMI_LARB_9_BASE (IO_PHYS + 0x05001000) 81*a64d9f44SBo-Chen Chen #define SMI_LARB_10_BASE (IO_PHYS + 0x05120000) 82*a64d9f44SBo-Chen Chen #define SMI_LARB_11A_BASE (IO_PHYS + 0x05230000) 83*a64d9f44SBo-Chen Chen #define SMI_LARB_11B_BASE (IO_PHYS + 0x05530000) 84*a64d9f44SBo-Chen Chen #define SMI_LARB_11C_BASE (IO_PHYS + 0x05630000) 85*a64d9f44SBo-Chen Chen #define SMI_LARB_12_BASE (IO_PHYS + 0x05340000) 86*a64d9f44SBo-Chen Chen #define SMI_LARB_13_BASE (IO_PHYS + 0x06001000) 87*a64d9f44SBo-Chen Chen #define SMI_LARB_14_BASE (IO_PHYS + 0x06002000) 88*a64d9f44SBo-Chen Chen #define SMI_LARB_15_BASE (IO_PHYS + 0x05140000) 89*a64d9f44SBo-Chen Chen #define SMI_LARB_16A_BASE (IO_PHYS + 0x06008000) 90*a64d9f44SBo-Chen Chen #define SMI_LARB_16B_BASE (IO_PHYS + 0x0600a000) 91*a64d9f44SBo-Chen Chen #define SMI_LARB_17A_BASE (IO_PHYS + 0x06009000) 92*a64d9f44SBo-Chen Chen #define SMI_LARB_17B_BASE (IO_PHYS + 0x0600b000) 93*a64d9f44SBo-Chen Chen #define SMI_LARB_19_BASE (IO_PHYS + 0x0a010000) 94*a64d9f44SBo-Chen Chen #define SMI_LARB_21_BASE (IO_PHYS + 0x0802e000) 95*a64d9f44SBo-Chen Chen #define SMI_LARB_23_BASE (IO_PHYS + 0x0800d000) 96*a64d9f44SBo-Chen Chen #define SMI_LARB_27_BASE (IO_PHYS + 0x07201000) 97*a64d9f44SBo-Chen Chen #define SMI_LARB_28_BASE (IO_PHYS + 0x00000000) 98*a64d9f44SBo-Chen Chen #define SMI_LARB_REG_RNG_SIZE (0x1000) 99*a64d9f44SBo-Chen Chen 100*a64d9f44SBo-Chen Chen /******************************************************************************* 101*a64d9f44SBo-Chen Chen * DP related constants 102*a64d9f44SBo-Chen Chen ******************************************************************************/ 103*a64d9f44SBo-Chen Chen #define EDP_SEC_BASE (IO_PHYS + 0x0C504000) 104*a64d9f44SBo-Chen Chen #define DP_SEC_BASE (IO_PHYS + 0x0C604000) 105*a64d9f44SBo-Chen Chen #define EDP_SEC_SIZE (0x1000) 106*a64d9f44SBo-Chen Chen #define DP_SEC_SIZE (0x1000) 107*a64d9f44SBo-Chen Chen 108*a64d9f44SBo-Chen Chen /******************************************************************************* 109*a64d9f44SBo-Chen Chen * EMI MPU related constants 110*a64d9f44SBo-Chen Chen *******************************************************************************/ 111*a64d9f44SBo-Chen Chen #define EMI_MPU_BASE (IO_PHYS + 0x00226000) 112*a64d9f44SBo-Chen Chen #define SUB_EMI_MPU_BASE (IO_PHYS + 0x00225000) 113*a64d9f44SBo-Chen Chen 114*a64d9f44SBo-Chen Chen /******************************************************************************* 115*a64d9f44SBo-Chen Chen * System counter frequency related constants 116*a64d9f44SBo-Chen Chen ******************************************************************************/ 117*a64d9f44SBo-Chen Chen #define SYS_COUNTER_FREQ_IN_HZ (13000000) 118*a64d9f44SBo-Chen Chen #define SYS_COUNTER_FREQ_IN_MHZ (13) 119*a64d9f44SBo-Chen Chen 120*a64d9f44SBo-Chen Chen /******************************************************************************* 121*a64d9f44SBo-Chen Chen * Platform binary types for linking 122*a64d9f44SBo-Chen Chen ******************************************************************************/ 123*a64d9f44SBo-Chen Chen #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 124*a64d9f44SBo-Chen Chen #define PLATFORM_LINKER_ARCH aarch64 125*a64d9f44SBo-Chen Chen 126*a64d9f44SBo-Chen Chen /******************************************************************************* 127*a64d9f44SBo-Chen Chen * Generic platform constants 128*a64d9f44SBo-Chen Chen ******************************************************************************/ 129*a64d9f44SBo-Chen Chen #define PLATFORM_STACK_SIZE (0x800) 130*a64d9f44SBo-Chen Chen #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 131*a64d9f44SBo-Chen Chen #define SOC_CHIP_ID U(0x8188) 132*a64d9f44SBo-Chen Chen 133*a64d9f44SBo-Chen Chen /******************************************************************************* 134*a64d9f44SBo-Chen Chen * Platform memory map related constants 135*a64d9f44SBo-Chen Chen ******************************************************************************/ 136*a64d9f44SBo-Chen Chen #define TZRAM_BASE (0x54600000) 137*a64d9f44SBo-Chen Chen #define TZRAM_SIZE (0x00030000) 138*a64d9f44SBo-Chen Chen 139*a64d9f44SBo-Chen Chen /******************************************************************************* 140*a64d9f44SBo-Chen Chen * BL31 specific defines. 141*a64d9f44SBo-Chen Chen ******************************************************************************/ 142*a64d9f44SBo-Chen Chen /* 143*a64d9f44SBo-Chen Chen * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 144*a64d9f44SBo-Chen Chen * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 145*a64d9f44SBo-Chen Chen * little space for growth. 146*a64d9f44SBo-Chen Chen */ 147*a64d9f44SBo-Chen Chen #define BL31_BASE (TZRAM_BASE + 0x1000) 148*a64d9f44SBo-Chen Chen #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 149*a64d9f44SBo-Chen Chen 150*a64d9f44SBo-Chen Chen /******************************************************************************* 151*a64d9f44SBo-Chen Chen * Platform specific page table and MMU setup constants 152*a64d9f44SBo-Chen Chen ******************************************************************************/ 153*a64d9f44SBo-Chen Chen #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 154*a64d9f44SBo-Chen Chen #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 155*a64d9f44SBo-Chen Chen #define MAX_XLAT_TABLES (16) 156*a64d9f44SBo-Chen Chen #define MAX_MMAP_REGIONS (16) 157*a64d9f44SBo-Chen Chen 158*a64d9f44SBo-Chen Chen #endif /* PLATFORM_DEF_H */ 159