127132f13SRex-BC Chen /* 227132f13SRex-BC Chen * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. 327132f13SRex-BC Chen * 427132f13SRex-BC Chen * SPDX-License-Identifier: BSD-3-Clause 527132f13SRex-BC Chen */ 627132f13SRex-BC Chen 727132f13SRex-BC Chen #ifndef PLATFORM_DEF_H 827132f13SRex-BC Chen #define PLATFORM_DEF_H 927132f13SRex-BC Chen 1027132f13SRex-BC Chen #define PLAT_PRIMARY_CPU 0x0 1127132f13SRex-BC Chen 1227132f13SRex-BC Chen #define MT_GIC_BASE (0x0C000000) 1327132f13SRex-BC Chen #define MCUCFG_BASE (0x0C530000) 1427132f13SRex-BC Chen #define IO_PHYS (0x10000000) 1527132f13SRex-BC Chen 1627132f13SRex-BC Chen /* Aggregate of all devices for MMU mapping */ 1727132f13SRex-BC Chen #define MTK_DEV_RNG0_BASE IO_PHYS 1827132f13SRex-BC Chen #define MTK_DEV_RNG0_SIZE 0x400000 1927132f13SRex-BC Chen #define MTK_DEV_RNG1_BASE (IO_PHYS + 0x1000000) 2027132f13SRex-BC Chen #define MTK_DEV_RNG1_SIZE 0xa110000 2127132f13SRex-BC Chen #define MTK_DEV_RNG2_BASE MT_GIC_BASE 2227132f13SRex-BC Chen #define MTK_DEV_RNG2_SIZE 0x600000 2327132f13SRex-BC Chen 2427132f13SRex-BC Chen 2527132f13SRex-BC Chen /******************************************************************************* 2627132f13SRex-BC Chen * UART related constants 2727132f13SRex-BC Chen ******************************************************************************/ 2827132f13SRex-BC Chen #define UART0_BASE (IO_PHYS + 0x01002000) 2927132f13SRex-BC Chen 3027132f13SRex-BC Chen #define UART_BAUDRATE 115200 3127132f13SRex-BC Chen 3227132f13SRex-BC Chen /******************************************************************************* 33*5bc88ec6SJames Lo * PWRAP related constants 34*5bc88ec6SJames Lo ******************************************************************************/ 35*5bc88ec6SJames Lo #define PMIC_WRAP_BASE (IO_PHYS + 0x0000D000) 36*5bc88ec6SJames Lo 37*5bc88ec6SJames Lo /******************************************************************************* 381b17e34cSPenny Jan * EMI MPU related constants 391b17e34cSPenny Jan ******************************************************************************/ 401b17e34cSPenny Jan #define EMI_MPU_BASE (IO_PHYS + 0x0021B000) 411b17e34cSPenny Jan 421b17e34cSPenny Jan /******************************************************************************* 4327132f13SRex-BC Chen * System counter frequency related constants 4427132f13SRex-BC Chen ******************************************************************************/ 4527132f13SRex-BC Chen #define SYS_COUNTER_FREQ_IN_TICKS 13000000 4627132f13SRex-BC Chen #define SYS_COUNTER_FREQ_IN_MHZ 13 4727132f13SRex-BC Chen 4827132f13SRex-BC Chen /******************************************************************************* 4927132f13SRex-BC Chen * Platform binary types for linking 5027132f13SRex-BC Chen ******************************************************************************/ 5127132f13SRex-BC Chen #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 5227132f13SRex-BC Chen #define PLATFORM_LINKER_ARCH aarch64 5327132f13SRex-BC Chen 5427132f13SRex-BC Chen /******************************************************************************* 5527132f13SRex-BC Chen * Generic platform constants 5627132f13SRex-BC Chen ******************************************************************************/ 5727132f13SRex-BC Chen #define PLATFORM_STACK_SIZE 0x800 5827132f13SRex-BC Chen 5927132f13SRex-BC Chen #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 6027132f13SRex-BC Chen 6127132f13SRex-BC Chen #define PLAT_MAX_PWR_LVL U(3) 6227132f13SRex-BC Chen #define PLAT_MAX_RET_STATE U(1) 6327132f13SRex-BC Chen #define PLAT_MAX_OFF_STATE U(9) 6427132f13SRex-BC Chen 6527132f13SRex-BC Chen #define PLATFORM_SYSTEM_COUNT U(1) 6627132f13SRex-BC Chen #define PLATFORM_MCUSYS_COUNT U(1) 6727132f13SRex-BC Chen #define PLATFORM_CLUSTER_COUNT U(1) 6827132f13SRex-BC Chen #define PLATFORM_CLUSTER0_CORE_COUNT U(8) 6927132f13SRex-BC Chen #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 7027132f13SRex-BC Chen 7127132f13SRex-BC Chen #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 7227132f13SRex-BC Chen #define PLATFORM_MAX_CPUS_PER_CLUSTER U(8) 7327132f13SRex-BC Chen 7427132f13SRex-BC Chen #define SOC_CHIP_ID U(0x8186) 7527132f13SRex-BC Chen 7627132f13SRex-BC Chen /******************************************************************************* 7727132f13SRex-BC Chen * Platform memory map related constants 7827132f13SRex-BC Chen ******************************************************************************/ 7927132f13SRex-BC Chen #define TZRAM_BASE 0x54600000 8027132f13SRex-BC Chen #define TZRAM_SIZE 0x00030000 8127132f13SRex-BC Chen 8227132f13SRex-BC Chen /******************************************************************************* 8327132f13SRex-BC Chen * BL31 specific defines. 8427132f13SRex-BC Chen ******************************************************************************/ 8527132f13SRex-BC Chen /* 8627132f13SRex-BC Chen * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 8727132f13SRex-BC Chen * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 8827132f13SRex-BC Chen * little space for growth. 8927132f13SRex-BC Chen */ 9027132f13SRex-BC Chen #define BL31_BASE (TZRAM_BASE + 0x1000) 9127132f13SRex-BC Chen #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 9227132f13SRex-BC Chen 9327132f13SRex-BC Chen /******************************************************************************* 9427132f13SRex-BC Chen * Platform specific page table and MMU setup constants 9527132f13SRex-BC Chen ******************************************************************************/ 9627132f13SRex-BC Chen #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 9727132f13SRex-BC Chen #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 9827132f13SRex-BC Chen #define MAX_XLAT_TABLES 16 9927132f13SRex-BC Chen #define MAX_MMAP_REGIONS 16 10027132f13SRex-BC Chen 10127132f13SRex-BC Chen /******************************************************************************* 10227132f13SRex-BC Chen * Declarations and constants to access the mailboxes safely. Each mailbox is 10327132f13SRex-BC Chen * aligned on the biggest cache line size in the platform. This is known only 10427132f13SRex-BC Chen * to the platform as it might have a combination of integrated and external 10527132f13SRex-BC Chen * caches. Such alignment ensures that two maiboxes do not sit on the same cache 10627132f13SRex-BC Chen * line at any cache level. They could belong to different cpus/clusters & 10727132f13SRex-BC Chen * get written while being protected by different locks causing corruption of 10827132f13SRex-BC Chen * a valid mailbox address. 10927132f13SRex-BC Chen ******************************************************************************/ 11027132f13SRex-BC Chen #define CACHE_WRITEBACK_SHIFT 6 11127132f13SRex-BC Chen #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 11227132f13SRex-BC Chen #endif /* PLATFORM_DEF_H */ 113