1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MT6373_LOWPOWER_REG_H 8 #define MT6373_LOWPOWER_REG_H 9 10 #define MT6373_RG_BUCK_VBUCK0_VOSEL_SLEEP_ADDR 0x1487 11 #define MT6373_RG_BUCK_VBUCK0_ONLV_EN_ADDR 0x1488 12 #define MT6373_RG_BUCK_VBUCK0_ONLV_EN_SHIFT 4 13 #define MT6373_RG_BUCK_VBUCK0_RC0_OP_EN_ADDR 0x148D 14 #define MT6373_RG_BUCK_VBUCK0_RC1_OP_EN_ADDR 0x148D 15 #define MT6373_RG_BUCK_VBUCK0_RC2_OP_EN_ADDR 0x148D 16 #define MT6373_RG_BUCK_VBUCK0_RC3_OP_EN_ADDR 0x148D 17 #define MT6373_RG_BUCK_VBUCK0_RC4_OP_EN_ADDR 0x148D 18 #define MT6373_RG_BUCK_VBUCK0_RC5_OP_EN_ADDR 0x148D 19 #define MT6373_RG_BUCK_VBUCK0_RC6_OP_EN_ADDR 0x148D 20 #define MT6373_RG_BUCK_VBUCK0_RC7_OP_EN_ADDR 0x148D 21 #define MT6373_RG_BUCK_VBUCK0_RC8_OP_EN_ADDR 0x148E 22 #define MT6373_RG_BUCK_VBUCK0_RC9_OP_EN_ADDR 0x148E 23 #define MT6373_RG_BUCK_VBUCK0_RC10_OP_EN_ADDR 0x148E 24 #define MT6373_RG_BUCK_VBUCK0_RC11_OP_EN_ADDR 0x148E 25 #define MT6373_RG_BUCK_VBUCK0_RC12_OP_EN_ADDR 0x148E 26 #define MT6373_RG_BUCK_VBUCK0_RC13_OP_EN_ADDR 0x148E 27 #define MT6373_RG_BUCK_VBUCK0_HW0_OP_EN_ADDR 0x148F 28 #define MT6373_RG_BUCK_VBUCK0_HW1_OP_EN_ADDR 0x148F 29 #define MT6373_RG_BUCK_VBUCK0_HW2_OP_EN_ADDR 0x148F 30 #define MT6373_RG_BUCK_VBUCK0_HW3_OP_EN_ADDR 0x148F 31 #define MT6373_RG_BUCK_VBUCK0_SW_OP_EN_ADDR 0x148F 32 #define MT6373_RG_BUCK_VBUCK0_RC0_OP_CFG_ADDR 0x1490 33 #define MT6373_RG_BUCK_VBUCK0_RC1_OP_CFG_ADDR 0x1490 34 #define MT6373_RG_BUCK_VBUCK0_RC2_OP_CFG_ADDR 0x1490 35 #define MT6373_RG_BUCK_VBUCK0_RC3_OP_CFG_ADDR 0x1490 36 #define MT6373_RG_BUCK_VBUCK0_RC4_OP_CFG_ADDR 0x1490 37 #define MT6373_RG_BUCK_VBUCK0_RC5_OP_CFG_ADDR 0x1490 38 #define MT6373_RG_BUCK_VBUCK0_RC6_OP_CFG_ADDR 0x1490 39 #define MT6373_RG_BUCK_VBUCK0_RC7_OP_CFG_ADDR 0x1490 40 #define MT6373_RG_BUCK_VBUCK0_RC8_OP_CFG_ADDR 0x1491 41 #define MT6373_RG_BUCK_VBUCK0_RC9_OP_CFG_ADDR 0x1491 42 #define MT6373_RG_BUCK_VBUCK0_RC10_OP_CFG_ADDR 0x1491 43 #define MT6373_RG_BUCK_VBUCK0_RC11_OP_CFG_ADDR 0x1491 44 #define MT6373_RG_BUCK_VBUCK0_RC12_OP_CFG_ADDR 0x1491 45 #define MT6373_RG_BUCK_VBUCK0_RC13_OP_CFG_ADDR 0x1491 46 #define MT6373_RG_BUCK_VBUCK0_HW0_OP_CFG_ADDR 0x1492 47 #define MT6373_RG_BUCK_VBUCK0_HW1_OP_CFG_ADDR 0x1492 48 #define MT6373_RG_BUCK_VBUCK0_HW2_OP_CFG_ADDR 0x1492 49 #define MT6373_RG_BUCK_VBUCK0_HW3_OP_CFG_ADDR 0x1492 50 #define MT6373_RG_BUCK_VBUCK0_RC0_OP_MODE_ADDR 0x1493 51 #define MT6373_RG_BUCK_VBUCK0_RC1_OP_MODE_ADDR 0x1493 52 #define MT6373_RG_BUCK_VBUCK0_RC2_OP_MODE_ADDR 0x1493 53 #define MT6373_RG_BUCK_VBUCK0_RC3_OP_MODE_ADDR 0x1493 54 #define MT6373_RG_BUCK_VBUCK0_RC4_OP_MODE_ADDR 0x1493 55 #define MT6373_RG_BUCK_VBUCK0_RC5_OP_MODE_ADDR 0x1493 56 #define MT6373_RG_BUCK_VBUCK0_RC6_OP_MODE_ADDR 0x1493 57 #define MT6373_RG_BUCK_VBUCK0_RC7_OP_MODE_ADDR 0x1493 58 #define MT6373_RG_BUCK_VBUCK0_RC8_OP_MODE_ADDR 0x1494 59 #define MT6373_RG_BUCK_VBUCK0_RC9_OP_MODE_ADDR 0x1494 60 #define MT6373_RG_BUCK_VBUCK0_RC10_OP_MODE_ADDR 0x1494 61 #define MT6373_RG_BUCK_VBUCK0_RC11_OP_MODE_ADDR 0x1494 62 #define MT6373_RG_BUCK_VBUCK0_RC12_OP_MODE_ADDR 0x1494 63 #define MT6373_RG_BUCK_VBUCK0_RC13_OP_MODE_ADDR 0x1494 64 #define MT6373_RG_BUCK_VBUCK0_HW0_OP_MODE_ADDR 0x1495 65 #define MT6373_RG_BUCK_VBUCK0_HW1_OP_MODE_ADDR 0x1495 66 #define MT6373_RG_BUCK_VBUCK0_HW2_OP_MODE_ADDR 0x1495 67 #define MT6373_RG_BUCK_VBUCK0_HW3_OP_MODE_ADDR 0x1495 68 #define MT6373_RG_BUCK_VBUCK1_VOSEL_SLEEP_ADDR 0x1507 69 #define MT6373_RG_BUCK_VBUCK1_ONLV_EN_ADDR 0x1508 70 #define MT6373_RG_BUCK_VBUCK1_ONLV_EN_SHIFT 4 71 #define MT6373_RG_BUCK_VBUCK1_RC0_OP_EN_ADDR 0x150D 72 #define MT6373_RG_BUCK_VBUCK1_RC1_OP_EN_ADDR 0x150D 73 #define MT6373_RG_BUCK_VBUCK1_RC2_OP_EN_ADDR 0x150D 74 #define MT6373_RG_BUCK_VBUCK1_RC3_OP_EN_ADDR 0x150D 75 #define MT6373_RG_BUCK_VBUCK1_RC4_OP_EN_ADDR 0x150D 76 #define MT6373_RG_BUCK_VBUCK1_RC5_OP_EN_ADDR 0x150D 77 #define MT6373_RG_BUCK_VBUCK1_RC6_OP_EN_ADDR 0x150D 78 #define MT6373_RG_BUCK_VBUCK1_RC7_OP_EN_ADDR 0x150D 79 #define MT6373_RG_BUCK_VBUCK1_RC8_OP_EN_ADDR 0x150E 80 #define MT6373_RG_BUCK_VBUCK1_RC9_OP_EN_ADDR 0x150E 81 #define MT6373_RG_BUCK_VBUCK1_RC10_OP_EN_ADDR 0x150E 82 #define MT6373_RG_BUCK_VBUCK1_RC11_OP_EN_ADDR 0x150E 83 #define MT6373_RG_BUCK_VBUCK1_RC12_OP_EN_ADDR 0x150E 84 #define MT6373_RG_BUCK_VBUCK1_RC13_OP_EN_ADDR 0x150E 85 #define MT6373_RG_BUCK_VBUCK1_HW0_OP_EN_ADDR 0x150F 86 #define MT6373_RG_BUCK_VBUCK1_HW1_OP_EN_ADDR 0x150F 87 #define MT6373_RG_BUCK_VBUCK1_HW2_OP_EN_ADDR 0x150F 88 #define MT6373_RG_BUCK_VBUCK1_HW3_OP_EN_ADDR 0x150F 89 #define MT6373_RG_BUCK_VBUCK1_SW_OP_EN_ADDR 0x150F 90 #define MT6373_RG_BUCK_VBUCK1_RC0_OP_CFG_ADDR 0x1510 91 #define MT6373_RG_BUCK_VBUCK1_RC1_OP_CFG_ADDR 0x1510 92 #define MT6373_RG_BUCK_VBUCK1_RC2_OP_CFG_ADDR 0x1510 93 #define MT6373_RG_BUCK_VBUCK1_RC3_OP_CFG_ADDR 0x1510 94 #define MT6373_RG_BUCK_VBUCK1_RC4_OP_CFG_ADDR 0x1510 95 #define MT6373_RG_BUCK_VBUCK1_RC5_OP_CFG_ADDR 0x1510 96 #define MT6373_RG_BUCK_VBUCK1_RC6_OP_CFG_ADDR 0x1510 97 #define MT6373_RG_BUCK_VBUCK1_RC7_OP_CFG_ADDR 0x1510 98 #define MT6373_RG_BUCK_VBUCK1_RC8_OP_CFG_ADDR 0x1511 99 #define MT6373_RG_BUCK_VBUCK1_RC9_OP_CFG_ADDR 0x1511 100 #define MT6373_RG_BUCK_VBUCK1_RC10_OP_CFG_ADDR 0x1511 101 #define MT6373_RG_BUCK_VBUCK1_RC11_OP_CFG_ADDR 0x1511 102 #define MT6373_RG_BUCK_VBUCK1_RC12_OP_CFG_ADDR 0x1511 103 #define MT6373_RG_BUCK_VBUCK1_RC13_OP_CFG_ADDR 0x1511 104 #define MT6373_RG_BUCK_VBUCK1_HW0_OP_CFG_ADDR 0x1512 105 #define MT6373_RG_BUCK_VBUCK1_HW1_OP_CFG_ADDR 0x1512 106 #define MT6373_RG_BUCK_VBUCK1_HW2_OP_CFG_ADDR 0x1512 107 #define MT6373_RG_BUCK_VBUCK1_HW3_OP_CFG_ADDR 0x1512 108 #define MT6373_RG_BUCK_VBUCK1_RC0_OP_MODE_ADDR 0x1513 109 #define MT6373_RG_BUCK_VBUCK1_RC1_OP_MODE_ADDR 0x1513 110 #define MT6373_RG_BUCK_VBUCK1_RC2_OP_MODE_ADDR 0x1513 111 #define MT6373_RG_BUCK_VBUCK1_RC3_OP_MODE_ADDR 0x1513 112 #define MT6373_RG_BUCK_VBUCK1_RC4_OP_MODE_ADDR 0x1513 113 #define MT6373_RG_BUCK_VBUCK1_RC5_OP_MODE_ADDR 0x1513 114 #define MT6373_RG_BUCK_VBUCK1_RC6_OP_MODE_ADDR 0x1513 115 #define MT6373_RG_BUCK_VBUCK1_RC7_OP_MODE_ADDR 0x1513 116 #define MT6373_RG_BUCK_VBUCK1_RC8_OP_MODE_ADDR 0x1514 117 #define MT6373_RG_BUCK_VBUCK1_RC9_OP_MODE_ADDR 0x1514 118 #define MT6373_RG_BUCK_VBUCK1_RC10_OP_MODE_ADDR 0x1514 119 #define MT6373_RG_BUCK_VBUCK1_RC11_OP_MODE_ADDR 0x1514 120 #define MT6373_RG_BUCK_VBUCK1_RC12_OP_MODE_ADDR 0x1514 121 #define MT6373_RG_BUCK_VBUCK1_RC13_OP_MODE_ADDR 0x1514 122 #define MT6373_RG_BUCK_VBUCK1_HW0_OP_MODE_ADDR 0x1515 123 #define MT6373_RG_BUCK_VBUCK1_HW1_OP_MODE_ADDR 0x1515 124 #define MT6373_RG_BUCK_VBUCK1_HW2_OP_MODE_ADDR 0x1515 125 #define MT6373_RG_BUCK_VBUCK1_HW3_OP_MODE_ADDR 0x1515 126 #define MT6373_RG_BUCK_VBUCK2_VOSEL_SLEEP_ADDR 0x1587 127 #define MT6373_RG_BUCK_VBUCK2_ONLV_EN_ADDR 0x1588 128 #define MT6373_RG_BUCK_VBUCK2_ONLV_EN_SHIFT 4 129 #define MT6373_RG_BUCK_VBUCK2_RC0_OP_EN_ADDR 0x158D 130 #define MT6373_RG_BUCK_VBUCK2_RC1_OP_EN_ADDR 0x158D 131 #define MT6373_RG_BUCK_VBUCK2_RC2_OP_EN_ADDR 0x158D 132 #define MT6373_RG_BUCK_VBUCK2_RC3_OP_EN_ADDR 0x158D 133 #define MT6373_RG_BUCK_VBUCK2_RC4_OP_EN_ADDR 0x158D 134 #define MT6373_RG_BUCK_VBUCK2_RC5_OP_EN_ADDR 0x158D 135 #define MT6373_RG_BUCK_VBUCK2_RC6_OP_EN_ADDR 0x158D 136 #define MT6373_RG_BUCK_VBUCK2_RC7_OP_EN_ADDR 0x158D 137 #define MT6373_RG_BUCK_VBUCK2_RC8_OP_EN_ADDR 0x158E 138 #define MT6373_RG_BUCK_VBUCK2_RC9_OP_EN_ADDR 0x158E 139 #define MT6373_RG_BUCK_VBUCK2_RC10_OP_EN_ADDR 0x158E 140 #define MT6373_RG_BUCK_VBUCK2_RC11_OP_EN_ADDR 0x158E 141 #define MT6373_RG_BUCK_VBUCK2_RC12_OP_EN_ADDR 0x158E 142 #define MT6373_RG_BUCK_VBUCK2_RC13_OP_EN_ADDR 0x158E 143 #define MT6373_RG_BUCK_VBUCK2_HW0_OP_EN_ADDR 0x158F 144 #define MT6373_RG_BUCK_VBUCK2_HW1_OP_EN_ADDR 0x158F 145 #define MT6373_RG_BUCK_VBUCK2_HW2_OP_EN_ADDR 0x158F 146 #define MT6373_RG_BUCK_VBUCK2_HW3_OP_EN_ADDR 0x158F 147 #define MT6373_RG_BUCK_VBUCK2_SW_OP_EN_ADDR 0x158F 148 #define MT6373_RG_BUCK_VBUCK2_RC0_OP_CFG_ADDR 0x1590 149 #define MT6373_RG_BUCK_VBUCK2_RC1_OP_CFG_ADDR 0x1590 150 #define MT6373_RG_BUCK_VBUCK2_RC2_OP_CFG_ADDR 0x1590 151 #define MT6373_RG_BUCK_VBUCK2_RC3_OP_CFG_ADDR 0x1590 152 #define MT6373_RG_BUCK_VBUCK2_RC4_OP_CFG_ADDR 0x1590 153 #define MT6373_RG_BUCK_VBUCK2_RC5_OP_CFG_ADDR 0x1590 154 #define MT6373_RG_BUCK_VBUCK2_RC6_OP_CFG_ADDR 0x1590 155 #define MT6373_RG_BUCK_VBUCK2_RC7_OP_CFG_ADDR 0x1590 156 #define MT6373_RG_BUCK_VBUCK2_RC8_OP_CFG_ADDR 0x1591 157 #define MT6373_RG_BUCK_VBUCK2_RC9_OP_CFG_ADDR 0x1591 158 #define MT6373_RG_BUCK_VBUCK2_RC10_OP_CFG_ADDR 0x1591 159 #define MT6373_RG_BUCK_VBUCK2_RC11_OP_CFG_ADDR 0x1591 160 #define MT6373_RG_BUCK_VBUCK2_RC12_OP_CFG_ADDR 0x1591 161 #define MT6373_RG_BUCK_VBUCK2_RC13_OP_CFG_ADDR 0x1591 162 #define MT6373_RG_BUCK_VBUCK2_HW0_OP_CFG_ADDR 0x1592 163 #define MT6373_RG_BUCK_VBUCK2_HW1_OP_CFG_ADDR 0x1592 164 #define MT6373_RG_BUCK_VBUCK2_HW2_OP_CFG_ADDR 0x1592 165 #define MT6373_RG_BUCK_VBUCK2_HW3_OP_CFG_ADDR 0x1592 166 #define MT6373_RG_BUCK_VBUCK2_RC0_OP_MODE_ADDR 0x1593 167 #define MT6373_RG_BUCK_VBUCK2_RC1_OP_MODE_ADDR 0x1593 168 #define MT6373_RG_BUCK_VBUCK2_RC2_OP_MODE_ADDR 0x1593 169 #define MT6373_RG_BUCK_VBUCK2_RC3_OP_MODE_ADDR 0x1593 170 #define MT6373_RG_BUCK_VBUCK2_RC4_OP_MODE_ADDR 0x1593 171 #define MT6373_RG_BUCK_VBUCK2_RC5_OP_MODE_ADDR 0x1593 172 #define MT6373_RG_BUCK_VBUCK2_RC6_OP_MODE_ADDR 0x1593 173 #define MT6373_RG_BUCK_VBUCK2_RC7_OP_MODE_ADDR 0x1593 174 #define MT6373_RG_BUCK_VBUCK2_RC8_OP_MODE_ADDR 0x1594 175 #define MT6373_RG_BUCK_VBUCK2_RC9_OP_MODE_ADDR 0x1594 176 #define MT6373_RG_BUCK_VBUCK2_RC10_OP_MODE_ADDR 0x1594 177 #define MT6373_RG_BUCK_VBUCK2_RC11_OP_MODE_ADDR 0x1594 178 #define MT6373_RG_BUCK_VBUCK2_RC12_OP_MODE_ADDR 0x1594 179 #define MT6373_RG_BUCK_VBUCK2_RC13_OP_MODE_ADDR 0x1594 180 #define MT6373_RG_BUCK_VBUCK2_HW0_OP_MODE_ADDR 0x1595 181 #define MT6373_RG_BUCK_VBUCK2_HW1_OP_MODE_ADDR 0x1595 182 #define MT6373_RG_BUCK_VBUCK2_HW2_OP_MODE_ADDR 0x1595 183 #define MT6373_RG_BUCK_VBUCK2_HW3_OP_MODE_ADDR 0x1595 184 #define MT6373_RG_BUCK_VBUCK3_VOSEL_SLEEP_ADDR 0x1607 185 #define MT6373_RG_BUCK_VBUCK3_ONLV_EN_ADDR 0x1608 186 #define MT6373_RG_BUCK_VBUCK3_ONLV_EN_SHIFT 4 187 #define MT6373_RG_BUCK_VBUCK3_RC0_OP_EN_ADDR 0x160D 188 #define MT6373_RG_BUCK_VBUCK3_RC1_OP_EN_ADDR 0x160D 189 #define MT6373_RG_BUCK_VBUCK3_RC2_OP_EN_ADDR 0x160D 190 #define MT6373_RG_BUCK_VBUCK3_RC3_OP_EN_ADDR 0x160D 191 #define MT6373_RG_BUCK_VBUCK3_RC4_OP_EN_ADDR 0x160D 192 #define MT6373_RG_BUCK_VBUCK3_RC5_OP_EN_ADDR 0x160D 193 #define MT6373_RG_BUCK_VBUCK3_RC6_OP_EN_ADDR 0x160D 194 #define MT6373_RG_BUCK_VBUCK3_RC7_OP_EN_ADDR 0x160D 195 #define MT6373_RG_BUCK_VBUCK3_RC8_OP_EN_ADDR 0x160E 196 #define MT6373_RG_BUCK_VBUCK3_RC9_OP_EN_ADDR 0x160E 197 #define MT6373_RG_BUCK_VBUCK3_RC10_OP_EN_ADDR 0x160E 198 #define MT6373_RG_BUCK_VBUCK3_RC11_OP_EN_ADDR 0x160E 199 #define MT6373_RG_BUCK_VBUCK3_RC12_OP_EN_ADDR 0x160E 200 #define MT6373_RG_BUCK_VBUCK3_RC13_OP_EN_ADDR 0x160E 201 #define MT6373_RG_BUCK_VBUCK3_HW0_OP_EN_ADDR 0x160F 202 #define MT6373_RG_BUCK_VBUCK3_HW1_OP_EN_ADDR 0x160F 203 #define MT6373_RG_BUCK_VBUCK3_HW2_OP_EN_ADDR 0x160F 204 #define MT6373_RG_BUCK_VBUCK3_HW3_OP_EN_ADDR 0x160F 205 #define MT6373_RG_BUCK_VBUCK3_SW_OP_EN_ADDR 0x160F 206 #define MT6373_RG_BUCK_VBUCK3_RC0_OP_CFG_ADDR 0x1610 207 #define MT6373_RG_BUCK_VBUCK3_RC1_OP_CFG_ADDR 0x1610 208 #define MT6373_RG_BUCK_VBUCK3_RC2_OP_CFG_ADDR 0x1610 209 #define MT6373_RG_BUCK_VBUCK3_RC3_OP_CFG_ADDR 0x1610 210 #define MT6373_RG_BUCK_VBUCK3_RC4_OP_CFG_ADDR 0x1610 211 #define MT6373_RG_BUCK_VBUCK3_RC5_OP_CFG_ADDR 0x1610 212 #define MT6373_RG_BUCK_VBUCK3_RC6_OP_CFG_ADDR 0x1610 213 #define MT6373_RG_BUCK_VBUCK3_RC7_OP_CFG_ADDR 0x1610 214 #define MT6373_RG_BUCK_VBUCK3_RC8_OP_CFG_ADDR 0x1611 215 #define MT6373_RG_BUCK_VBUCK3_RC9_OP_CFG_ADDR 0x1611 216 #define MT6373_RG_BUCK_VBUCK3_RC10_OP_CFG_ADDR 0x1611 217 #define MT6373_RG_BUCK_VBUCK3_RC11_OP_CFG_ADDR 0x1611 218 #define MT6373_RG_BUCK_VBUCK3_RC12_OP_CFG_ADDR 0x1611 219 #define MT6373_RG_BUCK_VBUCK3_RC13_OP_CFG_ADDR 0x1611 220 #define MT6373_RG_BUCK_VBUCK3_HW0_OP_CFG_ADDR 0x1612 221 #define MT6373_RG_BUCK_VBUCK3_HW1_OP_CFG_ADDR 0x1612 222 #define MT6373_RG_BUCK_VBUCK3_HW2_OP_CFG_ADDR 0x1612 223 #define MT6373_RG_BUCK_VBUCK3_HW3_OP_CFG_ADDR 0x1612 224 #define MT6373_RG_BUCK_VBUCK3_RC0_OP_MODE_ADDR 0x1613 225 #define MT6373_RG_BUCK_VBUCK3_RC1_OP_MODE_ADDR 0x1613 226 #define MT6373_RG_BUCK_VBUCK3_RC2_OP_MODE_ADDR 0x1613 227 #define MT6373_RG_BUCK_VBUCK3_RC3_OP_MODE_ADDR 0x1613 228 #define MT6373_RG_BUCK_VBUCK3_RC4_OP_MODE_ADDR 0x1613 229 #define MT6373_RG_BUCK_VBUCK3_RC5_OP_MODE_ADDR 0x1613 230 #define MT6373_RG_BUCK_VBUCK3_RC6_OP_MODE_ADDR 0x1613 231 #define MT6373_RG_BUCK_VBUCK3_RC7_OP_MODE_ADDR 0x1613 232 #define MT6373_RG_BUCK_VBUCK3_RC8_OP_MODE_ADDR 0x1614 233 #define MT6373_RG_BUCK_VBUCK3_RC9_OP_MODE_ADDR 0x1614 234 #define MT6373_RG_BUCK_VBUCK3_RC10_OP_MODE_ADDR 0x1614 235 #define MT6373_RG_BUCK_VBUCK3_RC11_OP_MODE_ADDR 0x1614 236 #define MT6373_RG_BUCK_VBUCK3_RC12_OP_MODE_ADDR 0x1614 237 #define MT6373_RG_BUCK_VBUCK3_RC13_OP_MODE_ADDR 0x1614 238 #define MT6373_RG_BUCK_VBUCK3_HW0_OP_MODE_ADDR 0x1615 239 #define MT6373_RG_BUCK_VBUCK3_HW1_OP_MODE_ADDR 0x1615 240 #define MT6373_RG_BUCK_VBUCK3_HW2_OP_MODE_ADDR 0x1615 241 #define MT6373_RG_BUCK_VBUCK3_HW3_OP_MODE_ADDR 0x1615 242 #define MT6373_RG_BUCK_VBUCK4_VOSEL_SLEEP_ADDR 0x1687 243 #define MT6373_RG_BUCK_VBUCK4_ONLV_EN_ADDR 0x1688 244 #define MT6373_RG_BUCK_VBUCK4_ONLV_EN_SHIFT 4 245 #define MT6373_RG_BUCK_VBUCK4_RC0_OP_EN_ADDR 0x168D 246 #define MT6373_RG_BUCK_VBUCK4_RC1_OP_EN_ADDR 0x168D 247 #define MT6373_RG_BUCK_VBUCK4_RC2_OP_EN_ADDR 0x168D 248 #define MT6373_RG_BUCK_VBUCK4_RC3_OP_EN_ADDR 0x168D 249 #define MT6373_RG_BUCK_VBUCK4_RC4_OP_EN_ADDR 0x168D 250 #define MT6373_RG_BUCK_VBUCK4_RC5_OP_EN_ADDR 0x168D 251 #define MT6373_RG_BUCK_VBUCK4_RC6_OP_EN_ADDR 0x168D 252 #define MT6373_RG_BUCK_VBUCK4_RC7_OP_EN_ADDR 0x168D 253 #define MT6373_RG_BUCK_VBUCK4_RC8_OP_EN_ADDR 0x168E 254 #define MT6373_RG_BUCK_VBUCK4_RC9_OP_EN_ADDR 0x168E 255 #define MT6373_RG_BUCK_VBUCK4_RC10_OP_EN_ADDR 0x168E 256 #define MT6373_RG_BUCK_VBUCK4_RC11_OP_EN_ADDR 0x168E 257 #define MT6373_RG_BUCK_VBUCK4_RC12_OP_EN_ADDR 0x168E 258 #define MT6373_RG_BUCK_VBUCK4_RC13_OP_EN_ADDR 0x168E 259 #define MT6373_RG_BUCK_VBUCK4_HW0_OP_EN_ADDR 0x168F 260 #define MT6373_RG_BUCK_VBUCK4_HW1_OP_EN_ADDR 0x168F 261 #define MT6373_RG_BUCK_VBUCK4_HW2_OP_EN_ADDR 0x168F 262 #define MT6373_RG_BUCK_VBUCK4_HW3_OP_EN_ADDR 0x168F 263 #define MT6373_RG_BUCK_VBUCK4_SW_OP_EN_ADDR 0x168F 264 #define MT6373_RG_BUCK_VBUCK4_RC0_OP_CFG_ADDR 0x1690 265 #define MT6373_RG_BUCK_VBUCK4_RC1_OP_CFG_ADDR 0x1690 266 #define MT6373_RG_BUCK_VBUCK4_RC2_OP_CFG_ADDR 0x1690 267 #define MT6373_RG_BUCK_VBUCK4_RC3_OP_CFG_ADDR 0x1690 268 #define MT6373_RG_BUCK_VBUCK4_RC4_OP_CFG_ADDR 0x1690 269 #define MT6373_RG_BUCK_VBUCK4_RC5_OP_CFG_ADDR 0x1690 270 #define MT6373_RG_BUCK_VBUCK4_RC6_OP_CFG_ADDR 0x1690 271 #define MT6373_RG_BUCK_VBUCK4_RC7_OP_CFG_ADDR 0x1690 272 #define MT6373_RG_BUCK_VBUCK4_RC8_OP_CFG_ADDR 0x1691 273 #define MT6373_RG_BUCK_VBUCK4_RC9_OP_CFG_ADDR 0x1691 274 #define MT6373_RG_BUCK_VBUCK4_RC10_OP_CFG_ADDR 0x1691 275 #define MT6373_RG_BUCK_VBUCK4_RC11_OP_CFG_ADDR 0x1691 276 #define MT6373_RG_BUCK_VBUCK4_RC12_OP_CFG_ADDR 0x1691 277 #define MT6373_RG_BUCK_VBUCK4_RC13_OP_CFG_ADDR 0x1691 278 #define MT6373_RG_BUCK_VBUCK4_HW0_OP_CFG_ADDR 0x1692 279 #define MT6373_RG_BUCK_VBUCK4_HW1_OP_CFG_ADDR 0x1692 280 #define MT6373_RG_BUCK_VBUCK4_HW2_OP_CFG_ADDR 0x1692 281 #define MT6373_RG_BUCK_VBUCK4_HW3_OP_CFG_ADDR 0x1692 282 #define MT6373_RG_BUCK_VBUCK4_RC0_OP_MODE_ADDR 0x1693 283 #define MT6373_RG_BUCK_VBUCK4_RC1_OP_MODE_ADDR 0x1693 284 #define MT6373_RG_BUCK_VBUCK4_RC2_OP_MODE_ADDR 0x1693 285 #define MT6373_RG_BUCK_VBUCK4_RC3_OP_MODE_ADDR 0x1693 286 #define MT6373_RG_BUCK_VBUCK4_RC4_OP_MODE_ADDR 0x1693 287 #define MT6373_RG_BUCK_VBUCK4_RC5_OP_MODE_ADDR 0x1693 288 #define MT6373_RG_BUCK_VBUCK4_RC6_OP_MODE_ADDR 0x1693 289 #define MT6373_RG_BUCK_VBUCK4_RC7_OP_MODE_ADDR 0x1693 290 #define MT6373_RG_BUCK_VBUCK4_RC8_OP_MODE_ADDR 0x1694 291 #define MT6373_RG_BUCK_VBUCK4_RC9_OP_MODE_ADDR 0x1694 292 #define MT6373_RG_BUCK_VBUCK4_RC10_OP_MODE_ADDR 0x1694 293 #define MT6373_RG_BUCK_VBUCK4_RC11_OP_MODE_ADDR 0x1694 294 #define MT6373_RG_BUCK_VBUCK4_RC12_OP_MODE_ADDR 0x1694 295 #define MT6373_RG_BUCK_VBUCK4_RC13_OP_MODE_ADDR 0x1694 296 #define MT6373_RG_BUCK_VBUCK4_HW0_OP_MODE_ADDR 0x1695 297 #define MT6373_RG_BUCK_VBUCK4_HW1_OP_MODE_ADDR 0x1695 298 #define MT6373_RG_BUCK_VBUCK4_HW2_OP_MODE_ADDR 0x1695 299 #define MT6373_RG_BUCK_VBUCK4_HW3_OP_MODE_ADDR 0x1695 300 #define MT6373_RG_BUCK_VBUCK5_VOSEL_SLEEP_ADDR 0x1707 301 #define MT6373_RG_BUCK_VBUCK5_ONLV_EN_ADDR 0x1708 302 #define MT6373_RG_BUCK_VBUCK5_ONLV_EN_SHIFT 4 303 #define MT6373_RG_BUCK_VBUCK5_RC0_OP_EN_ADDR 0x170D 304 #define MT6373_RG_BUCK_VBUCK5_RC1_OP_EN_ADDR 0x170D 305 #define MT6373_RG_BUCK_VBUCK5_RC2_OP_EN_ADDR 0x170D 306 #define MT6373_RG_BUCK_VBUCK5_RC3_OP_EN_ADDR 0x170D 307 #define MT6373_RG_BUCK_VBUCK5_RC4_OP_EN_ADDR 0x170D 308 #define MT6373_RG_BUCK_VBUCK5_RC5_OP_EN_ADDR 0x170D 309 #define MT6373_RG_BUCK_VBUCK5_RC6_OP_EN_ADDR 0x170D 310 #define MT6373_RG_BUCK_VBUCK5_RC7_OP_EN_ADDR 0x170D 311 #define MT6373_RG_BUCK_VBUCK5_RC8_OP_EN_ADDR 0x170E 312 #define MT6373_RG_BUCK_VBUCK5_RC9_OP_EN_ADDR 0x170E 313 #define MT6373_RG_BUCK_VBUCK5_RC10_OP_EN_ADDR 0x170E 314 #define MT6373_RG_BUCK_VBUCK5_RC11_OP_EN_ADDR 0x170E 315 #define MT6373_RG_BUCK_VBUCK5_RC12_OP_EN_ADDR 0x170E 316 #define MT6373_RG_BUCK_VBUCK5_RC13_OP_EN_ADDR 0x170E 317 #define MT6373_RG_BUCK_VBUCK5_HW0_OP_EN_ADDR 0x170F 318 #define MT6373_RG_BUCK_VBUCK5_HW1_OP_EN_ADDR 0x170F 319 #define MT6373_RG_BUCK_VBUCK5_HW2_OP_EN_ADDR 0x170F 320 #define MT6373_RG_BUCK_VBUCK5_HW3_OP_EN_ADDR 0x170F 321 #define MT6373_RG_BUCK_VBUCK5_SW_OP_EN_ADDR 0x170F 322 #define MT6373_RG_BUCK_VBUCK5_RC0_OP_CFG_ADDR 0x1710 323 #define MT6373_RG_BUCK_VBUCK5_RC1_OP_CFG_ADDR 0x1710 324 #define MT6373_RG_BUCK_VBUCK5_RC2_OP_CFG_ADDR 0x1710 325 #define MT6373_RG_BUCK_VBUCK5_RC3_OP_CFG_ADDR 0x1710 326 #define MT6373_RG_BUCK_VBUCK5_RC4_OP_CFG_ADDR 0x1710 327 #define MT6373_RG_BUCK_VBUCK5_RC5_OP_CFG_ADDR 0x1710 328 #define MT6373_RG_BUCK_VBUCK5_RC6_OP_CFG_ADDR 0x1710 329 #define MT6373_RG_BUCK_VBUCK5_RC7_OP_CFG_ADDR 0x1710 330 #define MT6373_RG_BUCK_VBUCK5_RC8_OP_CFG_ADDR 0x1711 331 #define MT6373_RG_BUCK_VBUCK5_RC9_OP_CFG_ADDR 0x1711 332 #define MT6373_RG_BUCK_VBUCK5_RC10_OP_CFG_ADDR 0x1711 333 #define MT6373_RG_BUCK_VBUCK5_RC11_OP_CFG_ADDR 0x1711 334 #define MT6373_RG_BUCK_VBUCK5_RC12_OP_CFG_ADDR 0x1711 335 #define MT6373_RG_BUCK_VBUCK5_RC13_OP_CFG_ADDR 0x1711 336 #define MT6373_RG_BUCK_VBUCK5_HW0_OP_CFG_ADDR 0x1712 337 #define MT6373_RG_BUCK_VBUCK5_HW1_OP_CFG_ADDR 0x1712 338 #define MT6373_RG_BUCK_VBUCK5_HW2_OP_CFG_ADDR 0x1712 339 #define MT6373_RG_BUCK_VBUCK5_HW3_OP_CFG_ADDR 0x1712 340 #define MT6373_RG_BUCK_VBUCK5_RC0_OP_MODE_ADDR 0x1713 341 #define MT6373_RG_BUCK_VBUCK5_RC1_OP_MODE_ADDR 0x1713 342 #define MT6373_RG_BUCK_VBUCK5_RC2_OP_MODE_ADDR 0x1713 343 #define MT6373_RG_BUCK_VBUCK5_RC3_OP_MODE_ADDR 0x1713 344 #define MT6373_RG_BUCK_VBUCK5_RC4_OP_MODE_ADDR 0x1713 345 #define MT6373_RG_BUCK_VBUCK5_RC5_OP_MODE_ADDR 0x1713 346 #define MT6373_RG_BUCK_VBUCK5_RC6_OP_MODE_ADDR 0x1713 347 #define MT6373_RG_BUCK_VBUCK5_RC7_OP_MODE_ADDR 0x1713 348 #define MT6373_RG_BUCK_VBUCK5_RC8_OP_MODE_ADDR 0x1714 349 #define MT6373_RG_BUCK_VBUCK5_RC9_OP_MODE_ADDR 0x1714 350 #define MT6373_RG_BUCK_VBUCK5_RC10_OP_MODE_ADDR 0x1714 351 #define MT6373_RG_BUCK_VBUCK5_RC11_OP_MODE_ADDR 0x1714 352 #define MT6373_RG_BUCK_VBUCK5_RC12_OP_MODE_ADDR 0x1714 353 #define MT6373_RG_BUCK_VBUCK5_RC13_OP_MODE_ADDR 0x1714 354 #define MT6373_RG_BUCK_VBUCK5_HW0_OP_MODE_ADDR 0x1715 355 #define MT6373_RG_BUCK_VBUCK5_HW1_OP_MODE_ADDR 0x1715 356 #define MT6373_RG_BUCK_VBUCK5_HW2_OP_MODE_ADDR 0x1715 357 #define MT6373_RG_BUCK_VBUCK5_HW3_OP_MODE_ADDR 0x1715 358 #define MT6373_RG_BUCK_VBUCK6_VOSEL_SLEEP_ADDR 0x1787 359 #define MT6373_RG_BUCK_VBUCK6_ONLV_EN_ADDR 0x1788 360 #define MT6373_RG_BUCK_VBUCK6_ONLV_EN_SHIFT 4 361 #define MT6373_RG_BUCK_VBUCK6_RC0_OP_EN_ADDR 0x178D 362 #define MT6373_RG_BUCK_VBUCK6_RC1_OP_EN_ADDR 0x178D 363 #define MT6373_RG_BUCK_VBUCK6_RC2_OP_EN_ADDR 0x178D 364 #define MT6373_RG_BUCK_VBUCK6_RC3_OP_EN_ADDR 0x178D 365 #define MT6373_RG_BUCK_VBUCK6_RC4_OP_EN_ADDR 0x178D 366 #define MT6373_RG_BUCK_VBUCK6_RC5_OP_EN_ADDR 0x178D 367 #define MT6373_RG_BUCK_VBUCK6_RC6_OP_EN_ADDR 0x178D 368 #define MT6373_RG_BUCK_VBUCK6_RC7_OP_EN_ADDR 0x178D 369 #define MT6373_RG_BUCK_VBUCK6_RC8_OP_EN_ADDR 0x178E 370 #define MT6373_RG_BUCK_VBUCK6_RC9_OP_EN_ADDR 0x178E 371 #define MT6373_RG_BUCK_VBUCK6_RC10_OP_EN_ADDR 0x178E 372 #define MT6373_RG_BUCK_VBUCK6_RC11_OP_EN_ADDR 0x178E 373 #define MT6373_RG_BUCK_VBUCK6_RC12_OP_EN_ADDR 0x178E 374 #define MT6373_RG_BUCK_VBUCK6_RC13_OP_EN_ADDR 0x178E 375 #define MT6373_RG_BUCK_VBUCK6_HW0_OP_EN_ADDR 0x178F 376 #define MT6373_RG_BUCK_VBUCK6_HW1_OP_EN_ADDR 0x178F 377 #define MT6373_RG_BUCK_VBUCK6_HW2_OP_EN_ADDR 0x178F 378 #define MT6373_RG_BUCK_VBUCK6_HW3_OP_EN_ADDR 0x178F 379 #define MT6373_RG_BUCK_VBUCK6_SW_OP_EN_ADDR 0x178F 380 #define MT6373_RG_BUCK_VBUCK6_RC0_OP_CFG_ADDR 0x1790 381 #define MT6373_RG_BUCK_VBUCK6_RC1_OP_CFG_ADDR 0x1790 382 #define MT6373_RG_BUCK_VBUCK6_RC2_OP_CFG_ADDR 0x1790 383 #define MT6373_RG_BUCK_VBUCK6_RC3_OP_CFG_ADDR 0x1790 384 #define MT6373_RG_BUCK_VBUCK6_RC4_OP_CFG_ADDR 0x1790 385 #define MT6373_RG_BUCK_VBUCK6_RC5_OP_CFG_ADDR 0x1790 386 #define MT6373_RG_BUCK_VBUCK6_RC6_OP_CFG_ADDR 0x1790 387 #define MT6373_RG_BUCK_VBUCK6_RC7_OP_CFG_ADDR 0x1790 388 #define MT6373_RG_BUCK_VBUCK6_RC8_OP_CFG_ADDR 0x1791 389 #define MT6373_RG_BUCK_VBUCK6_RC9_OP_CFG_ADDR 0x1791 390 #define MT6373_RG_BUCK_VBUCK6_RC10_OP_CFG_ADDR 0x1791 391 #define MT6373_RG_BUCK_VBUCK6_RC11_OP_CFG_ADDR 0x1791 392 #define MT6373_RG_BUCK_VBUCK6_RC12_OP_CFG_ADDR 0x1791 393 #define MT6373_RG_BUCK_VBUCK6_RC13_OP_CFG_ADDR 0x1791 394 #define MT6373_RG_BUCK_VBUCK6_HW0_OP_CFG_ADDR 0x1792 395 #define MT6373_RG_BUCK_VBUCK6_HW1_OP_CFG_ADDR 0x1792 396 #define MT6373_RG_BUCK_VBUCK6_HW2_OP_CFG_ADDR 0x1792 397 #define MT6373_RG_BUCK_VBUCK6_HW3_OP_CFG_ADDR 0x1792 398 #define MT6373_RG_BUCK_VBUCK6_RC0_OP_MODE_ADDR 0x1793 399 #define MT6373_RG_BUCK_VBUCK6_RC1_OP_MODE_ADDR 0x1793 400 #define MT6373_RG_BUCK_VBUCK6_RC2_OP_MODE_ADDR 0x1793 401 #define MT6373_RG_BUCK_VBUCK6_RC3_OP_MODE_ADDR 0x1793 402 #define MT6373_RG_BUCK_VBUCK6_RC4_OP_MODE_ADDR 0x1793 403 #define MT6373_RG_BUCK_VBUCK6_RC5_OP_MODE_ADDR 0x1793 404 #define MT6373_RG_BUCK_VBUCK6_RC6_OP_MODE_ADDR 0x1793 405 #define MT6373_RG_BUCK_VBUCK6_RC7_OP_MODE_ADDR 0x1793 406 #define MT6373_RG_BUCK_VBUCK6_RC8_OP_MODE_ADDR 0x1794 407 #define MT6373_RG_BUCK_VBUCK6_RC9_OP_MODE_ADDR 0x1794 408 #define MT6373_RG_BUCK_VBUCK6_RC10_OP_MODE_ADDR 0x1794 409 #define MT6373_RG_BUCK_VBUCK6_RC11_OP_MODE_ADDR 0x1794 410 #define MT6373_RG_BUCK_VBUCK6_RC12_OP_MODE_ADDR 0x1794 411 #define MT6373_RG_BUCK_VBUCK6_RC13_OP_MODE_ADDR 0x1794 412 #define MT6373_RG_BUCK_VBUCK6_HW0_OP_MODE_ADDR 0x1795 413 #define MT6373_RG_BUCK_VBUCK6_HW1_OP_MODE_ADDR 0x1795 414 #define MT6373_RG_BUCK_VBUCK6_HW2_OP_MODE_ADDR 0x1795 415 #define MT6373_RG_BUCK_VBUCK6_HW3_OP_MODE_ADDR 0x1795 416 #define MT6373_RG_BUCK_VBUCK7_VOSEL_SLEEP_ADDR 0x1807 417 #define MT6373_RG_BUCK_VBUCK7_ONLV_EN_ADDR 0x1808 418 #define MT6373_RG_BUCK_VBUCK7_ONLV_EN_SHIFT 4 419 #define MT6373_RG_BUCK_VBUCK7_RC0_OP_EN_ADDR 0x180D 420 #define MT6373_RG_BUCK_VBUCK7_RC1_OP_EN_ADDR 0x180D 421 #define MT6373_RG_BUCK_VBUCK7_RC2_OP_EN_ADDR 0x180D 422 #define MT6373_RG_BUCK_VBUCK7_RC3_OP_EN_ADDR 0x180D 423 #define MT6373_RG_BUCK_VBUCK7_RC4_OP_EN_ADDR 0x180D 424 #define MT6373_RG_BUCK_VBUCK7_RC5_OP_EN_ADDR 0x180D 425 #define MT6373_RG_BUCK_VBUCK7_RC6_OP_EN_ADDR 0x180D 426 #define MT6373_RG_BUCK_VBUCK7_RC7_OP_EN_ADDR 0x180D 427 #define MT6373_RG_BUCK_VBUCK7_RC8_OP_EN_ADDR 0x180E 428 #define MT6373_RG_BUCK_VBUCK7_RC9_OP_EN_ADDR 0x180E 429 #define MT6373_RG_BUCK_VBUCK7_RC10_OP_EN_ADDR 0x180E 430 #define MT6373_RG_BUCK_VBUCK7_RC11_OP_EN_ADDR 0x180E 431 #define MT6373_RG_BUCK_VBUCK7_RC12_OP_EN_ADDR 0x180E 432 #define MT6373_RG_BUCK_VBUCK7_RC13_OP_EN_ADDR 0x180E 433 #define MT6373_RG_BUCK_VBUCK7_HW0_OP_EN_ADDR 0x180F 434 #define MT6373_RG_BUCK_VBUCK7_HW1_OP_EN_ADDR 0x180F 435 #define MT6373_RG_BUCK_VBUCK7_HW2_OP_EN_ADDR 0x180F 436 #define MT6373_RG_BUCK_VBUCK7_HW3_OP_EN_ADDR 0x180F 437 #define MT6373_RG_BUCK_VBUCK7_SW_OP_EN_ADDR 0x180F 438 #define MT6373_RG_BUCK_VBUCK7_RC0_OP_CFG_ADDR 0x1810 439 #define MT6373_RG_BUCK_VBUCK7_RC1_OP_CFG_ADDR 0x1810 440 #define MT6373_RG_BUCK_VBUCK7_RC2_OP_CFG_ADDR 0x1810 441 #define MT6373_RG_BUCK_VBUCK7_RC3_OP_CFG_ADDR 0x1810 442 #define MT6373_RG_BUCK_VBUCK7_RC4_OP_CFG_ADDR 0x1810 443 #define MT6373_RG_BUCK_VBUCK7_RC5_OP_CFG_ADDR 0x1810 444 #define MT6373_RG_BUCK_VBUCK7_RC6_OP_CFG_ADDR 0x1810 445 #define MT6373_RG_BUCK_VBUCK7_RC7_OP_CFG_ADDR 0x1810 446 #define MT6373_RG_BUCK_VBUCK7_RC8_OP_CFG_ADDR 0x1811 447 #define MT6373_RG_BUCK_VBUCK7_RC9_OP_CFG_ADDR 0x1811 448 #define MT6373_RG_BUCK_VBUCK7_RC10_OP_CFG_ADDR 0x1811 449 #define MT6373_RG_BUCK_VBUCK7_RC11_OP_CFG_ADDR 0x1811 450 #define MT6373_RG_BUCK_VBUCK7_RC12_OP_CFG_ADDR 0x1811 451 #define MT6373_RG_BUCK_VBUCK7_RC13_OP_CFG_ADDR 0x1811 452 #define MT6373_RG_BUCK_VBUCK7_HW0_OP_CFG_ADDR 0x1812 453 #define MT6373_RG_BUCK_VBUCK7_HW1_OP_CFG_ADDR 0x1812 454 #define MT6373_RG_BUCK_VBUCK7_HW2_OP_CFG_ADDR 0x1812 455 #define MT6373_RG_BUCK_VBUCK7_HW3_OP_CFG_ADDR 0x1812 456 #define MT6373_RG_BUCK_VBUCK7_RC0_OP_MODE_ADDR 0x1813 457 #define MT6373_RG_BUCK_VBUCK7_RC1_OP_MODE_ADDR 0x1813 458 #define MT6373_RG_BUCK_VBUCK7_RC2_OP_MODE_ADDR 0x1813 459 #define MT6373_RG_BUCK_VBUCK7_RC3_OP_MODE_ADDR 0x1813 460 #define MT6373_RG_BUCK_VBUCK7_RC4_OP_MODE_ADDR 0x1813 461 #define MT6373_RG_BUCK_VBUCK7_RC5_OP_MODE_ADDR 0x1813 462 #define MT6373_RG_BUCK_VBUCK7_RC6_OP_MODE_ADDR 0x1813 463 #define MT6373_RG_BUCK_VBUCK7_RC7_OP_MODE_ADDR 0x1813 464 #define MT6373_RG_BUCK_VBUCK7_RC8_OP_MODE_ADDR 0x1814 465 #define MT6373_RG_BUCK_VBUCK7_RC9_OP_MODE_ADDR 0x1814 466 #define MT6373_RG_BUCK_VBUCK7_RC10_OP_MODE_ADDR 0x1814 467 #define MT6373_RG_BUCK_VBUCK7_RC11_OP_MODE_ADDR 0x1814 468 #define MT6373_RG_BUCK_VBUCK7_RC12_OP_MODE_ADDR 0x1814 469 #define MT6373_RG_BUCK_VBUCK7_RC13_OP_MODE_ADDR 0x1814 470 #define MT6373_RG_BUCK_VBUCK7_HW0_OP_MODE_ADDR 0x1815 471 #define MT6373_RG_BUCK_VBUCK7_HW1_OP_MODE_ADDR 0x1815 472 #define MT6373_RG_BUCK_VBUCK7_HW2_OP_MODE_ADDR 0x1815 473 #define MT6373_RG_BUCK_VBUCK7_HW3_OP_MODE_ADDR 0x1815 474 #define MT6373_RG_BUCK_VBUCK8_VOSEL_SLEEP_ADDR 0x1887 475 #define MT6373_RG_BUCK_VBUCK8_ONLV_EN_ADDR 0x1888 476 #define MT6373_RG_BUCK_VBUCK8_ONLV_EN_SHIFT 4 477 #define MT6373_RG_BUCK_VBUCK8_RC0_OP_EN_ADDR 0x188D 478 #define MT6373_RG_BUCK_VBUCK8_RC1_OP_EN_ADDR 0x188D 479 #define MT6373_RG_BUCK_VBUCK8_RC2_OP_EN_ADDR 0x188D 480 #define MT6373_RG_BUCK_VBUCK8_RC3_OP_EN_ADDR 0x188D 481 #define MT6373_RG_BUCK_VBUCK8_RC4_OP_EN_ADDR 0x188D 482 #define MT6373_RG_BUCK_VBUCK8_RC5_OP_EN_ADDR 0x188D 483 #define MT6373_RG_BUCK_VBUCK8_RC6_OP_EN_ADDR 0x188D 484 #define MT6373_RG_BUCK_VBUCK8_RC7_OP_EN_ADDR 0x188D 485 #define MT6373_RG_BUCK_VBUCK8_RC8_OP_EN_ADDR 0x188E 486 #define MT6373_RG_BUCK_VBUCK8_RC9_OP_EN_ADDR 0x188E 487 #define MT6373_RG_BUCK_VBUCK8_RC10_OP_EN_ADDR 0x188E 488 #define MT6373_RG_BUCK_VBUCK8_RC11_OP_EN_ADDR 0x188E 489 #define MT6373_RG_BUCK_VBUCK8_RC12_OP_EN_ADDR 0x188E 490 #define MT6373_RG_BUCK_VBUCK8_RC13_OP_EN_ADDR 0x188E 491 #define MT6373_RG_BUCK_VBUCK8_HW0_OP_EN_ADDR 0x188F 492 #define MT6373_RG_BUCK_VBUCK8_HW1_OP_EN_ADDR 0x188F 493 #define MT6373_RG_BUCK_VBUCK8_HW2_OP_EN_ADDR 0x188F 494 #define MT6373_RG_BUCK_VBUCK8_HW3_OP_EN_ADDR 0x188F 495 #define MT6373_RG_BUCK_VBUCK8_SW_OP_EN_ADDR 0x188F 496 #define MT6373_RG_BUCK_VBUCK8_RC0_OP_CFG_ADDR 0x1890 497 #define MT6373_RG_BUCK_VBUCK8_RC1_OP_CFG_ADDR 0x1890 498 #define MT6373_RG_BUCK_VBUCK8_RC2_OP_CFG_ADDR 0x1890 499 #define MT6373_RG_BUCK_VBUCK8_RC3_OP_CFG_ADDR 0x1890 500 #define MT6373_RG_BUCK_VBUCK8_RC4_OP_CFG_ADDR 0x1890 501 #define MT6373_RG_BUCK_VBUCK8_RC5_OP_CFG_ADDR 0x1890 502 #define MT6373_RG_BUCK_VBUCK8_RC6_OP_CFG_ADDR 0x1890 503 #define MT6373_RG_BUCK_VBUCK8_RC7_OP_CFG_ADDR 0x1890 504 #define MT6373_RG_BUCK_VBUCK8_RC8_OP_CFG_ADDR 0x1891 505 #define MT6373_RG_BUCK_VBUCK8_RC9_OP_CFG_ADDR 0x1891 506 #define MT6373_RG_BUCK_VBUCK8_RC10_OP_CFG_ADDR 0x1891 507 #define MT6373_RG_BUCK_VBUCK8_RC11_OP_CFG_ADDR 0x1891 508 #define MT6373_RG_BUCK_VBUCK8_RC12_OP_CFG_ADDR 0x1891 509 #define MT6373_RG_BUCK_VBUCK8_RC13_OP_CFG_ADDR 0x1891 510 #define MT6373_RG_BUCK_VBUCK8_HW0_OP_CFG_ADDR 0x1892 511 #define MT6373_RG_BUCK_VBUCK8_HW1_OP_CFG_ADDR 0x1892 512 #define MT6373_RG_BUCK_VBUCK8_HW2_OP_CFG_ADDR 0x1892 513 #define MT6373_RG_BUCK_VBUCK8_HW3_OP_CFG_ADDR 0x1892 514 #define MT6373_RG_BUCK_VBUCK8_RC0_OP_MODE_ADDR 0x1893 515 #define MT6373_RG_BUCK_VBUCK8_RC1_OP_MODE_ADDR 0x1893 516 #define MT6373_RG_BUCK_VBUCK8_RC2_OP_MODE_ADDR 0x1893 517 #define MT6373_RG_BUCK_VBUCK8_RC3_OP_MODE_ADDR 0x1893 518 #define MT6373_RG_BUCK_VBUCK8_RC4_OP_MODE_ADDR 0x1893 519 #define MT6373_RG_BUCK_VBUCK8_RC5_OP_MODE_ADDR 0x1893 520 #define MT6373_RG_BUCK_VBUCK8_RC6_OP_MODE_ADDR 0x1893 521 #define MT6373_RG_BUCK_VBUCK8_RC7_OP_MODE_ADDR 0x1893 522 #define MT6373_RG_BUCK_VBUCK8_RC8_OP_MODE_ADDR 0x1894 523 #define MT6373_RG_BUCK_VBUCK8_RC9_OP_MODE_ADDR 0x1894 524 #define MT6373_RG_BUCK_VBUCK8_RC10_OP_MODE_ADDR 0x1894 525 #define MT6373_RG_BUCK_VBUCK8_RC11_OP_MODE_ADDR 0x1894 526 #define MT6373_RG_BUCK_VBUCK8_RC12_OP_MODE_ADDR 0x1894 527 #define MT6373_RG_BUCK_VBUCK8_RC13_OP_MODE_ADDR 0x1894 528 #define MT6373_RG_BUCK_VBUCK8_HW0_OP_MODE_ADDR 0x1895 529 #define MT6373_RG_BUCK_VBUCK8_HW1_OP_MODE_ADDR 0x1895 530 #define MT6373_RG_BUCK_VBUCK8_HW2_OP_MODE_ADDR 0x1895 531 #define MT6373_RG_BUCK_VBUCK8_HW3_OP_MODE_ADDR 0x1895 532 #define MT6373_RG_BUCK_VBUCK9_VOSEL_SLEEP_ADDR 0x1907 533 #define MT6373_RG_BUCK_VBUCK9_ONLV_EN_ADDR 0x1908 534 #define MT6373_RG_BUCK_VBUCK9_ONLV_EN_SHIFT 4 535 #define MT6373_RG_BUCK_VBUCK9_RC0_OP_EN_ADDR 0x190D 536 #define MT6373_RG_BUCK_VBUCK9_RC1_OP_EN_ADDR 0x190D 537 #define MT6373_RG_BUCK_VBUCK9_RC2_OP_EN_ADDR 0x190D 538 #define MT6373_RG_BUCK_VBUCK9_RC3_OP_EN_ADDR 0x190D 539 #define MT6373_RG_BUCK_VBUCK9_RC4_OP_EN_ADDR 0x190D 540 #define MT6373_RG_BUCK_VBUCK9_RC5_OP_EN_ADDR 0x190D 541 #define MT6373_RG_BUCK_VBUCK9_RC6_OP_EN_ADDR 0x190D 542 #define MT6373_RG_BUCK_VBUCK9_RC7_OP_EN_ADDR 0x190D 543 #define MT6373_RG_BUCK_VBUCK9_RC8_OP_EN_ADDR 0x190E 544 #define MT6373_RG_BUCK_VBUCK9_RC9_OP_EN_ADDR 0x190E 545 #define MT6373_RG_BUCK_VBUCK9_RC10_OP_EN_ADDR 0x190E 546 #define MT6373_RG_BUCK_VBUCK9_RC11_OP_EN_ADDR 0x190E 547 #define MT6373_RG_BUCK_VBUCK9_RC12_OP_EN_ADDR 0x190E 548 #define MT6373_RG_BUCK_VBUCK9_RC13_OP_EN_ADDR 0x190E 549 #define MT6373_RG_BUCK_VBUCK9_HW0_OP_EN_ADDR 0x190F 550 #define MT6373_RG_BUCK_VBUCK9_HW1_OP_EN_ADDR 0x190F 551 #define MT6373_RG_BUCK_VBUCK9_HW2_OP_EN_ADDR 0x190F 552 #define MT6373_RG_BUCK_VBUCK9_HW3_OP_EN_ADDR 0x190F 553 #define MT6373_RG_BUCK_VBUCK9_SW_OP_EN_ADDR 0x190F 554 #define MT6373_RG_BUCK_VBUCK9_RC0_OP_CFG_ADDR 0x1910 555 #define MT6373_RG_BUCK_VBUCK9_RC1_OP_CFG_ADDR 0x1910 556 #define MT6373_RG_BUCK_VBUCK9_RC2_OP_CFG_ADDR 0x1910 557 #define MT6373_RG_BUCK_VBUCK9_RC3_OP_CFG_ADDR 0x1910 558 #define MT6373_RG_BUCK_VBUCK9_RC4_OP_CFG_ADDR 0x1910 559 #define MT6373_RG_BUCK_VBUCK9_RC5_OP_CFG_ADDR 0x1910 560 #define MT6373_RG_BUCK_VBUCK9_RC6_OP_CFG_ADDR 0x1910 561 #define MT6373_RG_BUCK_VBUCK9_RC7_OP_CFG_ADDR 0x1910 562 #define MT6373_RG_BUCK_VBUCK9_RC8_OP_CFG_ADDR 0x1911 563 #define MT6373_RG_BUCK_VBUCK9_RC9_OP_CFG_ADDR 0x1911 564 #define MT6373_RG_BUCK_VBUCK9_RC10_OP_CFG_ADDR 0x1911 565 #define MT6373_RG_BUCK_VBUCK9_RC11_OP_CFG_ADDR 0x1911 566 #define MT6373_RG_BUCK_VBUCK9_RC12_OP_CFG_ADDR 0x1911 567 #define MT6373_RG_BUCK_VBUCK9_RC13_OP_CFG_ADDR 0x1911 568 #define MT6373_RG_BUCK_VBUCK9_HW0_OP_CFG_ADDR 0x1912 569 #define MT6373_RG_BUCK_VBUCK9_HW1_OP_CFG_ADDR 0x1912 570 #define MT6373_RG_BUCK_VBUCK9_HW2_OP_CFG_ADDR 0x1912 571 #define MT6373_RG_BUCK_VBUCK9_HW3_OP_CFG_ADDR 0x1912 572 #define MT6373_RG_BUCK_VBUCK9_RC0_OP_MODE_ADDR 0x1913 573 #define MT6373_RG_BUCK_VBUCK9_RC1_OP_MODE_ADDR 0x1913 574 #define MT6373_RG_BUCK_VBUCK9_RC2_OP_MODE_ADDR 0x1913 575 #define MT6373_RG_BUCK_VBUCK9_RC3_OP_MODE_ADDR 0x1913 576 #define MT6373_RG_BUCK_VBUCK9_RC4_OP_MODE_ADDR 0x1913 577 #define MT6373_RG_BUCK_VBUCK9_RC5_OP_MODE_ADDR 0x1913 578 #define MT6373_RG_BUCK_VBUCK9_RC6_OP_MODE_ADDR 0x1913 579 #define MT6373_RG_BUCK_VBUCK9_RC7_OP_MODE_ADDR 0x1913 580 #define MT6373_RG_BUCK_VBUCK9_RC8_OP_MODE_ADDR 0x1914 581 #define MT6373_RG_BUCK_VBUCK9_RC9_OP_MODE_ADDR 0x1914 582 #define MT6373_RG_BUCK_VBUCK9_RC10_OP_MODE_ADDR 0x1914 583 #define MT6373_RG_BUCK_VBUCK9_RC11_OP_MODE_ADDR 0x1914 584 #define MT6373_RG_BUCK_VBUCK9_RC12_OP_MODE_ADDR 0x1914 585 #define MT6373_RG_BUCK_VBUCK9_RC13_OP_MODE_ADDR 0x1914 586 #define MT6373_RG_BUCK_VBUCK9_HW0_OP_MODE_ADDR 0x1915 587 #define MT6373_RG_BUCK_VBUCK9_HW1_OP_MODE_ADDR 0x1915 588 #define MT6373_RG_BUCK_VBUCK9_HW2_OP_MODE_ADDR 0x1915 589 #define MT6373_RG_BUCK_VBUCK9_HW3_OP_MODE_ADDR 0x1915 590 #define MT6373_RG_LDO_VAUD18_ONLV_EN_ADDR 0x1B88 591 #define MT6373_RG_LDO_VAUD18_ONLV_EN_SHIFT 3 592 #define MT6373_RG_LDO_VAUD18_RC0_OP_EN_ADDR 0x1B8C 593 #define MT6373_RG_LDO_VAUD18_RC1_OP_EN_ADDR 0x1B8C 594 #define MT6373_RG_LDO_VAUD18_RC2_OP_EN_ADDR 0x1B8C 595 #define MT6373_RG_LDO_VAUD18_RC3_OP_EN_ADDR 0x1B8C 596 #define MT6373_RG_LDO_VAUD18_RC4_OP_EN_ADDR 0x1B8C 597 #define MT6373_RG_LDO_VAUD18_RC5_OP_EN_ADDR 0x1B8C 598 #define MT6373_RG_LDO_VAUD18_RC6_OP_EN_ADDR 0x1B8C 599 #define MT6373_RG_LDO_VAUD18_RC7_OP_EN_ADDR 0x1B8C 600 #define MT6373_RG_LDO_VAUD18_RC8_OP_EN_ADDR 0x1B8D 601 #define MT6373_RG_LDO_VAUD18_RC9_OP_EN_ADDR 0x1B8D 602 #define MT6373_RG_LDO_VAUD18_RC10_OP_EN_ADDR 0x1B8D 603 #define MT6373_RG_LDO_VAUD18_RC11_OP_EN_ADDR 0x1B8D 604 #define MT6373_RG_LDO_VAUD18_RC12_OP_EN_ADDR 0x1B8D 605 #define MT6373_RG_LDO_VAUD18_RC13_OP_EN_ADDR 0x1B8D 606 #define MT6373_RG_LDO_VAUD18_HW0_OP_EN_ADDR 0x1B8E 607 #define MT6373_RG_LDO_VAUD18_HW1_OP_EN_ADDR 0x1B8E 608 #define MT6373_RG_LDO_VAUD18_HW2_OP_EN_ADDR 0x1B8E 609 #define MT6373_RG_LDO_VAUD18_HW3_OP_EN_ADDR 0x1B8E 610 #define MT6373_RG_LDO_VAUD18_HW4_OP_EN_ADDR 0x1B8E 611 #define MT6373_RG_LDO_VAUD18_HW5_OP_EN_ADDR 0x1B8E 612 #define MT6373_RG_LDO_VAUD18_HW6_OP_EN_ADDR 0x1B8E 613 #define MT6373_RG_LDO_VAUD18_SW_OP_EN_ADDR 0x1B8E 614 #define MT6373_RG_LDO_VAUD18_RC0_OP_CFG_ADDR 0x1B8F 615 #define MT6373_RG_LDO_VAUD18_RC1_OP_CFG_ADDR 0x1B8F 616 #define MT6373_RG_LDO_VAUD18_RC2_OP_CFG_ADDR 0x1B8F 617 #define MT6373_RG_LDO_VAUD18_RC3_OP_CFG_ADDR 0x1B8F 618 #define MT6373_RG_LDO_VAUD18_RC4_OP_CFG_ADDR 0x1B8F 619 #define MT6373_RG_LDO_VAUD18_RC5_OP_CFG_ADDR 0x1B8F 620 #define MT6373_RG_LDO_VAUD18_RC6_OP_CFG_ADDR 0x1B8F 621 #define MT6373_RG_LDO_VAUD18_RC7_OP_CFG_ADDR 0x1B8F 622 #define MT6373_RG_LDO_VAUD18_RC8_OP_CFG_ADDR 0x1B90 623 #define MT6373_RG_LDO_VAUD18_RC9_OP_CFG_ADDR 0x1B90 624 #define MT6373_RG_LDO_VAUD18_RC10_OP_CFG_ADDR 0x1B90 625 #define MT6373_RG_LDO_VAUD18_RC11_OP_CFG_ADDR 0x1B90 626 #define MT6373_RG_LDO_VAUD18_RC12_OP_CFG_ADDR 0x1B90 627 #define MT6373_RG_LDO_VAUD18_RC13_OP_CFG_ADDR 0x1B90 628 #define MT6373_RG_LDO_VAUD18_HW0_OP_CFG_ADDR 0x1B91 629 #define MT6373_RG_LDO_VAUD18_HW1_OP_CFG_ADDR 0x1B91 630 #define MT6373_RG_LDO_VAUD18_HW2_OP_CFG_ADDR 0x1B91 631 #define MT6373_RG_LDO_VAUD18_HW3_OP_CFG_ADDR 0x1B91 632 #define MT6373_RG_LDO_VAUD18_HW4_OP_CFG_ADDR 0x1B91 633 #define MT6373_RG_LDO_VAUD18_HW5_OP_CFG_ADDR 0x1B91 634 #define MT6373_RG_LDO_VAUD18_HW6_OP_CFG_ADDR 0x1B91 635 #define MT6373_RG_LDO_VAUD18_SW_OP_CFG_ADDR 0x1B91 636 #define MT6373_RG_LDO_VAUD18_RC0_OP_MODE_ADDR 0x1B92 637 #define MT6373_RG_LDO_VAUD18_RC1_OP_MODE_ADDR 0x1B92 638 #define MT6373_RG_LDO_VAUD18_RC2_OP_MODE_ADDR 0x1B92 639 #define MT6373_RG_LDO_VAUD18_RC3_OP_MODE_ADDR 0x1B92 640 #define MT6373_RG_LDO_VAUD18_RC4_OP_MODE_ADDR 0x1B92 641 #define MT6373_RG_LDO_VAUD18_RC5_OP_MODE_ADDR 0x1B92 642 #define MT6373_RG_LDO_VAUD18_RC6_OP_MODE_ADDR 0x1B92 643 #define MT6373_RG_LDO_VAUD18_RC7_OP_MODE_ADDR 0x1B92 644 #define MT6373_RG_LDO_VAUD18_RC8_OP_MODE_ADDR 0x1B93 645 #define MT6373_RG_LDO_VAUD18_RC9_OP_MODE_ADDR 0x1B93 646 #define MT6373_RG_LDO_VAUD18_RC10_OP_MODE_ADDR 0x1B93 647 #define MT6373_RG_LDO_VAUD18_RC11_OP_MODE_ADDR 0x1B93 648 #define MT6373_RG_LDO_VAUD18_RC12_OP_MODE_ADDR 0x1B93 649 #define MT6373_RG_LDO_VAUD18_RC13_OP_MODE_ADDR 0x1B93 650 #define MT6373_RG_LDO_VAUD18_HW0_OP_MODE_ADDR 0x1B94 651 #define MT6373_RG_LDO_VAUD18_HW1_OP_MODE_ADDR 0x1B94 652 #define MT6373_RG_LDO_VAUD18_HW2_OP_MODE_ADDR 0x1B94 653 #define MT6373_RG_LDO_VAUD18_HW3_OP_MODE_ADDR 0x1B94 654 #define MT6373_RG_LDO_VAUD18_HW4_OP_MODE_ADDR 0x1B94 655 #define MT6373_RG_LDO_VAUD18_HW5_OP_MODE_ADDR 0x1B94 656 #define MT6373_RG_LDO_VAUD18_HW6_OP_MODE_ADDR 0x1B94 657 #define MT6373_RG_LDO_VUSB_ONLV_EN_ADDR 0x1B96 658 #define MT6373_RG_LDO_VUSB_ONLV_EN_SHIFT 3 659 #define MT6373_RG_LDO_VUSB_RC0_OP_EN_ADDR 0x1B9A 660 #define MT6373_RG_LDO_VUSB_RC1_OP_EN_ADDR 0x1B9A 661 #define MT6373_RG_LDO_VUSB_RC2_OP_EN_ADDR 0x1B9A 662 #define MT6373_RG_LDO_VUSB_RC3_OP_EN_ADDR 0x1B9A 663 #define MT6373_RG_LDO_VUSB_RC4_OP_EN_ADDR 0x1B9A 664 #define MT6373_RG_LDO_VUSB_RC5_OP_EN_ADDR 0x1B9A 665 #define MT6373_RG_LDO_VUSB_RC6_OP_EN_ADDR 0x1B9A 666 #define MT6373_RG_LDO_VUSB_RC7_OP_EN_ADDR 0x1B9A 667 #define MT6373_RG_LDO_VUSB_RC8_OP_EN_ADDR 0x1B9B 668 #define MT6373_RG_LDO_VUSB_RC9_OP_EN_ADDR 0x1B9B 669 #define MT6373_RG_LDO_VUSB_RC10_OP_EN_ADDR 0x1B9B 670 #define MT6373_RG_LDO_VUSB_RC11_OP_EN_ADDR 0x1B9B 671 #define MT6373_RG_LDO_VUSB_RC12_OP_EN_ADDR 0x1B9B 672 #define MT6373_RG_LDO_VUSB_RC13_OP_EN_ADDR 0x1B9B 673 #define MT6373_RG_LDO_VUSB_HW0_OP_EN_ADDR 0x1B9C 674 #define MT6373_RG_LDO_VUSB_HW1_OP_EN_ADDR 0x1B9C 675 #define MT6373_RG_LDO_VUSB_HW2_OP_EN_ADDR 0x1B9C 676 #define MT6373_RG_LDO_VUSB_HW3_OP_EN_ADDR 0x1B9C 677 #define MT6373_RG_LDO_VUSB_HW4_OP_EN_ADDR 0x1B9C 678 #define MT6373_RG_LDO_VUSB_HW5_OP_EN_ADDR 0x1B9C 679 #define MT6373_RG_LDO_VUSB_HW6_OP_EN_ADDR 0x1B9C 680 #define MT6373_RG_LDO_VUSB_SW_OP_EN_ADDR 0x1B9C 681 #define MT6373_RG_LDO_VUSB_RC0_OP_CFG_ADDR 0x1B9D 682 #define MT6373_RG_LDO_VUSB_RC1_OP_CFG_ADDR 0x1B9D 683 #define MT6373_RG_LDO_VUSB_RC2_OP_CFG_ADDR 0x1B9D 684 #define MT6373_RG_LDO_VUSB_RC3_OP_CFG_ADDR 0x1B9D 685 #define MT6373_RG_LDO_VUSB_RC4_OP_CFG_ADDR 0x1B9D 686 #define MT6373_RG_LDO_VUSB_RC5_OP_CFG_ADDR 0x1B9D 687 #define MT6373_RG_LDO_VUSB_RC6_OP_CFG_ADDR 0x1B9D 688 #define MT6373_RG_LDO_VUSB_RC7_OP_CFG_ADDR 0x1B9D 689 #define MT6373_RG_LDO_VUSB_RC8_OP_CFG_ADDR 0x1B9E 690 #define MT6373_RG_LDO_VUSB_RC9_OP_CFG_ADDR 0x1B9E 691 #define MT6373_RG_LDO_VUSB_RC10_OP_CFG_ADDR 0x1B9E 692 #define MT6373_RG_LDO_VUSB_RC11_OP_CFG_ADDR 0x1B9E 693 #define MT6373_RG_LDO_VUSB_RC12_OP_CFG_ADDR 0x1B9E 694 #define MT6373_RG_LDO_VUSB_RC13_OP_CFG_ADDR 0x1B9E 695 #define MT6373_RG_LDO_VUSB_HW0_OP_CFG_ADDR 0x1B9F 696 #define MT6373_RG_LDO_VUSB_HW1_OP_CFG_ADDR 0x1B9F 697 #define MT6373_RG_LDO_VUSB_HW2_OP_CFG_ADDR 0x1B9F 698 #define MT6373_RG_LDO_VUSB_HW3_OP_CFG_ADDR 0x1B9F 699 #define MT6373_RG_LDO_VUSB_HW4_OP_CFG_ADDR 0x1B9F 700 #define MT6373_RG_LDO_VUSB_HW5_OP_CFG_ADDR 0x1B9F 701 #define MT6373_RG_LDO_VUSB_HW6_OP_CFG_ADDR 0x1B9F 702 #define MT6373_RG_LDO_VUSB_SW_OP_CFG_ADDR 0x1B9F 703 #define MT6373_RG_LDO_VUSB_RC0_OP_MODE_ADDR 0x1BA0 704 #define MT6373_RG_LDO_VUSB_RC1_OP_MODE_ADDR 0x1BA0 705 #define MT6373_RG_LDO_VUSB_RC2_OP_MODE_ADDR 0x1BA0 706 #define MT6373_RG_LDO_VUSB_RC3_OP_MODE_ADDR 0x1BA0 707 #define MT6373_RG_LDO_VUSB_RC4_OP_MODE_ADDR 0x1BA0 708 #define MT6373_RG_LDO_VUSB_RC5_OP_MODE_ADDR 0x1BA0 709 #define MT6373_RG_LDO_VUSB_RC6_OP_MODE_ADDR 0x1BA0 710 #define MT6373_RG_LDO_VUSB_RC7_OP_MODE_ADDR 0x1BA0 711 #define MT6373_RG_LDO_VUSB_RC8_OP_MODE_ADDR 0x1BA1 712 #define MT6373_RG_LDO_VUSB_RC9_OP_MODE_ADDR 0x1BA1 713 #define MT6373_RG_LDO_VUSB_RC10_OP_MODE_ADDR 0x1BA1 714 #define MT6373_RG_LDO_VUSB_RC11_OP_MODE_ADDR 0x1BA1 715 #define MT6373_RG_LDO_VUSB_RC12_OP_MODE_ADDR 0x1BA1 716 #define MT6373_RG_LDO_VUSB_RC13_OP_MODE_ADDR 0x1BA1 717 #define MT6373_RG_LDO_VUSB_HW0_OP_MODE_ADDR 0x1BA2 718 #define MT6373_RG_LDO_VUSB_HW1_OP_MODE_ADDR 0x1BA2 719 #define MT6373_RG_LDO_VUSB_HW2_OP_MODE_ADDR 0x1BA2 720 #define MT6373_RG_LDO_VUSB_HW3_OP_MODE_ADDR 0x1BA2 721 #define MT6373_RG_LDO_VUSB_HW4_OP_MODE_ADDR 0x1BA2 722 #define MT6373_RG_LDO_VUSB_HW5_OP_MODE_ADDR 0x1BA2 723 #define MT6373_RG_LDO_VUSB_HW6_OP_MODE_ADDR 0x1BA2 724 #define MT6373_RG_LDO_VAUX18_ONLV_EN_ADDR 0x1BA4 725 #define MT6373_RG_LDO_VAUX18_ONLV_EN_SHIFT 3 726 #define MT6373_RG_LDO_VAUX18_RC0_OP_EN_ADDR 0x1BA8 727 #define MT6373_RG_LDO_VAUX18_RC1_OP_EN_ADDR 0x1BA8 728 #define MT6373_RG_LDO_VAUX18_RC2_OP_EN_ADDR 0x1BA8 729 #define MT6373_RG_LDO_VAUX18_RC3_OP_EN_ADDR 0x1BA8 730 #define MT6373_RG_LDO_VAUX18_RC4_OP_EN_ADDR 0x1BA8 731 #define MT6373_RG_LDO_VAUX18_RC5_OP_EN_ADDR 0x1BA8 732 #define MT6373_RG_LDO_VAUX18_RC6_OP_EN_ADDR 0x1BA8 733 #define MT6373_RG_LDO_VAUX18_RC7_OP_EN_ADDR 0x1BA8 734 #define MT6373_RG_LDO_VAUX18_RC8_OP_EN_ADDR 0x1BA9 735 #define MT6373_RG_LDO_VAUX18_RC9_OP_EN_ADDR 0x1BA9 736 #define MT6373_RG_LDO_VAUX18_RC10_OP_EN_ADDR 0x1BA9 737 #define MT6373_RG_LDO_VAUX18_RC11_OP_EN_ADDR 0x1BA9 738 #define MT6373_RG_LDO_VAUX18_RC12_OP_EN_ADDR 0x1BA9 739 #define MT6373_RG_LDO_VAUX18_RC13_OP_EN_ADDR 0x1BA9 740 #define MT6373_RG_LDO_VAUX18_HW0_OP_EN_ADDR 0x1BAA 741 #define MT6373_RG_LDO_VAUX18_HW1_OP_EN_ADDR 0x1BAA 742 #define MT6373_RG_LDO_VAUX18_HW2_OP_EN_ADDR 0x1BAA 743 #define MT6373_RG_LDO_VAUX18_HW3_OP_EN_ADDR 0x1BAA 744 #define MT6373_RG_LDO_VAUX18_HW4_OP_EN_ADDR 0x1BAA 745 #define MT6373_RG_LDO_VAUX18_HW5_OP_EN_ADDR 0x1BAA 746 #define MT6373_RG_LDO_VAUX18_HW6_OP_EN_ADDR 0x1BAA 747 #define MT6373_RG_LDO_VAUX18_SW_OP_EN_ADDR 0x1BAA 748 #define MT6373_RG_LDO_VAUX18_RC0_OP_CFG_ADDR 0x1BAB 749 #define MT6373_RG_LDO_VAUX18_RC1_OP_CFG_ADDR 0x1BAB 750 #define MT6373_RG_LDO_VAUX18_RC2_OP_CFG_ADDR 0x1BAB 751 #define MT6373_RG_LDO_VAUX18_RC3_OP_CFG_ADDR 0x1BAB 752 #define MT6373_RG_LDO_VAUX18_RC4_OP_CFG_ADDR 0x1BAB 753 #define MT6373_RG_LDO_VAUX18_RC5_OP_CFG_ADDR 0x1BAB 754 #define MT6373_RG_LDO_VAUX18_RC6_OP_CFG_ADDR 0x1BAB 755 #define MT6373_RG_LDO_VAUX18_RC7_OP_CFG_ADDR 0x1BAB 756 #define MT6373_RG_LDO_VAUX18_RC8_OP_CFG_ADDR 0x1BAC 757 #define MT6373_RG_LDO_VAUX18_RC9_OP_CFG_ADDR 0x1BAC 758 #define MT6373_RG_LDO_VAUX18_RC10_OP_CFG_ADDR 0x1BAC 759 #define MT6373_RG_LDO_VAUX18_RC11_OP_CFG_ADDR 0x1BAC 760 #define MT6373_RG_LDO_VAUX18_RC12_OP_CFG_ADDR 0x1BAC 761 #define MT6373_RG_LDO_VAUX18_RC13_OP_CFG_ADDR 0x1BAC 762 #define MT6373_RG_LDO_VAUX18_HW0_OP_CFG_ADDR 0x1BAD 763 #define MT6373_RG_LDO_VAUX18_HW1_OP_CFG_ADDR 0x1BAD 764 #define MT6373_RG_LDO_VAUX18_HW2_OP_CFG_ADDR 0x1BAD 765 #define MT6373_RG_LDO_VAUX18_HW3_OP_CFG_ADDR 0x1BAD 766 #define MT6373_RG_LDO_VAUX18_HW4_OP_CFG_ADDR 0x1BAD 767 #define MT6373_RG_LDO_VAUX18_HW5_OP_CFG_ADDR 0x1BAD 768 #define MT6373_RG_LDO_VAUX18_HW6_OP_CFG_ADDR 0x1BAD 769 #define MT6373_RG_LDO_VAUX18_SW_OP_CFG_ADDR 0x1BAD 770 #define MT6373_RG_LDO_VAUX18_RC0_OP_MODE_ADDR 0x1BAE 771 #define MT6373_RG_LDO_VAUX18_RC1_OP_MODE_ADDR 0x1BAE 772 #define MT6373_RG_LDO_VAUX18_RC2_OP_MODE_ADDR 0x1BAE 773 #define MT6373_RG_LDO_VAUX18_RC3_OP_MODE_ADDR 0x1BAE 774 #define MT6373_RG_LDO_VAUX18_RC4_OP_MODE_ADDR 0x1BAE 775 #define MT6373_RG_LDO_VAUX18_RC5_OP_MODE_ADDR 0x1BAE 776 #define MT6373_RG_LDO_VAUX18_RC6_OP_MODE_ADDR 0x1BAE 777 #define MT6373_RG_LDO_VAUX18_RC7_OP_MODE_ADDR 0x1BAE 778 #define MT6373_RG_LDO_VAUX18_RC8_OP_MODE_ADDR 0x1BAF 779 #define MT6373_RG_LDO_VAUX18_RC9_OP_MODE_ADDR 0x1BAF 780 #define MT6373_RG_LDO_VAUX18_RC10_OP_MODE_ADDR 0x1BAF 781 #define MT6373_RG_LDO_VAUX18_RC11_OP_MODE_ADDR 0x1BAF 782 #define MT6373_RG_LDO_VAUX18_RC12_OP_MODE_ADDR 0x1BAF 783 #define MT6373_RG_LDO_VAUX18_RC13_OP_MODE_ADDR 0x1BAF 784 #define MT6373_RG_LDO_VAUX18_HW0_OP_MODE_ADDR 0x1BB0 785 #define MT6373_RG_LDO_VAUX18_HW1_OP_MODE_ADDR 0x1BB0 786 #define MT6373_RG_LDO_VAUX18_HW2_OP_MODE_ADDR 0x1BB0 787 #define MT6373_RG_LDO_VAUX18_HW3_OP_MODE_ADDR 0x1BB0 788 #define MT6373_RG_LDO_VAUX18_HW4_OP_MODE_ADDR 0x1BB0 789 #define MT6373_RG_LDO_VAUX18_HW5_OP_MODE_ADDR 0x1BB0 790 #define MT6373_RG_LDO_VAUX18_HW6_OP_MODE_ADDR 0x1BB0 791 #define MT6373_RG_LDO_VRF13_AIF_ONLV_EN_ADDR 0x1BB2 792 #define MT6373_RG_LDO_VRF13_AIF_ONLV_EN_SHIFT 3 793 #define MT6373_RG_LDO_VRF13_AIF_RC0_OP_EN_ADDR 0x1BB6 794 #define MT6373_RG_LDO_VRF13_AIF_RC1_OP_EN_ADDR 0x1BB6 795 #define MT6373_RG_LDO_VRF13_AIF_RC2_OP_EN_ADDR 0x1BB6 796 #define MT6373_RG_LDO_VRF13_AIF_RC3_OP_EN_ADDR 0x1BB6 797 #define MT6373_RG_LDO_VRF13_AIF_RC4_OP_EN_ADDR 0x1BB6 798 #define MT6373_RG_LDO_VRF13_AIF_RC5_OP_EN_ADDR 0x1BB6 799 #define MT6373_RG_LDO_VRF13_AIF_RC6_OP_EN_ADDR 0x1BB6 800 #define MT6373_RG_LDO_VRF13_AIF_RC7_OP_EN_ADDR 0x1BB6 801 #define MT6373_RG_LDO_VRF13_AIF_RC8_OP_EN_ADDR 0x1BB7 802 #define MT6373_RG_LDO_VRF13_AIF_RC9_OP_EN_ADDR 0x1BB7 803 #define MT6373_RG_LDO_VRF13_AIF_RC10_OP_EN_ADDR 0x1BB7 804 #define MT6373_RG_LDO_VRF13_AIF_RC11_OP_EN_ADDR 0x1BB7 805 #define MT6373_RG_LDO_VRF13_AIF_RC12_OP_EN_ADDR 0x1BB7 806 #define MT6373_RG_LDO_VRF13_AIF_RC13_OP_EN_ADDR 0x1BB7 807 #define MT6373_RG_LDO_VRF13_AIF_HW0_OP_EN_ADDR 0x1BB8 808 #define MT6373_RG_LDO_VRF13_AIF_HW1_OP_EN_ADDR 0x1BB8 809 #define MT6373_RG_LDO_VRF13_AIF_HW2_OP_EN_ADDR 0x1BB8 810 #define MT6373_RG_LDO_VRF13_AIF_HW3_OP_EN_ADDR 0x1BB8 811 #define MT6373_RG_LDO_VRF13_AIF_HW4_OP_EN_ADDR 0x1BB8 812 #define MT6373_RG_LDO_VRF13_AIF_HW5_OP_EN_ADDR 0x1BB8 813 #define MT6373_RG_LDO_VRF13_AIF_HW6_OP_EN_ADDR 0x1BB8 814 #define MT6373_RG_LDO_VRF13_AIF_SW_OP_EN_ADDR 0x1BB8 815 #define MT6373_RG_LDO_VRF13_AIF_RC0_OP_CFG_ADDR 0x1BB9 816 #define MT6373_RG_LDO_VRF13_AIF_RC1_OP_CFG_ADDR 0x1BB9 817 #define MT6373_RG_LDO_VRF13_AIF_RC2_OP_CFG_ADDR 0x1BB9 818 #define MT6373_RG_LDO_VRF13_AIF_RC3_OP_CFG_ADDR 0x1BB9 819 #define MT6373_RG_LDO_VRF13_AIF_RC4_OP_CFG_ADDR 0x1BB9 820 #define MT6373_RG_LDO_VRF13_AIF_RC5_OP_CFG_ADDR 0x1BB9 821 #define MT6373_RG_LDO_VRF13_AIF_RC6_OP_CFG_ADDR 0x1BB9 822 #define MT6373_RG_LDO_VRF13_AIF_RC7_OP_CFG_ADDR 0x1BB9 823 #define MT6373_RG_LDO_VRF13_AIF_RC8_OP_CFG_ADDR 0x1BBA 824 #define MT6373_RG_LDO_VRF13_AIF_RC9_OP_CFG_ADDR 0x1BBA 825 #define MT6373_RG_LDO_VRF13_AIF_RC10_OP_CFG_ADDR 0x1BBA 826 #define MT6373_RG_LDO_VRF13_AIF_RC11_OP_CFG_ADDR 0x1BBA 827 #define MT6373_RG_LDO_VRF13_AIF_RC12_OP_CFG_ADDR 0x1BBA 828 #define MT6373_RG_LDO_VRF13_AIF_RC13_OP_CFG_ADDR 0x1BBA 829 #define MT6373_RG_LDO_VRF13_AIF_HW0_OP_CFG_ADDR 0x1BBB 830 #define MT6373_RG_LDO_VRF13_AIF_HW1_OP_CFG_ADDR 0x1BBB 831 #define MT6373_RG_LDO_VRF13_AIF_HW2_OP_CFG_ADDR 0x1BBB 832 #define MT6373_RG_LDO_VRF13_AIF_HW3_OP_CFG_ADDR 0x1BBB 833 #define MT6373_RG_LDO_VRF13_AIF_HW4_OP_CFG_ADDR 0x1BBB 834 #define MT6373_RG_LDO_VRF13_AIF_HW5_OP_CFG_ADDR 0x1BBB 835 #define MT6373_RG_LDO_VRF13_AIF_HW6_OP_CFG_ADDR 0x1BBB 836 #define MT6373_RG_LDO_VRF13_AIF_SW_OP_CFG_ADDR 0x1BBB 837 #define MT6373_RG_LDO_VRF13_AIF_RC0_OP_MODE_ADDR 0x1BBC 838 #define MT6373_RG_LDO_VRF13_AIF_RC1_OP_MODE_ADDR 0x1BBC 839 #define MT6373_RG_LDO_VRF13_AIF_RC2_OP_MODE_ADDR 0x1BBC 840 #define MT6373_RG_LDO_VRF13_AIF_RC3_OP_MODE_ADDR 0x1BBC 841 #define MT6373_RG_LDO_VRF13_AIF_RC4_OP_MODE_ADDR 0x1BBC 842 #define MT6373_RG_LDO_VRF13_AIF_RC5_OP_MODE_ADDR 0x1BBC 843 #define MT6373_RG_LDO_VRF13_AIF_RC6_OP_MODE_ADDR 0x1BBC 844 #define MT6373_RG_LDO_VRF13_AIF_RC7_OP_MODE_ADDR 0x1BBC 845 #define MT6373_RG_LDO_VRF13_AIF_RC8_OP_MODE_ADDR 0x1BBD 846 #define MT6373_RG_LDO_VRF13_AIF_RC9_OP_MODE_ADDR 0x1BBD 847 #define MT6373_RG_LDO_VRF13_AIF_RC10_OP_MODE_ADDR 0x1BBD 848 #define MT6373_RG_LDO_VRF13_AIF_RC11_OP_MODE_ADDR 0x1BBD 849 #define MT6373_RG_LDO_VRF13_AIF_RC12_OP_MODE_ADDR 0x1BBD 850 #define MT6373_RG_LDO_VRF13_AIF_RC13_OP_MODE_ADDR 0x1BBD 851 #define MT6373_RG_LDO_VRF13_AIF_HW0_OP_MODE_ADDR 0x1BBE 852 #define MT6373_RG_LDO_VRF13_AIF_HW1_OP_MODE_ADDR 0x1BBE 853 #define MT6373_RG_LDO_VRF13_AIF_HW2_OP_MODE_ADDR 0x1BBE 854 #define MT6373_RG_LDO_VRF13_AIF_HW3_OP_MODE_ADDR 0x1BBE 855 #define MT6373_RG_LDO_VRF13_AIF_HW4_OP_MODE_ADDR 0x1BBE 856 #define MT6373_RG_LDO_VRF13_AIF_HW5_OP_MODE_ADDR 0x1BBE 857 #define MT6373_RG_LDO_VRF13_AIF_HW6_OP_MODE_ADDR 0x1BBE 858 #define MT6373_RG_LDO_VRF18_AIF_ONLV_EN_ADDR 0x1BC0 859 #define MT6373_RG_LDO_VRF18_AIF_ONLV_EN_SHIFT 3 860 #define MT6373_RG_LDO_VRF18_AIF_RC0_OP_EN_ADDR 0x1BC4 861 #define MT6373_RG_LDO_VRF18_AIF_RC1_OP_EN_ADDR 0x1BC4 862 #define MT6373_RG_LDO_VRF18_AIF_RC2_OP_EN_ADDR 0x1BC4 863 #define MT6373_RG_LDO_VRF18_AIF_RC3_OP_EN_ADDR 0x1BC4 864 #define MT6373_RG_LDO_VRF18_AIF_RC4_OP_EN_ADDR 0x1BC4 865 #define MT6373_RG_LDO_VRF18_AIF_RC5_OP_EN_ADDR 0x1BC4 866 #define MT6373_RG_LDO_VRF18_AIF_RC6_OP_EN_ADDR 0x1BC4 867 #define MT6373_RG_LDO_VRF18_AIF_RC7_OP_EN_ADDR 0x1BC4 868 #define MT6373_RG_LDO_VRF18_AIF_RC8_OP_EN_ADDR 0x1BC5 869 #define MT6373_RG_LDO_VRF18_AIF_RC9_OP_EN_ADDR 0x1BC5 870 #define MT6373_RG_LDO_VRF18_AIF_RC10_OP_EN_ADDR 0x1BC5 871 #define MT6373_RG_LDO_VRF18_AIF_RC11_OP_EN_ADDR 0x1BC5 872 #define MT6373_RG_LDO_VRF18_AIF_RC12_OP_EN_ADDR 0x1BC5 873 #define MT6373_RG_LDO_VRF18_AIF_RC13_OP_EN_ADDR 0x1BC5 874 #define MT6373_RG_LDO_VRF18_AIF_HW0_OP_EN_ADDR 0x1BC6 875 #define MT6373_RG_LDO_VRF18_AIF_HW1_OP_EN_ADDR 0x1BC6 876 #define MT6373_RG_LDO_VRF18_AIF_HW2_OP_EN_ADDR 0x1BC6 877 #define MT6373_RG_LDO_VRF18_AIF_HW3_OP_EN_ADDR 0x1BC6 878 #define MT6373_RG_LDO_VRF18_AIF_HW4_OP_EN_ADDR 0x1BC6 879 #define MT6373_RG_LDO_VRF18_AIF_HW5_OP_EN_ADDR 0x1BC6 880 #define MT6373_RG_LDO_VRF18_AIF_HW6_OP_EN_ADDR 0x1BC6 881 #define MT6373_RG_LDO_VRF18_AIF_SW_OP_EN_ADDR 0x1BC6 882 #define MT6373_RG_LDO_VRF18_AIF_RC0_OP_CFG_ADDR 0x1BC7 883 #define MT6373_RG_LDO_VRF18_AIF_RC1_OP_CFG_ADDR 0x1BC7 884 #define MT6373_RG_LDO_VRF18_AIF_RC2_OP_CFG_ADDR 0x1BC7 885 #define MT6373_RG_LDO_VRF18_AIF_RC3_OP_CFG_ADDR 0x1BC7 886 #define MT6373_RG_LDO_VRF18_AIF_RC4_OP_CFG_ADDR 0x1BC7 887 #define MT6373_RG_LDO_VRF18_AIF_RC5_OP_CFG_ADDR 0x1BC7 888 #define MT6373_RG_LDO_VRF18_AIF_RC6_OP_CFG_ADDR 0x1BC7 889 #define MT6373_RG_LDO_VRF18_AIF_RC7_OP_CFG_ADDR 0x1BC7 890 #define MT6373_RG_LDO_VRF18_AIF_RC8_OP_CFG_ADDR 0x1BC8 891 #define MT6373_RG_LDO_VRF18_AIF_RC9_OP_CFG_ADDR 0x1BC8 892 #define MT6373_RG_LDO_VRF18_AIF_RC10_OP_CFG_ADDR 0x1BC8 893 #define MT6373_RG_LDO_VRF18_AIF_RC11_OP_CFG_ADDR 0x1BC8 894 #define MT6373_RG_LDO_VRF18_AIF_RC12_OP_CFG_ADDR 0x1BC8 895 #define MT6373_RG_LDO_VRF18_AIF_RC13_OP_CFG_ADDR 0x1BC8 896 #define MT6373_RG_LDO_VRF18_AIF_HW0_OP_CFG_ADDR 0x1BC9 897 #define MT6373_RG_LDO_VRF18_AIF_HW1_OP_CFG_ADDR 0x1BC9 898 #define MT6373_RG_LDO_VRF18_AIF_HW2_OP_CFG_ADDR 0x1BC9 899 #define MT6373_RG_LDO_VRF18_AIF_HW3_OP_CFG_ADDR 0x1BC9 900 #define MT6373_RG_LDO_VRF18_AIF_HW4_OP_CFG_ADDR 0x1BC9 901 #define MT6373_RG_LDO_VRF18_AIF_HW5_OP_CFG_ADDR 0x1BC9 902 #define MT6373_RG_LDO_VRF18_AIF_HW6_OP_CFG_ADDR 0x1BC9 903 #define MT6373_RG_LDO_VRF18_AIF_SW_OP_CFG_ADDR 0x1BC9 904 #define MT6373_RG_LDO_VRF18_AIF_RC0_OP_MODE_ADDR 0x1BCA 905 #define MT6373_RG_LDO_VRF18_AIF_RC1_OP_MODE_ADDR 0x1BCA 906 #define MT6373_RG_LDO_VRF18_AIF_RC2_OP_MODE_ADDR 0x1BCA 907 #define MT6373_RG_LDO_VRF18_AIF_RC3_OP_MODE_ADDR 0x1BCA 908 #define MT6373_RG_LDO_VRF18_AIF_RC4_OP_MODE_ADDR 0x1BCA 909 #define MT6373_RG_LDO_VRF18_AIF_RC5_OP_MODE_ADDR 0x1BCA 910 #define MT6373_RG_LDO_VRF18_AIF_RC6_OP_MODE_ADDR 0x1BCA 911 #define MT6373_RG_LDO_VRF18_AIF_RC7_OP_MODE_ADDR 0x1BCA 912 #define MT6373_RG_LDO_VRF18_AIF_RC8_OP_MODE_ADDR 0x1BCB 913 #define MT6373_RG_LDO_VRF18_AIF_RC9_OP_MODE_ADDR 0x1BCB 914 #define MT6373_RG_LDO_VRF18_AIF_RC10_OP_MODE_ADDR 0x1BCB 915 #define MT6373_RG_LDO_VRF18_AIF_RC11_OP_MODE_ADDR 0x1BCB 916 #define MT6373_RG_LDO_VRF18_AIF_RC12_OP_MODE_ADDR 0x1BCB 917 #define MT6373_RG_LDO_VRF18_AIF_RC13_OP_MODE_ADDR 0x1BCB 918 #define MT6373_RG_LDO_VRF18_AIF_HW0_OP_MODE_ADDR 0x1BCC 919 #define MT6373_RG_LDO_VRF18_AIF_HW1_OP_MODE_ADDR 0x1BCC 920 #define MT6373_RG_LDO_VRF18_AIF_HW2_OP_MODE_ADDR 0x1BCC 921 #define MT6373_RG_LDO_VRF18_AIF_HW3_OP_MODE_ADDR 0x1BCC 922 #define MT6373_RG_LDO_VRF18_AIF_HW4_OP_MODE_ADDR 0x1BCC 923 #define MT6373_RG_LDO_VRF18_AIF_HW5_OP_MODE_ADDR 0x1BCC 924 #define MT6373_RG_LDO_VRF18_AIF_HW6_OP_MODE_ADDR 0x1BCC 925 #define MT6373_RG_LDO_VRFIO18_AIF_ONLV_EN_ADDR 0x1BCE 926 #define MT6373_RG_LDO_VRFIO18_AIF_ONLV_EN_SHIFT 3 927 #define MT6373_RG_LDO_VRFIO18_AIF_RC0_OP_EN_ADDR 0x1BD2 928 #define MT6373_RG_LDO_VRFIO18_AIF_RC1_OP_EN_ADDR 0x1BD2 929 #define MT6373_RG_LDO_VRFIO18_AIF_RC2_OP_EN_ADDR 0x1BD2 930 #define MT6373_RG_LDO_VRFIO18_AIF_RC3_OP_EN_ADDR 0x1BD2 931 #define MT6373_RG_LDO_VRFIO18_AIF_RC4_OP_EN_ADDR 0x1BD2 932 #define MT6373_RG_LDO_VRFIO18_AIF_RC5_OP_EN_ADDR 0x1BD2 933 #define MT6373_RG_LDO_VRFIO18_AIF_RC6_OP_EN_ADDR 0x1BD2 934 #define MT6373_RG_LDO_VRFIO18_AIF_RC7_OP_EN_ADDR 0x1BD2 935 #define MT6373_RG_LDO_VRFIO18_AIF_RC8_OP_EN_ADDR 0x1BD3 936 #define MT6373_RG_LDO_VRFIO18_AIF_RC9_OP_EN_ADDR 0x1BD3 937 #define MT6373_RG_LDO_VRFIO18_AIF_RC10_OP_EN_ADDR 0x1BD3 938 #define MT6373_RG_LDO_VRFIO18_AIF_RC11_OP_EN_ADDR 0x1BD3 939 #define MT6373_RG_LDO_VRFIO18_AIF_RC12_OP_EN_ADDR 0x1BD3 940 #define MT6373_RG_LDO_VRFIO18_AIF_RC13_OP_EN_ADDR 0x1BD3 941 #define MT6373_RG_LDO_VRFIO18_AIF_HW0_OP_EN_ADDR 0x1BD4 942 #define MT6373_RG_LDO_VRFIO18_AIF_HW1_OP_EN_ADDR 0x1BD4 943 #define MT6373_RG_LDO_VRFIO18_AIF_HW2_OP_EN_ADDR 0x1BD4 944 #define MT6373_RG_LDO_VRFIO18_AIF_HW3_OP_EN_ADDR 0x1BD4 945 #define MT6373_RG_LDO_VRFIO18_AIF_HW4_OP_EN_ADDR 0x1BD4 946 #define MT6373_RG_LDO_VRFIO18_AIF_HW5_OP_EN_ADDR 0x1BD4 947 #define MT6373_RG_LDO_VRFIO18_AIF_HW6_OP_EN_ADDR 0x1BD4 948 #define MT6373_RG_LDO_VRFIO18_AIF_SW_OP_EN_ADDR 0x1BD4 949 #define MT6373_RG_LDO_VRFIO18_AIF_RC0_OP_CFG_ADDR 0x1BD5 950 #define MT6373_RG_LDO_VRFIO18_AIF_RC1_OP_CFG_ADDR 0x1BD5 951 #define MT6373_RG_LDO_VRFIO18_AIF_RC2_OP_CFG_ADDR 0x1BD5 952 #define MT6373_RG_LDO_VRFIO18_AIF_RC3_OP_CFG_ADDR 0x1BD5 953 #define MT6373_RG_LDO_VRFIO18_AIF_RC4_OP_CFG_ADDR 0x1BD5 954 #define MT6373_RG_LDO_VRFIO18_AIF_RC5_OP_CFG_ADDR 0x1BD5 955 #define MT6373_RG_LDO_VRFIO18_AIF_RC6_OP_CFG_ADDR 0x1BD5 956 #define MT6373_RG_LDO_VRFIO18_AIF_RC7_OP_CFG_ADDR 0x1BD5 957 #define MT6373_RG_LDO_VRFIO18_AIF_RC8_OP_CFG_ADDR 0x1BD6 958 #define MT6373_RG_LDO_VRFIO18_AIF_RC9_OP_CFG_ADDR 0x1BD6 959 #define MT6373_RG_LDO_VRFIO18_AIF_RC10_OP_CFG_ADDR 0x1BD6 960 #define MT6373_RG_LDO_VRFIO18_AIF_RC11_OP_CFG_ADDR 0x1BD6 961 #define MT6373_RG_LDO_VRFIO18_AIF_RC12_OP_CFG_ADDR 0x1BD6 962 #define MT6373_RG_LDO_VRFIO18_AIF_RC13_OP_CFG_ADDR 0x1BD6 963 #define MT6373_RG_LDO_VRFIO18_AIF_HW0_OP_CFG_ADDR 0x1BD7 964 #define MT6373_RG_LDO_VRFIO18_AIF_HW1_OP_CFG_ADDR 0x1BD7 965 #define MT6373_RG_LDO_VRFIO18_AIF_HW2_OP_CFG_ADDR 0x1BD7 966 #define MT6373_RG_LDO_VRFIO18_AIF_HW3_OP_CFG_ADDR 0x1BD7 967 #define MT6373_RG_LDO_VRFIO18_AIF_HW4_OP_CFG_ADDR 0x1BD7 968 #define MT6373_RG_LDO_VRFIO18_AIF_HW5_OP_CFG_ADDR 0x1BD7 969 #define MT6373_RG_LDO_VRFIO18_AIF_HW6_OP_CFG_ADDR 0x1BD7 970 #define MT6373_RG_LDO_VRFIO18_AIF_SW_OP_CFG_ADDR 0x1BD7 971 #define MT6373_RG_LDO_VRFIO18_AIF_RC0_OP_MODE_ADDR 0x1BD8 972 #define MT6373_RG_LDO_VRFIO18_AIF_RC1_OP_MODE_ADDR 0x1BD8 973 #define MT6373_RG_LDO_VRFIO18_AIF_RC2_OP_MODE_ADDR 0x1BD8 974 #define MT6373_RG_LDO_VRFIO18_AIF_RC3_OP_MODE_ADDR 0x1BD8 975 #define MT6373_RG_LDO_VRFIO18_AIF_RC4_OP_MODE_ADDR 0x1BD8 976 #define MT6373_RG_LDO_VRFIO18_AIF_RC5_OP_MODE_ADDR 0x1BD8 977 #define MT6373_RG_LDO_VRFIO18_AIF_RC6_OP_MODE_ADDR 0x1BD8 978 #define MT6373_RG_LDO_VRFIO18_AIF_RC7_OP_MODE_ADDR 0x1BD8 979 #define MT6373_RG_LDO_VRFIO18_AIF_RC8_OP_MODE_ADDR 0x1BD9 980 #define MT6373_RG_LDO_VRFIO18_AIF_RC9_OP_MODE_ADDR 0x1BD9 981 #define MT6373_RG_LDO_VRFIO18_AIF_RC10_OP_MODE_ADDR 0x1BD9 982 #define MT6373_RG_LDO_VRFIO18_AIF_RC11_OP_MODE_ADDR 0x1BD9 983 #define MT6373_RG_LDO_VRFIO18_AIF_RC12_OP_MODE_ADDR 0x1BD9 984 #define MT6373_RG_LDO_VRFIO18_AIF_RC13_OP_MODE_ADDR 0x1BD9 985 #define MT6373_RG_LDO_VRFIO18_AIF_HW0_OP_MODE_ADDR 0x1BDA 986 #define MT6373_RG_LDO_VRFIO18_AIF_HW1_OP_MODE_ADDR 0x1BDA 987 #define MT6373_RG_LDO_VRFIO18_AIF_HW2_OP_MODE_ADDR 0x1BDA 988 #define MT6373_RG_LDO_VRFIO18_AIF_HW3_OP_MODE_ADDR 0x1BDA 989 #define MT6373_RG_LDO_VRFIO18_AIF_HW4_OP_MODE_ADDR 0x1BDA 990 #define MT6373_RG_LDO_VRFIO18_AIF_HW5_OP_MODE_ADDR 0x1BDA 991 #define MT6373_RG_LDO_VRFIO18_AIF_HW6_OP_MODE_ADDR 0x1BDA 992 #define MT6373_RG_LDO_VCN33_1_ONLV_EN_ADDR 0x1C08 993 #define MT6373_RG_LDO_VCN33_1_ONLV_EN_SHIFT 3 994 #define MT6373_RG_LDO_VCN33_1_RC0_OP_EN_ADDR 0x1C0C 995 #define MT6373_RG_LDO_VCN33_1_RC1_OP_EN_ADDR 0x1C0C 996 #define MT6373_RG_LDO_VCN33_1_RC2_OP_EN_ADDR 0x1C0C 997 #define MT6373_RG_LDO_VCN33_1_RC3_OP_EN_ADDR 0x1C0C 998 #define MT6373_RG_LDO_VCN33_1_RC4_OP_EN_ADDR 0x1C0C 999 #define MT6373_RG_LDO_VCN33_1_RC5_OP_EN_ADDR 0x1C0C 1000 #define MT6373_RG_LDO_VCN33_1_RC6_OP_EN_ADDR 0x1C0C 1001 #define MT6373_RG_LDO_VCN33_1_RC7_OP_EN_ADDR 0x1C0C 1002 #define MT6373_RG_LDO_VCN33_1_RC8_OP_EN_ADDR 0x1C0D 1003 #define MT6373_RG_LDO_VCN33_1_RC9_OP_EN_ADDR 0x1C0D 1004 #define MT6373_RG_LDO_VCN33_1_RC10_OP_EN_ADDR 0x1C0D 1005 #define MT6373_RG_LDO_VCN33_1_RC11_OP_EN_ADDR 0x1C0D 1006 #define MT6373_RG_LDO_VCN33_1_RC12_OP_EN_ADDR 0x1C0D 1007 #define MT6373_RG_LDO_VCN33_1_RC13_OP_EN_ADDR 0x1C0D 1008 #define MT6373_RG_LDO_VCN33_1_HW0_OP_EN_ADDR 0x1C0E 1009 #define MT6373_RG_LDO_VCN33_1_HW1_OP_EN_ADDR 0x1C0E 1010 #define MT6373_RG_LDO_VCN33_1_HW2_OP_EN_ADDR 0x1C0E 1011 #define MT6373_RG_LDO_VCN33_1_HW3_OP_EN_ADDR 0x1C0E 1012 #define MT6373_RG_LDO_VCN33_1_HW4_OP_EN_ADDR 0x1C0E 1013 #define MT6373_RG_LDO_VCN33_1_HW5_OP_EN_ADDR 0x1C0E 1014 #define MT6373_RG_LDO_VCN33_1_HW6_OP_EN_ADDR 0x1C0E 1015 #define MT6373_RG_LDO_VCN33_1_SW_OP_EN_ADDR 0x1C0E 1016 #define MT6373_RG_LDO_VCN33_1_RC0_OP_CFG_ADDR 0x1C0F 1017 #define MT6373_RG_LDO_VCN33_1_RC1_OP_CFG_ADDR 0x1C0F 1018 #define MT6373_RG_LDO_VCN33_1_RC2_OP_CFG_ADDR 0x1C0F 1019 #define MT6373_RG_LDO_VCN33_1_RC3_OP_CFG_ADDR 0x1C0F 1020 #define MT6373_RG_LDO_VCN33_1_RC4_OP_CFG_ADDR 0x1C0F 1021 #define MT6373_RG_LDO_VCN33_1_RC5_OP_CFG_ADDR 0x1C0F 1022 #define MT6373_RG_LDO_VCN33_1_RC6_OP_CFG_ADDR 0x1C0F 1023 #define MT6373_RG_LDO_VCN33_1_RC7_OP_CFG_ADDR 0x1C0F 1024 #define MT6373_RG_LDO_VCN33_1_RC8_OP_CFG_ADDR 0x1C10 1025 #define MT6373_RG_LDO_VCN33_1_RC9_OP_CFG_ADDR 0x1C10 1026 #define MT6373_RG_LDO_VCN33_1_RC10_OP_CFG_ADDR 0x1C10 1027 #define MT6373_RG_LDO_VCN33_1_RC11_OP_CFG_ADDR 0x1C10 1028 #define MT6373_RG_LDO_VCN33_1_RC12_OP_CFG_ADDR 0x1C10 1029 #define MT6373_RG_LDO_VCN33_1_RC13_OP_CFG_ADDR 0x1C10 1030 #define MT6373_RG_LDO_VCN33_1_HW0_OP_CFG_ADDR 0x1C11 1031 #define MT6373_RG_LDO_VCN33_1_HW1_OP_CFG_ADDR 0x1C11 1032 #define MT6373_RG_LDO_VCN33_1_HW2_OP_CFG_ADDR 0x1C11 1033 #define MT6373_RG_LDO_VCN33_1_HW3_OP_CFG_ADDR 0x1C11 1034 #define MT6373_RG_LDO_VCN33_1_HW4_OP_CFG_ADDR 0x1C11 1035 #define MT6373_RG_LDO_VCN33_1_HW5_OP_CFG_ADDR 0x1C11 1036 #define MT6373_RG_LDO_VCN33_1_HW6_OP_CFG_ADDR 0x1C11 1037 #define MT6373_RG_LDO_VCN33_1_SW_OP_CFG_ADDR 0x1C11 1038 #define MT6373_RG_LDO_VCN33_1_RC0_OP_MODE_ADDR 0x1C12 1039 #define MT6373_RG_LDO_VCN33_1_RC1_OP_MODE_ADDR 0x1C12 1040 #define MT6373_RG_LDO_VCN33_1_RC2_OP_MODE_ADDR 0x1C12 1041 #define MT6373_RG_LDO_VCN33_1_RC3_OP_MODE_ADDR 0x1C12 1042 #define MT6373_RG_LDO_VCN33_1_RC4_OP_MODE_ADDR 0x1C12 1043 #define MT6373_RG_LDO_VCN33_1_RC5_OP_MODE_ADDR 0x1C12 1044 #define MT6373_RG_LDO_VCN33_1_RC6_OP_MODE_ADDR 0x1C12 1045 #define MT6373_RG_LDO_VCN33_1_RC7_OP_MODE_ADDR 0x1C12 1046 #define MT6373_RG_LDO_VCN33_1_RC8_OP_MODE_ADDR 0x1C13 1047 #define MT6373_RG_LDO_VCN33_1_RC9_OP_MODE_ADDR 0x1C13 1048 #define MT6373_RG_LDO_VCN33_1_RC10_OP_MODE_ADDR 0x1C13 1049 #define MT6373_RG_LDO_VCN33_1_RC11_OP_MODE_ADDR 0x1C13 1050 #define MT6373_RG_LDO_VCN33_1_RC12_OP_MODE_ADDR 0x1C13 1051 #define MT6373_RG_LDO_VCN33_1_RC13_OP_MODE_ADDR 0x1C13 1052 #define MT6373_RG_LDO_VCN33_1_HW0_OP_MODE_ADDR 0x1C14 1053 #define MT6373_RG_LDO_VCN33_1_HW1_OP_MODE_ADDR 0x1C14 1054 #define MT6373_RG_LDO_VCN33_1_HW2_OP_MODE_ADDR 0x1C14 1055 #define MT6373_RG_LDO_VCN33_1_HW3_OP_MODE_ADDR 0x1C14 1056 #define MT6373_RG_LDO_VCN33_1_HW4_OP_MODE_ADDR 0x1C14 1057 #define MT6373_RG_LDO_VCN33_1_HW5_OP_MODE_ADDR 0x1C14 1058 #define MT6373_RG_LDO_VCN33_1_HW6_OP_MODE_ADDR 0x1C14 1059 #define MT6373_RG_LDO_VCN33_2_ONLV_EN_ADDR 0x1C16 1060 #define MT6373_RG_LDO_VCN33_2_ONLV_EN_SHIFT 3 1061 #define MT6373_RG_LDO_VCN33_2_RC0_OP_EN_ADDR 0x1C1A 1062 #define MT6373_RG_LDO_VCN33_2_RC1_OP_EN_ADDR 0x1C1A 1063 #define MT6373_RG_LDO_VCN33_2_RC2_OP_EN_ADDR 0x1C1A 1064 #define MT6373_RG_LDO_VCN33_2_RC3_OP_EN_ADDR 0x1C1A 1065 #define MT6373_RG_LDO_VCN33_2_RC4_OP_EN_ADDR 0x1C1A 1066 #define MT6373_RG_LDO_VCN33_2_RC5_OP_EN_ADDR 0x1C1A 1067 #define MT6373_RG_LDO_VCN33_2_RC6_OP_EN_ADDR 0x1C1A 1068 #define MT6373_RG_LDO_VCN33_2_RC7_OP_EN_ADDR 0x1C1A 1069 #define MT6373_RG_LDO_VCN33_2_RC8_OP_EN_ADDR 0x1C1B 1070 #define MT6373_RG_LDO_VCN33_2_RC9_OP_EN_ADDR 0x1C1B 1071 #define MT6373_RG_LDO_VCN33_2_RC10_OP_EN_ADDR 0x1C1B 1072 #define MT6373_RG_LDO_VCN33_2_RC11_OP_EN_ADDR 0x1C1B 1073 #define MT6373_RG_LDO_VCN33_2_RC12_OP_EN_ADDR 0x1C1B 1074 #define MT6373_RG_LDO_VCN33_2_RC13_OP_EN_ADDR 0x1C1B 1075 #define MT6373_RG_LDO_VCN33_2_HW0_OP_EN_ADDR 0x1C1C 1076 #define MT6373_RG_LDO_VCN33_2_HW1_OP_EN_ADDR 0x1C1C 1077 #define MT6373_RG_LDO_VCN33_2_HW2_OP_EN_ADDR 0x1C1C 1078 #define MT6373_RG_LDO_VCN33_2_HW3_OP_EN_ADDR 0x1C1C 1079 #define MT6373_RG_LDO_VCN33_2_HW4_OP_EN_ADDR 0x1C1C 1080 #define MT6373_RG_LDO_VCN33_2_HW5_OP_EN_ADDR 0x1C1C 1081 #define MT6373_RG_LDO_VCN33_2_HW6_OP_EN_ADDR 0x1C1C 1082 #define MT6373_RG_LDO_VCN33_2_SW_OP_EN_ADDR 0x1C1C 1083 #define MT6373_RG_LDO_VCN33_2_RC0_OP_CFG_ADDR 0x1C1D 1084 #define MT6373_RG_LDO_VCN33_2_RC1_OP_CFG_ADDR 0x1C1D 1085 #define MT6373_RG_LDO_VCN33_2_RC2_OP_CFG_ADDR 0x1C1D 1086 #define MT6373_RG_LDO_VCN33_2_RC3_OP_CFG_ADDR 0x1C1D 1087 #define MT6373_RG_LDO_VCN33_2_RC4_OP_CFG_ADDR 0x1C1D 1088 #define MT6373_RG_LDO_VCN33_2_RC5_OP_CFG_ADDR 0x1C1D 1089 #define MT6373_RG_LDO_VCN33_2_RC6_OP_CFG_ADDR 0x1C1D 1090 #define MT6373_RG_LDO_VCN33_2_RC7_OP_CFG_ADDR 0x1C1D 1091 #define MT6373_RG_LDO_VCN33_2_RC8_OP_CFG_ADDR 0x1C1E 1092 #define MT6373_RG_LDO_VCN33_2_RC9_OP_CFG_ADDR 0x1C1E 1093 #define MT6373_RG_LDO_VCN33_2_RC10_OP_CFG_ADDR 0x1C1E 1094 #define MT6373_RG_LDO_VCN33_2_RC11_OP_CFG_ADDR 0x1C1E 1095 #define MT6373_RG_LDO_VCN33_2_RC12_OP_CFG_ADDR 0x1C1E 1096 #define MT6373_RG_LDO_VCN33_2_RC13_OP_CFG_ADDR 0x1C1E 1097 #define MT6373_RG_LDO_VCN33_2_HW0_OP_CFG_ADDR 0x1C1F 1098 #define MT6373_RG_LDO_VCN33_2_HW1_OP_CFG_ADDR 0x1C1F 1099 #define MT6373_RG_LDO_VCN33_2_HW2_OP_CFG_ADDR 0x1C1F 1100 #define MT6373_RG_LDO_VCN33_2_HW3_OP_CFG_ADDR 0x1C1F 1101 #define MT6373_RG_LDO_VCN33_2_HW4_OP_CFG_ADDR 0x1C1F 1102 #define MT6373_RG_LDO_VCN33_2_HW5_OP_CFG_ADDR 0x1C1F 1103 #define MT6373_RG_LDO_VCN33_2_HW6_OP_CFG_ADDR 0x1C1F 1104 #define MT6373_RG_LDO_VCN33_2_SW_OP_CFG_ADDR 0x1C1F 1105 #define MT6373_RG_LDO_VCN33_2_RC0_OP_MODE_ADDR 0x1C20 1106 #define MT6373_RG_LDO_VCN33_2_RC1_OP_MODE_ADDR 0x1C20 1107 #define MT6373_RG_LDO_VCN33_2_RC2_OP_MODE_ADDR 0x1C20 1108 #define MT6373_RG_LDO_VCN33_2_RC3_OP_MODE_ADDR 0x1C20 1109 #define MT6373_RG_LDO_VCN33_2_RC4_OP_MODE_ADDR 0x1C20 1110 #define MT6373_RG_LDO_VCN33_2_RC5_OP_MODE_ADDR 0x1C20 1111 #define MT6373_RG_LDO_VCN33_2_RC6_OP_MODE_ADDR 0x1C20 1112 #define MT6373_RG_LDO_VCN33_2_RC7_OP_MODE_ADDR 0x1C20 1113 #define MT6373_RG_LDO_VCN33_2_RC8_OP_MODE_ADDR 0x1C21 1114 #define MT6373_RG_LDO_VCN33_2_RC9_OP_MODE_ADDR 0x1C21 1115 #define MT6373_RG_LDO_VCN33_2_RC10_OP_MODE_ADDR 0x1C21 1116 #define MT6373_RG_LDO_VCN33_2_RC11_OP_MODE_ADDR 0x1C21 1117 #define MT6373_RG_LDO_VCN33_2_RC12_OP_MODE_ADDR 0x1C21 1118 #define MT6373_RG_LDO_VCN33_2_RC13_OP_MODE_ADDR 0x1C21 1119 #define MT6373_RG_LDO_VCN33_2_HW0_OP_MODE_ADDR 0x1C22 1120 #define MT6373_RG_LDO_VCN33_2_HW1_OP_MODE_ADDR 0x1C22 1121 #define MT6373_RG_LDO_VCN33_2_HW2_OP_MODE_ADDR 0x1C22 1122 #define MT6373_RG_LDO_VCN33_2_HW3_OP_MODE_ADDR 0x1C22 1123 #define MT6373_RG_LDO_VCN33_2_HW4_OP_MODE_ADDR 0x1C22 1124 #define MT6373_RG_LDO_VCN33_2_HW5_OP_MODE_ADDR 0x1C22 1125 #define MT6373_RG_LDO_VCN33_2_HW6_OP_MODE_ADDR 0x1C22 1126 #define MT6373_RG_LDO_VCN33_3_ONLV_EN_ADDR 0x1C24 1127 #define MT6373_RG_LDO_VCN33_3_ONLV_EN_SHIFT 3 1128 #define MT6373_RG_LDO_VCN33_3_RC0_OP_EN_ADDR 0x1C28 1129 #define MT6373_RG_LDO_VCN33_3_RC1_OP_EN_ADDR 0x1C28 1130 #define MT6373_RG_LDO_VCN33_3_RC2_OP_EN_ADDR 0x1C28 1131 #define MT6373_RG_LDO_VCN33_3_RC3_OP_EN_ADDR 0x1C28 1132 #define MT6373_RG_LDO_VCN33_3_RC4_OP_EN_ADDR 0x1C28 1133 #define MT6373_RG_LDO_VCN33_3_RC5_OP_EN_ADDR 0x1C28 1134 #define MT6373_RG_LDO_VCN33_3_RC6_OP_EN_ADDR 0x1C28 1135 #define MT6373_RG_LDO_VCN33_3_RC7_OP_EN_ADDR 0x1C28 1136 #define MT6373_RG_LDO_VCN33_3_RC8_OP_EN_ADDR 0x1C29 1137 #define MT6373_RG_LDO_VCN33_3_RC9_OP_EN_ADDR 0x1C29 1138 #define MT6373_RG_LDO_VCN33_3_RC10_OP_EN_ADDR 0x1C29 1139 #define MT6373_RG_LDO_VCN33_3_RC11_OP_EN_ADDR 0x1C29 1140 #define MT6373_RG_LDO_VCN33_3_RC12_OP_EN_ADDR 0x1C29 1141 #define MT6373_RG_LDO_VCN33_3_RC13_OP_EN_ADDR 0x1C29 1142 #define MT6373_RG_LDO_VCN33_3_HW0_OP_EN_ADDR 0x1C2A 1143 #define MT6373_RG_LDO_VCN33_3_HW1_OP_EN_ADDR 0x1C2A 1144 #define MT6373_RG_LDO_VCN33_3_HW2_OP_EN_ADDR 0x1C2A 1145 #define MT6373_RG_LDO_VCN33_3_HW3_OP_EN_ADDR 0x1C2A 1146 #define MT6373_RG_LDO_VCN33_3_HW4_OP_EN_ADDR 0x1C2A 1147 #define MT6373_RG_LDO_VCN33_3_HW5_OP_EN_ADDR 0x1C2A 1148 #define MT6373_RG_LDO_VCN33_3_HW6_OP_EN_ADDR 0x1C2A 1149 #define MT6373_RG_LDO_VCN33_3_SW_OP_EN_ADDR 0x1C2A 1150 #define MT6373_RG_LDO_VCN33_3_RC0_OP_CFG_ADDR 0x1C2B 1151 #define MT6373_RG_LDO_VCN33_3_RC1_OP_CFG_ADDR 0x1C2B 1152 #define MT6373_RG_LDO_VCN33_3_RC2_OP_CFG_ADDR 0x1C2B 1153 #define MT6373_RG_LDO_VCN33_3_RC3_OP_CFG_ADDR 0x1C2B 1154 #define MT6373_RG_LDO_VCN33_3_RC4_OP_CFG_ADDR 0x1C2B 1155 #define MT6373_RG_LDO_VCN33_3_RC5_OP_CFG_ADDR 0x1C2B 1156 #define MT6373_RG_LDO_VCN33_3_RC6_OP_CFG_ADDR 0x1C2B 1157 #define MT6373_RG_LDO_VCN33_3_RC7_OP_CFG_ADDR 0x1C2B 1158 #define MT6373_RG_LDO_VCN33_3_RC8_OP_CFG_ADDR 0x1C2C 1159 #define MT6373_RG_LDO_VCN33_3_RC9_OP_CFG_ADDR 0x1C2C 1160 #define MT6373_RG_LDO_VCN33_3_RC10_OP_CFG_ADDR 0x1C2C 1161 #define MT6373_RG_LDO_VCN33_3_RC11_OP_CFG_ADDR 0x1C2C 1162 #define MT6373_RG_LDO_VCN33_3_RC12_OP_CFG_ADDR 0x1C2C 1163 #define MT6373_RG_LDO_VCN33_3_RC13_OP_CFG_ADDR 0x1C2C 1164 #define MT6373_RG_LDO_VCN33_3_HW0_OP_CFG_ADDR 0x1C2D 1165 #define MT6373_RG_LDO_VCN33_3_HW1_OP_CFG_ADDR 0x1C2D 1166 #define MT6373_RG_LDO_VCN33_3_HW2_OP_CFG_ADDR 0x1C2D 1167 #define MT6373_RG_LDO_VCN33_3_HW3_OP_CFG_ADDR 0x1C2D 1168 #define MT6373_RG_LDO_VCN33_3_HW4_OP_CFG_ADDR 0x1C2D 1169 #define MT6373_RG_LDO_VCN33_3_HW5_OP_CFG_ADDR 0x1C2D 1170 #define MT6373_RG_LDO_VCN33_3_HW6_OP_CFG_ADDR 0x1C2D 1171 #define MT6373_RG_LDO_VCN33_3_SW_OP_CFG_ADDR 0x1C2D 1172 #define MT6373_RG_LDO_VCN33_3_RC0_OP_MODE_ADDR 0x1C2E 1173 #define MT6373_RG_LDO_VCN33_3_RC1_OP_MODE_ADDR 0x1C2E 1174 #define MT6373_RG_LDO_VCN33_3_RC2_OP_MODE_ADDR 0x1C2E 1175 #define MT6373_RG_LDO_VCN33_3_RC3_OP_MODE_ADDR 0x1C2E 1176 #define MT6373_RG_LDO_VCN33_3_RC4_OP_MODE_ADDR 0x1C2E 1177 #define MT6373_RG_LDO_VCN33_3_RC5_OP_MODE_ADDR 0x1C2E 1178 #define MT6373_RG_LDO_VCN33_3_RC6_OP_MODE_ADDR 0x1C2E 1179 #define MT6373_RG_LDO_VCN33_3_RC7_OP_MODE_ADDR 0x1C2E 1180 #define MT6373_RG_LDO_VCN33_3_RC8_OP_MODE_ADDR 0x1C2F 1181 #define MT6373_RG_LDO_VCN33_3_RC9_OP_MODE_ADDR 0x1C2F 1182 #define MT6373_RG_LDO_VCN33_3_RC10_OP_MODE_ADDR 0x1C2F 1183 #define MT6373_RG_LDO_VCN33_3_RC11_OP_MODE_ADDR 0x1C2F 1184 #define MT6373_RG_LDO_VCN33_3_RC12_OP_MODE_ADDR 0x1C2F 1185 #define MT6373_RG_LDO_VCN33_3_RC13_OP_MODE_ADDR 0x1C2F 1186 #define MT6373_RG_LDO_VCN33_3_HW0_OP_MODE_ADDR 0x1C30 1187 #define MT6373_RG_LDO_VCN33_3_HW1_OP_MODE_ADDR 0x1C30 1188 #define MT6373_RG_LDO_VCN33_3_HW2_OP_MODE_ADDR 0x1C30 1189 #define MT6373_RG_LDO_VCN33_3_HW3_OP_MODE_ADDR 0x1C30 1190 #define MT6373_RG_LDO_VCN33_3_HW4_OP_MODE_ADDR 0x1C30 1191 #define MT6373_RG_LDO_VCN33_3_HW5_OP_MODE_ADDR 0x1C30 1192 #define MT6373_RG_LDO_VCN33_3_HW6_OP_MODE_ADDR 0x1C30 1193 #define MT6373_RG_LDO_VCN18IO_ONLV_EN_ADDR 0x1C32 1194 #define MT6373_RG_LDO_VCN18IO_ONLV_EN_SHIFT 3 1195 #define MT6373_RG_LDO_VCN18IO_RC0_OP_EN_ADDR 0x1C36 1196 #define MT6373_RG_LDO_VCN18IO_RC1_OP_EN_ADDR 0x1C36 1197 #define MT6373_RG_LDO_VCN18IO_RC2_OP_EN_ADDR 0x1C36 1198 #define MT6373_RG_LDO_VCN18IO_RC3_OP_EN_ADDR 0x1C36 1199 #define MT6373_RG_LDO_VCN18IO_RC4_OP_EN_ADDR 0x1C36 1200 #define MT6373_RG_LDO_VCN18IO_RC5_OP_EN_ADDR 0x1C36 1201 #define MT6373_RG_LDO_VCN18IO_RC6_OP_EN_ADDR 0x1C36 1202 #define MT6373_RG_LDO_VCN18IO_RC7_OP_EN_ADDR 0x1C36 1203 #define MT6373_RG_LDO_VCN18IO_RC8_OP_EN_ADDR 0x1C37 1204 #define MT6373_RG_LDO_VCN18IO_RC9_OP_EN_ADDR 0x1C37 1205 #define MT6373_RG_LDO_VCN18IO_RC10_OP_EN_ADDR 0x1C37 1206 #define MT6373_RG_LDO_VCN18IO_RC11_OP_EN_ADDR 0x1C37 1207 #define MT6373_RG_LDO_VCN18IO_RC12_OP_EN_ADDR 0x1C37 1208 #define MT6373_RG_LDO_VCN18IO_RC13_OP_EN_ADDR 0x1C37 1209 #define MT6373_RG_LDO_VCN18IO_HW0_OP_EN_ADDR 0x1C38 1210 #define MT6373_RG_LDO_VCN18IO_HW1_OP_EN_ADDR 0x1C38 1211 #define MT6373_RG_LDO_VCN18IO_HW2_OP_EN_ADDR 0x1C38 1212 #define MT6373_RG_LDO_VCN18IO_HW3_OP_EN_ADDR 0x1C38 1213 #define MT6373_RG_LDO_VCN18IO_HW4_OP_EN_ADDR 0x1C38 1214 #define MT6373_RG_LDO_VCN18IO_HW5_OP_EN_ADDR 0x1C38 1215 #define MT6373_RG_LDO_VCN18IO_HW6_OP_EN_ADDR 0x1C38 1216 #define MT6373_RG_LDO_VCN18IO_SW_OP_EN_ADDR 0x1C38 1217 #define MT6373_RG_LDO_VCN18IO_RC0_OP_CFG_ADDR 0x1C39 1218 #define MT6373_RG_LDO_VCN18IO_RC1_OP_CFG_ADDR 0x1C39 1219 #define MT6373_RG_LDO_VCN18IO_RC2_OP_CFG_ADDR 0x1C39 1220 #define MT6373_RG_LDO_VCN18IO_RC3_OP_CFG_ADDR 0x1C39 1221 #define MT6373_RG_LDO_VCN18IO_RC4_OP_CFG_ADDR 0x1C39 1222 #define MT6373_RG_LDO_VCN18IO_RC5_OP_CFG_ADDR 0x1C39 1223 #define MT6373_RG_LDO_VCN18IO_RC6_OP_CFG_ADDR 0x1C39 1224 #define MT6373_RG_LDO_VCN18IO_RC7_OP_CFG_ADDR 0x1C39 1225 #define MT6373_RG_LDO_VCN18IO_RC8_OP_CFG_ADDR 0x1C3A 1226 #define MT6373_RG_LDO_VCN18IO_RC9_OP_CFG_ADDR 0x1C3A 1227 #define MT6373_RG_LDO_VCN18IO_RC10_OP_CFG_ADDR 0x1C3A 1228 #define MT6373_RG_LDO_VCN18IO_RC11_OP_CFG_ADDR 0x1C3A 1229 #define MT6373_RG_LDO_VCN18IO_RC12_OP_CFG_ADDR 0x1C3A 1230 #define MT6373_RG_LDO_VCN18IO_RC13_OP_CFG_ADDR 0x1C3A 1231 #define MT6373_RG_LDO_VCN18IO_HW0_OP_CFG_ADDR 0x1C3B 1232 #define MT6373_RG_LDO_VCN18IO_HW1_OP_CFG_ADDR 0x1C3B 1233 #define MT6373_RG_LDO_VCN18IO_HW2_OP_CFG_ADDR 0x1C3B 1234 #define MT6373_RG_LDO_VCN18IO_HW3_OP_CFG_ADDR 0x1C3B 1235 #define MT6373_RG_LDO_VCN18IO_HW4_OP_CFG_ADDR 0x1C3B 1236 #define MT6373_RG_LDO_VCN18IO_HW5_OP_CFG_ADDR 0x1C3B 1237 #define MT6373_RG_LDO_VCN18IO_HW6_OP_CFG_ADDR 0x1C3B 1238 #define MT6373_RG_LDO_VCN18IO_SW_OP_CFG_ADDR 0x1C3B 1239 #define MT6373_RG_LDO_VCN18IO_RC0_OP_MODE_ADDR 0x1C3C 1240 #define MT6373_RG_LDO_VCN18IO_RC1_OP_MODE_ADDR 0x1C3C 1241 #define MT6373_RG_LDO_VCN18IO_RC2_OP_MODE_ADDR 0x1C3C 1242 #define MT6373_RG_LDO_VCN18IO_RC3_OP_MODE_ADDR 0x1C3C 1243 #define MT6373_RG_LDO_VCN18IO_RC4_OP_MODE_ADDR 0x1C3C 1244 #define MT6373_RG_LDO_VCN18IO_RC5_OP_MODE_ADDR 0x1C3C 1245 #define MT6373_RG_LDO_VCN18IO_RC6_OP_MODE_ADDR 0x1C3C 1246 #define MT6373_RG_LDO_VCN18IO_RC7_OP_MODE_ADDR 0x1C3C 1247 #define MT6373_RG_LDO_VCN18IO_RC8_OP_MODE_ADDR 0x1C3D 1248 #define MT6373_RG_LDO_VCN18IO_RC9_OP_MODE_ADDR 0x1C3D 1249 #define MT6373_RG_LDO_VCN18IO_RC10_OP_MODE_ADDR 0x1C3D 1250 #define MT6373_RG_LDO_VCN18IO_RC11_OP_MODE_ADDR 0x1C3D 1251 #define MT6373_RG_LDO_VCN18IO_RC12_OP_MODE_ADDR 0x1C3D 1252 #define MT6373_RG_LDO_VCN18IO_RC13_OP_MODE_ADDR 0x1C3D 1253 #define MT6373_RG_LDO_VCN18IO_HW0_OP_MODE_ADDR 0x1C3E 1254 #define MT6373_RG_LDO_VCN18IO_HW1_OP_MODE_ADDR 0x1C3E 1255 #define MT6373_RG_LDO_VCN18IO_HW2_OP_MODE_ADDR 0x1C3E 1256 #define MT6373_RG_LDO_VCN18IO_HW3_OP_MODE_ADDR 0x1C3E 1257 #define MT6373_RG_LDO_VCN18IO_HW4_OP_MODE_ADDR 0x1C3E 1258 #define MT6373_RG_LDO_VCN18IO_HW5_OP_MODE_ADDR 0x1C3E 1259 #define MT6373_RG_LDO_VCN18IO_HW6_OP_MODE_ADDR 0x1C3E 1260 #define MT6373_RG_LDO_VRF09_AIF_ONLV_EN_ADDR 0x1C40 1261 #define MT6373_RG_LDO_VRF09_AIF_ONLV_EN_SHIFT 3 1262 #define MT6373_RG_LDO_VRF09_AIF_RC0_OP_EN_ADDR 0x1C44 1263 #define MT6373_RG_LDO_VRF09_AIF_RC1_OP_EN_ADDR 0x1C44 1264 #define MT6373_RG_LDO_VRF09_AIF_RC2_OP_EN_ADDR 0x1C44 1265 #define MT6373_RG_LDO_VRF09_AIF_RC3_OP_EN_ADDR 0x1C44 1266 #define MT6373_RG_LDO_VRF09_AIF_RC4_OP_EN_ADDR 0x1C44 1267 #define MT6373_RG_LDO_VRF09_AIF_RC5_OP_EN_ADDR 0x1C44 1268 #define MT6373_RG_LDO_VRF09_AIF_RC6_OP_EN_ADDR 0x1C44 1269 #define MT6373_RG_LDO_VRF09_AIF_RC7_OP_EN_ADDR 0x1C44 1270 #define MT6373_RG_LDO_VRF09_AIF_RC8_OP_EN_ADDR 0x1C45 1271 #define MT6373_RG_LDO_VRF09_AIF_RC9_OP_EN_ADDR 0x1C45 1272 #define MT6373_RG_LDO_VRF09_AIF_RC10_OP_EN_ADDR 0x1C45 1273 #define MT6373_RG_LDO_VRF09_AIF_RC11_OP_EN_ADDR 0x1C45 1274 #define MT6373_RG_LDO_VRF09_AIF_RC12_OP_EN_ADDR 0x1C45 1275 #define MT6373_RG_LDO_VRF09_AIF_RC13_OP_EN_ADDR 0x1C45 1276 #define MT6373_RG_LDO_VRF09_AIF_HW0_OP_EN_ADDR 0x1C46 1277 #define MT6373_RG_LDO_VRF09_AIF_HW1_OP_EN_ADDR 0x1C46 1278 #define MT6373_RG_LDO_VRF09_AIF_HW2_OP_EN_ADDR 0x1C46 1279 #define MT6373_RG_LDO_VRF09_AIF_HW3_OP_EN_ADDR 0x1C46 1280 #define MT6373_RG_LDO_VRF09_AIF_HW4_OP_EN_ADDR 0x1C46 1281 #define MT6373_RG_LDO_VRF09_AIF_HW5_OP_EN_ADDR 0x1C46 1282 #define MT6373_RG_LDO_VRF09_AIF_HW6_OP_EN_ADDR 0x1C46 1283 #define MT6373_RG_LDO_VRF09_AIF_SW_OP_EN_ADDR 0x1C46 1284 #define MT6373_RG_LDO_VRF09_AIF_RC0_OP_CFG_ADDR 0x1C47 1285 #define MT6373_RG_LDO_VRF09_AIF_RC1_OP_CFG_ADDR 0x1C47 1286 #define MT6373_RG_LDO_VRF09_AIF_RC2_OP_CFG_ADDR 0x1C47 1287 #define MT6373_RG_LDO_VRF09_AIF_RC3_OP_CFG_ADDR 0x1C47 1288 #define MT6373_RG_LDO_VRF09_AIF_RC4_OP_CFG_ADDR 0x1C47 1289 #define MT6373_RG_LDO_VRF09_AIF_RC5_OP_CFG_ADDR 0x1C47 1290 #define MT6373_RG_LDO_VRF09_AIF_RC6_OP_CFG_ADDR 0x1C47 1291 #define MT6373_RG_LDO_VRF09_AIF_RC7_OP_CFG_ADDR 0x1C47 1292 #define MT6373_RG_LDO_VRF09_AIF_RC8_OP_CFG_ADDR 0x1C48 1293 #define MT6373_RG_LDO_VRF09_AIF_RC9_OP_CFG_ADDR 0x1C48 1294 #define MT6373_RG_LDO_VRF09_AIF_RC10_OP_CFG_ADDR 0x1C48 1295 #define MT6373_RG_LDO_VRF09_AIF_RC11_OP_CFG_ADDR 0x1C48 1296 #define MT6373_RG_LDO_VRF09_AIF_RC12_OP_CFG_ADDR 0x1C48 1297 #define MT6373_RG_LDO_VRF09_AIF_RC13_OP_CFG_ADDR 0x1C48 1298 #define MT6373_RG_LDO_VRF09_AIF_HW0_OP_CFG_ADDR 0x1C49 1299 #define MT6373_RG_LDO_VRF09_AIF_HW1_OP_CFG_ADDR 0x1C49 1300 #define MT6373_RG_LDO_VRF09_AIF_HW2_OP_CFG_ADDR 0x1C49 1301 #define MT6373_RG_LDO_VRF09_AIF_HW3_OP_CFG_ADDR 0x1C49 1302 #define MT6373_RG_LDO_VRF09_AIF_HW4_OP_CFG_ADDR 0x1C49 1303 #define MT6373_RG_LDO_VRF09_AIF_HW5_OP_CFG_ADDR 0x1C49 1304 #define MT6373_RG_LDO_VRF09_AIF_HW6_OP_CFG_ADDR 0x1C49 1305 #define MT6373_RG_LDO_VRF09_AIF_SW_OP_CFG_ADDR 0x1C49 1306 #define MT6373_RG_LDO_VRF09_AIF_RC0_OP_MODE_ADDR 0x1C4A 1307 #define MT6373_RG_LDO_VRF09_AIF_RC1_OP_MODE_ADDR 0x1C4A 1308 #define MT6373_RG_LDO_VRF09_AIF_RC2_OP_MODE_ADDR 0x1C4A 1309 #define MT6373_RG_LDO_VRF09_AIF_RC3_OP_MODE_ADDR 0x1C4A 1310 #define MT6373_RG_LDO_VRF09_AIF_RC4_OP_MODE_ADDR 0x1C4A 1311 #define MT6373_RG_LDO_VRF09_AIF_RC5_OP_MODE_ADDR 0x1C4A 1312 #define MT6373_RG_LDO_VRF09_AIF_RC6_OP_MODE_ADDR 0x1C4A 1313 #define MT6373_RG_LDO_VRF09_AIF_RC7_OP_MODE_ADDR 0x1C4A 1314 #define MT6373_RG_LDO_VRF09_AIF_RC8_OP_MODE_ADDR 0x1C4B 1315 #define MT6373_RG_LDO_VRF09_AIF_RC9_OP_MODE_ADDR 0x1C4B 1316 #define MT6373_RG_LDO_VRF09_AIF_RC10_OP_MODE_ADDR 0x1C4B 1317 #define MT6373_RG_LDO_VRF09_AIF_RC11_OP_MODE_ADDR 0x1C4B 1318 #define MT6373_RG_LDO_VRF09_AIF_RC12_OP_MODE_ADDR 0x1C4B 1319 #define MT6373_RG_LDO_VRF09_AIF_RC13_OP_MODE_ADDR 0x1C4B 1320 #define MT6373_RG_LDO_VRF09_AIF_HW0_OP_MODE_ADDR 0x1C4C 1321 #define MT6373_RG_LDO_VRF09_AIF_HW1_OP_MODE_ADDR 0x1C4C 1322 #define MT6373_RG_LDO_VRF09_AIF_HW2_OP_MODE_ADDR 0x1C4C 1323 #define MT6373_RG_LDO_VRF09_AIF_HW3_OP_MODE_ADDR 0x1C4C 1324 #define MT6373_RG_LDO_VRF09_AIF_HW4_OP_MODE_ADDR 0x1C4C 1325 #define MT6373_RG_LDO_VRF09_AIF_HW5_OP_MODE_ADDR 0x1C4C 1326 #define MT6373_RG_LDO_VRF09_AIF_HW6_OP_MODE_ADDR 0x1C4C 1327 #define MT6373_RG_LDO_VRF12_AIF_ONLV_EN_ADDR 0x1C4E 1328 #define MT6373_RG_LDO_VRF12_AIF_ONLV_EN_SHIFT 3 1329 #define MT6373_RG_LDO_VRF12_AIF_RC0_OP_EN_ADDR 0x1C52 1330 #define MT6373_RG_LDO_VRF12_AIF_RC1_OP_EN_ADDR 0x1C52 1331 #define MT6373_RG_LDO_VRF12_AIF_RC2_OP_EN_ADDR 0x1C52 1332 #define MT6373_RG_LDO_VRF12_AIF_RC3_OP_EN_ADDR 0x1C52 1333 #define MT6373_RG_LDO_VRF12_AIF_RC4_OP_EN_ADDR 0x1C52 1334 #define MT6373_RG_LDO_VRF12_AIF_RC5_OP_EN_ADDR 0x1C52 1335 #define MT6373_RG_LDO_VRF12_AIF_RC6_OP_EN_ADDR 0x1C52 1336 #define MT6373_RG_LDO_VRF12_AIF_RC7_OP_EN_ADDR 0x1C52 1337 #define MT6373_RG_LDO_VRF12_AIF_RC8_OP_EN_ADDR 0x1C53 1338 #define MT6373_RG_LDO_VRF12_AIF_RC9_OP_EN_ADDR 0x1C53 1339 #define MT6373_RG_LDO_VRF12_AIF_RC10_OP_EN_ADDR 0x1C53 1340 #define MT6373_RG_LDO_VRF12_AIF_RC11_OP_EN_ADDR 0x1C53 1341 #define MT6373_RG_LDO_VRF12_AIF_RC12_OP_EN_ADDR 0x1C53 1342 #define MT6373_RG_LDO_VRF12_AIF_RC13_OP_EN_ADDR 0x1C53 1343 #define MT6373_RG_LDO_VRF12_AIF_HW0_OP_EN_ADDR 0x1C54 1344 #define MT6373_RG_LDO_VRF12_AIF_HW1_OP_EN_ADDR 0x1C54 1345 #define MT6373_RG_LDO_VRF12_AIF_HW2_OP_EN_ADDR 0x1C54 1346 #define MT6373_RG_LDO_VRF12_AIF_HW3_OP_EN_ADDR 0x1C54 1347 #define MT6373_RG_LDO_VRF12_AIF_HW4_OP_EN_ADDR 0x1C54 1348 #define MT6373_RG_LDO_VRF12_AIF_HW5_OP_EN_ADDR 0x1C54 1349 #define MT6373_RG_LDO_VRF12_AIF_HW6_OP_EN_ADDR 0x1C54 1350 #define MT6373_RG_LDO_VRF12_AIF_SW_OP_EN_ADDR 0x1C54 1351 #define MT6373_RG_LDO_VRF12_AIF_RC0_OP_CFG_ADDR 0x1C55 1352 #define MT6373_RG_LDO_VRF12_AIF_RC1_OP_CFG_ADDR 0x1C55 1353 #define MT6373_RG_LDO_VRF12_AIF_RC2_OP_CFG_ADDR 0x1C55 1354 #define MT6373_RG_LDO_VRF12_AIF_RC3_OP_CFG_ADDR 0x1C55 1355 #define MT6373_RG_LDO_VRF12_AIF_RC4_OP_CFG_ADDR 0x1C55 1356 #define MT6373_RG_LDO_VRF12_AIF_RC5_OP_CFG_ADDR 0x1C55 1357 #define MT6373_RG_LDO_VRF12_AIF_RC6_OP_CFG_ADDR 0x1C55 1358 #define MT6373_RG_LDO_VRF12_AIF_RC7_OP_CFG_ADDR 0x1C55 1359 #define MT6373_RG_LDO_VRF12_AIF_RC8_OP_CFG_ADDR 0x1C56 1360 #define MT6373_RG_LDO_VRF12_AIF_RC9_OP_CFG_ADDR 0x1C56 1361 #define MT6373_RG_LDO_VRF12_AIF_RC10_OP_CFG_ADDR 0x1C56 1362 #define MT6373_RG_LDO_VRF12_AIF_RC11_OP_CFG_ADDR 0x1C56 1363 #define MT6373_RG_LDO_VRF12_AIF_RC12_OP_CFG_ADDR 0x1C56 1364 #define MT6373_RG_LDO_VRF12_AIF_RC13_OP_CFG_ADDR 0x1C56 1365 #define MT6373_RG_LDO_VRF12_AIF_HW0_OP_CFG_ADDR 0x1C57 1366 #define MT6373_RG_LDO_VRF12_AIF_HW1_OP_CFG_ADDR 0x1C57 1367 #define MT6373_RG_LDO_VRF12_AIF_HW2_OP_CFG_ADDR 0x1C57 1368 #define MT6373_RG_LDO_VRF12_AIF_HW3_OP_CFG_ADDR 0x1C57 1369 #define MT6373_RG_LDO_VRF12_AIF_HW4_OP_CFG_ADDR 0x1C57 1370 #define MT6373_RG_LDO_VRF12_AIF_HW5_OP_CFG_ADDR 0x1C57 1371 #define MT6373_RG_LDO_VRF12_AIF_HW6_OP_CFG_ADDR 0x1C57 1372 #define MT6373_RG_LDO_VRF12_AIF_SW_OP_CFG_ADDR 0x1C57 1373 #define MT6373_RG_LDO_VRF12_AIF_RC0_OP_MODE_ADDR 0x1C58 1374 #define MT6373_RG_LDO_VRF12_AIF_RC1_OP_MODE_ADDR 0x1C58 1375 #define MT6373_RG_LDO_VRF12_AIF_RC2_OP_MODE_ADDR 0x1C58 1376 #define MT6373_RG_LDO_VRF12_AIF_RC3_OP_MODE_ADDR 0x1C58 1377 #define MT6373_RG_LDO_VRF12_AIF_RC4_OP_MODE_ADDR 0x1C58 1378 #define MT6373_RG_LDO_VRF12_AIF_RC5_OP_MODE_ADDR 0x1C58 1379 #define MT6373_RG_LDO_VRF12_AIF_RC6_OP_MODE_ADDR 0x1C58 1380 #define MT6373_RG_LDO_VRF12_AIF_RC7_OP_MODE_ADDR 0x1C58 1381 #define MT6373_RG_LDO_VRF12_AIF_RC8_OP_MODE_ADDR 0x1C59 1382 #define MT6373_RG_LDO_VRF12_AIF_RC9_OP_MODE_ADDR 0x1C59 1383 #define MT6373_RG_LDO_VRF12_AIF_RC10_OP_MODE_ADDR 0x1C59 1384 #define MT6373_RG_LDO_VRF12_AIF_RC11_OP_MODE_ADDR 0x1C59 1385 #define MT6373_RG_LDO_VRF12_AIF_RC12_OP_MODE_ADDR 0x1C59 1386 #define MT6373_RG_LDO_VRF12_AIF_RC13_OP_MODE_ADDR 0x1C59 1387 #define MT6373_RG_LDO_VRF12_AIF_HW0_OP_MODE_ADDR 0x1C5A 1388 #define MT6373_RG_LDO_VRF12_AIF_HW1_OP_MODE_ADDR 0x1C5A 1389 #define MT6373_RG_LDO_VRF12_AIF_HW2_OP_MODE_ADDR 0x1C5A 1390 #define MT6373_RG_LDO_VRF12_AIF_HW3_OP_MODE_ADDR 0x1C5A 1391 #define MT6373_RG_LDO_VRF12_AIF_HW4_OP_MODE_ADDR 0x1C5A 1392 #define MT6373_RG_LDO_VRF12_AIF_HW5_OP_MODE_ADDR 0x1C5A 1393 #define MT6373_RG_LDO_VRF12_AIF_HW6_OP_MODE_ADDR 0x1C5A 1394 #define MT6373_RG_LDO_VANT18_ONLV_EN_ADDR 0x1C88 1395 #define MT6373_RG_LDO_VANT18_ONLV_EN_SHIFT 3 1396 #define MT6373_RG_LDO_VANT18_RC0_OP_EN_ADDR 0x1C8C 1397 #define MT6373_RG_LDO_VANT18_RC1_OP_EN_ADDR 0x1C8C 1398 #define MT6373_RG_LDO_VANT18_RC2_OP_EN_ADDR 0x1C8C 1399 #define MT6373_RG_LDO_VANT18_RC3_OP_EN_ADDR 0x1C8C 1400 #define MT6373_RG_LDO_VANT18_RC4_OP_EN_ADDR 0x1C8C 1401 #define MT6373_RG_LDO_VANT18_RC5_OP_EN_ADDR 0x1C8C 1402 #define MT6373_RG_LDO_VANT18_RC6_OP_EN_ADDR 0x1C8C 1403 #define MT6373_RG_LDO_VANT18_RC7_OP_EN_ADDR 0x1C8C 1404 #define MT6373_RG_LDO_VANT18_RC8_OP_EN_ADDR 0x1C8D 1405 #define MT6373_RG_LDO_VANT18_RC9_OP_EN_ADDR 0x1C8D 1406 #define MT6373_RG_LDO_VANT18_RC10_OP_EN_ADDR 0x1C8D 1407 #define MT6373_RG_LDO_VANT18_RC11_OP_EN_ADDR 0x1C8D 1408 #define MT6373_RG_LDO_VANT18_RC12_OP_EN_ADDR 0x1C8D 1409 #define MT6373_RG_LDO_VANT18_RC13_OP_EN_ADDR 0x1C8D 1410 #define MT6373_RG_LDO_VANT18_HW0_OP_EN_ADDR 0x1C8E 1411 #define MT6373_RG_LDO_VANT18_HW1_OP_EN_ADDR 0x1C8E 1412 #define MT6373_RG_LDO_VANT18_HW2_OP_EN_ADDR 0x1C8E 1413 #define MT6373_RG_LDO_VANT18_HW3_OP_EN_ADDR 0x1C8E 1414 #define MT6373_RG_LDO_VANT18_HW4_OP_EN_ADDR 0x1C8E 1415 #define MT6373_RG_LDO_VANT18_HW5_OP_EN_ADDR 0x1C8E 1416 #define MT6373_RG_LDO_VANT18_HW6_OP_EN_ADDR 0x1C8E 1417 #define MT6373_RG_LDO_VANT18_SW_OP_EN_ADDR 0x1C8E 1418 #define MT6373_RG_LDO_VANT18_RC0_OP_CFG_ADDR 0x1C8F 1419 #define MT6373_RG_LDO_VANT18_RC1_OP_CFG_ADDR 0x1C8F 1420 #define MT6373_RG_LDO_VANT18_RC2_OP_CFG_ADDR 0x1C8F 1421 #define MT6373_RG_LDO_VANT18_RC3_OP_CFG_ADDR 0x1C8F 1422 #define MT6373_RG_LDO_VANT18_RC4_OP_CFG_ADDR 0x1C8F 1423 #define MT6373_RG_LDO_VANT18_RC5_OP_CFG_ADDR 0x1C8F 1424 #define MT6373_RG_LDO_VANT18_RC6_OP_CFG_ADDR 0x1C8F 1425 #define MT6373_RG_LDO_VANT18_RC7_OP_CFG_ADDR 0x1C8F 1426 #define MT6373_RG_LDO_VANT18_RC8_OP_CFG_ADDR 0x1C90 1427 #define MT6373_RG_LDO_VANT18_RC9_OP_CFG_ADDR 0x1C90 1428 #define MT6373_RG_LDO_VANT18_RC10_OP_CFG_ADDR 0x1C90 1429 #define MT6373_RG_LDO_VANT18_RC11_OP_CFG_ADDR 0x1C90 1430 #define MT6373_RG_LDO_VANT18_RC12_OP_CFG_ADDR 0x1C90 1431 #define MT6373_RG_LDO_VANT18_RC13_OP_CFG_ADDR 0x1C90 1432 #define MT6373_RG_LDO_VANT18_HW0_OP_CFG_ADDR 0x1C91 1433 #define MT6373_RG_LDO_VANT18_HW1_OP_CFG_ADDR 0x1C91 1434 #define MT6373_RG_LDO_VANT18_HW2_OP_CFG_ADDR 0x1C91 1435 #define MT6373_RG_LDO_VANT18_HW3_OP_CFG_ADDR 0x1C91 1436 #define MT6373_RG_LDO_VANT18_HW4_OP_CFG_ADDR 0x1C91 1437 #define MT6373_RG_LDO_VANT18_HW5_OP_CFG_ADDR 0x1C91 1438 #define MT6373_RG_LDO_VANT18_HW6_OP_CFG_ADDR 0x1C91 1439 #define MT6373_RG_LDO_VANT18_SW_OP_CFG_ADDR 0x1C91 1440 #define MT6373_RG_LDO_VANT18_RC0_OP_MODE_ADDR 0x1C92 1441 #define MT6373_RG_LDO_VANT18_RC1_OP_MODE_ADDR 0x1C92 1442 #define MT6373_RG_LDO_VANT18_RC2_OP_MODE_ADDR 0x1C92 1443 #define MT6373_RG_LDO_VANT18_RC3_OP_MODE_ADDR 0x1C92 1444 #define MT6373_RG_LDO_VANT18_RC4_OP_MODE_ADDR 0x1C92 1445 #define MT6373_RG_LDO_VANT18_RC5_OP_MODE_ADDR 0x1C92 1446 #define MT6373_RG_LDO_VANT18_RC6_OP_MODE_ADDR 0x1C92 1447 #define MT6373_RG_LDO_VANT18_RC7_OP_MODE_ADDR 0x1C92 1448 #define MT6373_RG_LDO_VANT18_RC8_OP_MODE_ADDR 0x1C93 1449 #define MT6373_RG_LDO_VANT18_RC9_OP_MODE_ADDR 0x1C93 1450 #define MT6373_RG_LDO_VANT18_RC10_OP_MODE_ADDR 0x1C93 1451 #define MT6373_RG_LDO_VANT18_RC11_OP_MODE_ADDR 0x1C93 1452 #define MT6373_RG_LDO_VANT18_RC12_OP_MODE_ADDR 0x1C93 1453 #define MT6373_RG_LDO_VANT18_RC13_OP_MODE_ADDR 0x1C93 1454 #define MT6373_RG_LDO_VANT18_HW0_OP_MODE_ADDR 0x1C94 1455 #define MT6373_RG_LDO_VANT18_HW1_OP_MODE_ADDR 0x1C94 1456 #define MT6373_RG_LDO_VANT18_HW2_OP_MODE_ADDR 0x1C94 1457 #define MT6373_RG_LDO_VANT18_HW3_OP_MODE_ADDR 0x1C94 1458 #define MT6373_RG_LDO_VANT18_HW4_OP_MODE_ADDR 0x1C94 1459 #define MT6373_RG_LDO_VANT18_HW5_OP_MODE_ADDR 0x1C94 1460 #define MT6373_RG_LDO_VANT18_HW6_OP_MODE_ADDR 0x1C94 1461 #define MT6373_RG_LDO_VMDDR_ONLV_EN_ADDR 0x1C96 1462 #define MT6373_RG_LDO_VMDDR_ONLV_EN_SHIFT 3 1463 #define MT6373_RG_LDO_VMDDR_RC0_OP_EN_ADDR 0x1C9A 1464 #define MT6373_RG_LDO_VMDDR_RC1_OP_EN_ADDR 0x1C9A 1465 #define MT6373_RG_LDO_VMDDR_RC2_OP_EN_ADDR 0x1C9A 1466 #define MT6373_RG_LDO_VMDDR_RC3_OP_EN_ADDR 0x1C9A 1467 #define MT6373_RG_LDO_VMDDR_RC4_OP_EN_ADDR 0x1C9A 1468 #define MT6373_RG_LDO_VMDDR_RC5_OP_EN_ADDR 0x1C9A 1469 #define MT6373_RG_LDO_VMDDR_RC6_OP_EN_ADDR 0x1C9A 1470 #define MT6373_RG_LDO_VMDDR_RC7_OP_EN_ADDR 0x1C9A 1471 #define MT6373_RG_LDO_VMDDR_RC8_OP_EN_ADDR 0x1C9B 1472 #define MT6373_RG_LDO_VMDDR_RC9_OP_EN_ADDR 0x1C9B 1473 #define MT6373_RG_LDO_VMDDR_RC10_OP_EN_ADDR 0x1C9B 1474 #define MT6373_RG_LDO_VMDDR_RC11_OP_EN_ADDR 0x1C9B 1475 #define MT6373_RG_LDO_VMDDR_RC12_OP_EN_ADDR 0x1C9B 1476 #define MT6373_RG_LDO_VMDDR_RC13_OP_EN_ADDR 0x1C9B 1477 #define MT6373_RG_LDO_VMDDR_HW0_OP_EN_ADDR 0x1C9C 1478 #define MT6373_RG_LDO_VMDDR_HW1_OP_EN_ADDR 0x1C9C 1479 #define MT6373_RG_LDO_VMDDR_HW2_OP_EN_ADDR 0x1C9C 1480 #define MT6373_RG_LDO_VMDDR_HW3_OP_EN_ADDR 0x1C9C 1481 #define MT6373_RG_LDO_VMDDR_HW4_OP_EN_ADDR 0x1C9C 1482 #define MT6373_RG_LDO_VMDDR_HW5_OP_EN_ADDR 0x1C9C 1483 #define MT6373_RG_LDO_VMDDR_HW6_OP_EN_ADDR 0x1C9C 1484 #define MT6373_RG_LDO_VMDDR_SW_OP_EN_ADDR 0x1C9C 1485 #define MT6373_RG_LDO_VMDDR_RC0_OP_CFG_ADDR 0x1C9D 1486 #define MT6373_RG_LDO_VMDDR_RC1_OP_CFG_ADDR 0x1C9D 1487 #define MT6373_RG_LDO_VMDDR_RC2_OP_CFG_ADDR 0x1C9D 1488 #define MT6373_RG_LDO_VMDDR_RC3_OP_CFG_ADDR 0x1C9D 1489 #define MT6373_RG_LDO_VMDDR_RC4_OP_CFG_ADDR 0x1C9D 1490 #define MT6373_RG_LDO_VMDDR_RC5_OP_CFG_ADDR 0x1C9D 1491 #define MT6373_RG_LDO_VMDDR_RC6_OP_CFG_ADDR 0x1C9D 1492 #define MT6373_RG_LDO_VMDDR_RC7_OP_CFG_ADDR 0x1C9D 1493 #define MT6373_RG_LDO_VMDDR_RC8_OP_CFG_ADDR 0x1C9E 1494 #define MT6373_RG_LDO_VMDDR_RC9_OP_CFG_ADDR 0x1C9E 1495 #define MT6373_RG_LDO_VMDDR_RC10_OP_CFG_ADDR 0x1C9E 1496 #define MT6373_RG_LDO_VMDDR_RC11_OP_CFG_ADDR 0x1C9E 1497 #define MT6373_RG_LDO_VMDDR_RC12_OP_CFG_ADDR 0x1C9E 1498 #define MT6373_RG_LDO_VMDDR_RC13_OP_CFG_ADDR 0x1C9E 1499 #define MT6373_RG_LDO_VMDDR_HW0_OP_CFG_ADDR 0x1C9F 1500 #define MT6373_RG_LDO_VMDDR_HW1_OP_CFG_ADDR 0x1C9F 1501 #define MT6373_RG_LDO_VMDDR_HW2_OP_CFG_ADDR 0x1C9F 1502 #define MT6373_RG_LDO_VMDDR_HW3_OP_CFG_ADDR 0x1C9F 1503 #define MT6373_RG_LDO_VMDDR_HW4_OP_CFG_ADDR 0x1C9F 1504 #define MT6373_RG_LDO_VMDDR_HW5_OP_CFG_ADDR 0x1C9F 1505 #define MT6373_RG_LDO_VMDDR_HW6_OP_CFG_ADDR 0x1C9F 1506 #define MT6373_RG_LDO_VMDDR_SW_OP_CFG_ADDR 0x1C9F 1507 #define MT6373_RG_LDO_VMDDR_RC0_OP_MODE_ADDR 0x1CA0 1508 #define MT6373_RG_LDO_VMDDR_RC1_OP_MODE_ADDR 0x1CA0 1509 #define MT6373_RG_LDO_VMDDR_RC2_OP_MODE_ADDR 0x1CA0 1510 #define MT6373_RG_LDO_VMDDR_RC3_OP_MODE_ADDR 0x1CA0 1511 #define MT6373_RG_LDO_VMDDR_RC4_OP_MODE_ADDR 0x1CA0 1512 #define MT6373_RG_LDO_VMDDR_RC5_OP_MODE_ADDR 0x1CA0 1513 #define MT6373_RG_LDO_VMDDR_RC6_OP_MODE_ADDR 0x1CA0 1514 #define MT6373_RG_LDO_VMDDR_RC7_OP_MODE_ADDR 0x1CA0 1515 #define MT6373_RG_LDO_VMDDR_RC8_OP_MODE_ADDR 0x1CA1 1516 #define MT6373_RG_LDO_VMDDR_RC9_OP_MODE_ADDR 0x1CA1 1517 #define MT6373_RG_LDO_VMDDR_RC10_OP_MODE_ADDR 0x1CA1 1518 #define MT6373_RG_LDO_VMDDR_RC11_OP_MODE_ADDR 0x1CA1 1519 #define MT6373_RG_LDO_VMDDR_RC12_OP_MODE_ADDR 0x1CA1 1520 #define MT6373_RG_LDO_VMDDR_RC13_OP_MODE_ADDR 0x1CA1 1521 #define MT6373_RG_LDO_VMDDR_HW0_OP_MODE_ADDR 0x1CA2 1522 #define MT6373_RG_LDO_VMDDR_HW1_OP_MODE_ADDR 0x1CA2 1523 #define MT6373_RG_LDO_VMDDR_HW2_OP_MODE_ADDR 0x1CA2 1524 #define MT6373_RG_LDO_VMDDR_HW3_OP_MODE_ADDR 0x1CA2 1525 #define MT6373_RG_LDO_VMDDR_HW4_OP_MODE_ADDR 0x1CA2 1526 #define MT6373_RG_LDO_VMDDR_HW5_OP_MODE_ADDR 0x1CA2 1527 #define MT6373_RG_LDO_VMDDR_HW6_OP_MODE_ADDR 0x1CA2 1528 #define MT6373_RG_LDO_VEFUSE_ONLV_EN_ADDR 0x1CA4 1529 #define MT6373_RG_LDO_VEFUSE_ONLV_EN_SHIFT 3 1530 #define MT6373_RG_LDO_VEFUSE_RC0_OP_EN_ADDR 0x1CA8 1531 #define MT6373_RG_LDO_VEFUSE_RC1_OP_EN_ADDR 0x1CA8 1532 #define MT6373_RG_LDO_VEFUSE_RC2_OP_EN_ADDR 0x1CA8 1533 #define MT6373_RG_LDO_VEFUSE_RC3_OP_EN_ADDR 0x1CA8 1534 #define MT6373_RG_LDO_VEFUSE_RC4_OP_EN_ADDR 0x1CA8 1535 #define MT6373_RG_LDO_VEFUSE_RC5_OP_EN_ADDR 0x1CA8 1536 #define MT6373_RG_LDO_VEFUSE_RC6_OP_EN_ADDR 0x1CA8 1537 #define MT6373_RG_LDO_VEFUSE_RC7_OP_EN_ADDR 0x1CA8 1538 #define MT6373_RG_LDO_VEFUSE_RC8_OP_EN_ADDR 0x1CA9 1539 #define MT6373_RG_LDO_VEFUSE_RC9_OP_EN_ADDR 0x1CA9 1540 #define MT6373_RG_LDO_VEFUSE_RC10_OP_EN_ADDR 0x1CA9 1541 #define MT6373_RG_LDO_VEFUSE_RC11_OP_EN_ADDR 0x1CA9 1542 #define MT6373_RG_LDO_VEFUSE_RC12_OP_EN_ADDR 0x1CA9 1543 #define MT6373_RG_LDO_VEFUSE_RC13_OP_EN_ADDR 0x1CA9 1544 #define MT6373_RG_LDO_VEFUSE_HW0_OP_EN_ADDR 0x1CAA 1545 #define MT6373_RG_LDO_VEFUSE_HW1_OP_EN_ADDR 0x1CAA 1546 #define MT6373_RG_LDO_VEFUSE_HW2_OP_EN_ADDR 0x1CAA 1547 #define MT6373_RG_LDO_VEFUSE_HW3_OP_EN_ADDR 0x1CAA 1548 #define MT6373_RG_LDO_VEFUSE_HW4_OP_EN_ADDR 0x1CAA 1549 #define MT6373_RG_LDO_VEFUSE_HW5_OP_EN_ADDR 0x1CAA 1550 #define MT6373_RG_LDO_VEFUSE_HW6_OP_EN_ADDR 0x1CAA 1551 #define MT6373_RG_LDO_VEFUSE_SW_OP_EN_ADDR 0x1CAA 1552 #define MT6373_RG_LDO_VEFUSE_RC0_OP_CFG_ADDR 0x1CAB 1553 #define MT6373_RG_LDO_VEFUSE_RC1_OP_CFG_ADDR 0x1CAB 1554 #define MT6373_RG_LDO_VEFUSE_RC2_OP_CFG_ADDR 0x1CAB 1555 #define MT6373_RG_LDO_VEFUSE_RC3_OP_CFG_ADDR 0x1CAB 1556 #define MT6373_RG_LDO_VEFUSE_RC4_OP_CFG_ADDR 0x1CAB 1557 #define MT6373_RG_LDO_VEFUSE_RC5_OP_CFG_ADDR 0x1CAB 1558 #define MT6373_RG_LDO_VEFUSE_RC6_OP_CFG_ADDR 0x1CAB 1559 #define MT6373_RG_LDO_VEFUSE_RC7_OP_CFG_ADDR 0x1CAB 1560 #define MT6373_RG_LDO_VEFUSE_RC8_OP_CFG_ADDR 0x1CAC 1561 #define MT6373_RG_LDO_VEFUSE_RC9_OP_CFG_ADDR 0x1CAC 1562 #define MT6373_RG_LDO_VEFUSE_RC10_OP_CFG_ADDR 0x1CAC 1563 #define MT6373_RG_LDO_VEFUSE_RC11_OP_CFG_ADDR 0x1CAC 1564 #define MT6373_RG_LDO_VEFUSE_RC12_OP_CFG_ADDR 0x1CAC 1565 #define MT6373_RG_LDO_VEFUSE_RC13_OP_CFG_ADDR 0x1CAC 1566 #define MT6373_RG_LDO_VEFUSE_HW0_OP_CFG_ADDR 0x1CAD 1567 #define MT6373_RG_LDO_VEFUSE_HW1_OP_CFG_ADDR 0x1CAD 1568 #define MT6373_RG_LDO_VEFUSE_HW2_OP_CFG_ADDR 0x1CAD 1569 #define MT6373_RG_LDO_VEFUSE_HW3_OP_CFG_ADDR 0x1CAD 1570 #define MT6373_RG_LDO_VEFUSE_HW4_OP_CFG_ADDR 0x1CAD 1571 #define MT6373_RG_LDO_VEFUSE_HW5_OP_CFG_ADDR 0x1CAD 1572 #define MT6373_RG_LDO_VEFUSE_HW6_OP_CFG_ADDR 0x1CAD 1573 #define MT6373_RG_LDO_VEFUSE_SW_OP_CFG_ADDR 0x1CAD 1574 #define MT6373_RG_LDO_VEFUSE_RC0_OP_MODE_ADDR 0x1CAE 1575 #define MT6373_RG_LDO_VEFUSE_RC1_OP_MODE_ADDR 0x1CAE 1576 #define MT6373_RG_LDO_VEFUSE_RC2_OP_MODE_ADDR 0x1CAE 1577 #define MT6373_RG_LDO_VEFUSE_RC3_OP_MODE_ADDR 0x1CAE 1578 #define MT6373_RG_LDO_VEFUSE_RC4_OP_MODE_ADDR 0x1CAE 1579 #define MT6373_RG_LDO_VEFUSE_RC5_OP_MODE_ADDR 0x1CAE 1580 #define MT6373_RG_LDO_VEFUSE_RC6_OP_MODE_ADDR 0x1CAE 1581 #define MT6373_RG_LDO_VEFUSE_RC7_OP_MODE_ADDR 0x1CAE 1582 #define MT6373_RG_LDO_VEFUSE_RC8_OP_MODE_ADDR 0x1CAF 1583 #define MT6373_RG_LDO_VEFUSE_RC9_OP_MODE_ADDR 0x1CAF 1584 #define MT6373_RG_LDO_VEFUSE_RC10_OP_MODE_ADDR 0x1CAF 1585 #define MT6373_RG_LDO_VEFUSE_RC11_OP_MODE_ADDR 0x1CAF 1586 #define MT6373_RG_LDO_VEFUSE_RC12_OP_MODE_ADDR 0x1CAF 1587 #define MT6373_RG_LDO_VEFUSE_RC13_OP_MODE_ADDR 0x1CAF 1588 #define MT6373_RG_LDO_VEFUSE_HW0_OP_MODE_ADDR 0x1CB0 1589 #define MT6373_RG_LDO_VEFUSE_HW1_OP_MODE_ADDR 0x1CB0 1590 #define MT6373_RG_LDO_VEFUSE_HW2_OP_MODE_ADDR 0x1CB0 1591 #define MT6373_RG_LDO_VEFUSE_HW3_OP_MODE_ADDR 0x1CB0 1592 #define MT6373_RG_LDO_VEFUSE_HW4_OP_MODE_ADDR 0x1CB0 1593 #define MT6373_RG_LDO_VEFUSE_HW5_OP_MODE_ADDR 0x1CB0 1594 #define MT6373_RG_LDO_VEFUSE_HW6_OP_MODE_ADDR 0x1CB0 1595 #define MT6373_RG_LDO_VMCH_ONLV_EN_ADDR 0x1CB2 1596 #define MT6373_RG_LDO_VMCH_ONLV_EN_SHIFT 3 1597 #define MT6373_RG_LDO_VMCH_RC0_OP_EN_ADDR 0x1CB6 1598 #define MT6373_RG_LDO_VMCH_RC1_OP_EN_ADDR 0x1CB6 1599 #define MT6373_RG_LDO_VMCH_RC2_OP_EN_ADDR 0x1CB6 1600 #define MT6373_RG_LDO_VMCH_RC3_OP_EN_ADDR 0x1CB6 1601 #define MT6373_RG_LDO_VMCH_RC4_OP_EN_ADDR 0x1CB6 1602 #define MT6373_RG_LDO_VMCH_RC5_OP_EN_ADDR 0x1CB6 1603 #define MT6373_RG_LDO_VMCH_RC6_OP_EN_ADDR 0x1CB6 1604 #define MT6373_RG_LDO_VMCH_RC7_OP_EN_ADDR 0x1CB6 1605 #define MT6373_RG_LDO_VMCH_RC8_OP_EN_ADDR 0x1CB7 1606 #define MT6373_RG_LDO_VMCH_RC9_OP_EN_ADDR 0x1CB7 1607 #define MT6373_RG_LDO_VMCH_RC10_OP_EN_ADDR 0x1CB7 1608 #define MT6373_RG_LDO_VMCH_RC11_OP_EN_ADDR 0x1CB7 1609 #define MT6373_RG_LDO_VMCH_RC12_OP_EN_ADDR 0x1CB7 1610 #define MT6373_RG_LDO_VMCH_RC13_OP_EN_ADDR 0x1CB7 1611 #define MT6373_RG_LDO_VMCH_HW0_OP_EN_ADDR 0x1CB8 1612 #define MT6373_RG_LDO_VMCH_HW1_OP_EN_ADDR 0x1CB8 1613 #define MT6373_RG_LDO_VMCH_HW2_OP_EN_ADDR 0x1CB8 1614 #define MT6373_RG_LDO_VMCH_HW3_OP_EN_ADDR 0x1CB8 1615 #define MT6373_RG_LDO_VMCH_HW4_OP_EN_ADDR 0x1CB8 1616 #define MT6373_RG_LDO_VMCH_HW5_OP_EN_ADDR 0x1CB8 1617 #define MT6373_RG_LDO_VMCH_HW6_OP_EN_ADDR 0x1CB8 1618 #define MT6373_RG_LDO_VMCH_SW_OP_EN_ADDR 0x1CB8 1619 #define MT6373_RG_LDO_VMCH_RC0_OP_CFG_ADDR 0x1CB9 1620 #define MT6373_RG_LDO_VMCH_RC1_OP_CFG_ADDR 0x1CB9 1621 #define MT6373_RG_LDO_VMCH_RC2_OP_CFG_ADDR 0x1CB9 1622 #define MT6373_RG_LDO_VMCH_RC3_OP_CFG_ADDR 0x1CB9 1623 #define MT6373_RG_LDO_VMCH_RC4_OP_CFG_ADDR 0x1CB9 1624 #define MT6373_RG_LDO_VMCH_RC5_OP_CFG_ADDR 0x1CB9 1625 #define MT6373_RG_LDO_VMCH_RC6_OP_CFG_ADDR 0x1CB9 1626 #define MT6373_RG_LDO_VMCH_RC7_OP_CFG_ADDR 0x1CB9 1627 #define MT6373_RG_LDO_VMCH_RC8_OP_CFG_ADDR 0x1CBA 1628 #define MT6373_RG_LDO_VMCH_RC9_OP_CFG_ADDR 0x1CBA 1629 #define MT6373_RG_LDO_VMCH_RC10_OP_CFG_ADDR 0x1CBA 1630 #define MT6373_RG_LDO_VMCH_RC11_OP_CFG_ADDR 0x1CBA 1631 #define MT6373_RG_LDO_VMCH_RC12_OP_CFG_ADDR 0x1CBA 1632 #define MT6373_RG_LDO_VMCH_RC13_OP_CFG_ADDR 0x1CBA 1633 #define MT6373_RG_LDO_VMCH_HW0_OP_CFG_ADDR 0x1CBB 1634 #define MT6373_RG_LDO_VMCH_HW1_OP_CFG_ADDR 0x1CBB 1635 #define MT6373_RG_LDO_VMCH_HW2_OP_CFG_ADDR 0x1CBB 1636 #define MT6373_RG_LDO_VMCH_HW3_OP_CFG_ADDR 0x1CBB 1637 #define MT6373_RG_LDO_VMCH_HW4_OP_CFG_ADDR 0x1CBB 1638 #define MT6373_RG_LDO_VMCH_HW5_OP_CFG_ADDR 0x1CBB 1639 #define MT6373_RG_LDO_VMCH_HW6_OP_CFG_ADDR 0x1CBB 1640 #define MT6373_RG_LDO_VMCH_SW_OP_CFG_ADDR 0x1CBB 1641 #define MT6373_RG_LDO_VMCH_RC0_OP_MODE_ADDR 0x1CBC 1642 #define MT6373_RG_LDO_VMCH_RC1_OP_MODE_ADDR 0x1CBC 1643 #define MT6373_RG_LDO_VMCH_RC2_OP_MODE_ADDR 0x1CBC 1644 #define MT6373_RG_LDO_VMCH_RC3_OP_MODE_ADDR 0x1CBC 1645 #define MT6373_RG_LDO_VMCH_RC4_OP_MODE_ADDR 0x1CBC 1646 #define MT6373_RG_LDO_VMCH_RC5_OP_MODE_ADDR 0x1CBC 1647 #define MT6373_RG_LDO_VMCH_RC6_OP_MODE_ADDR 0x1CBC 1648 #define MT6373_RG_LDO_VMCH_RC7_OP_MODE_ADDR 0x1CBC 1649 #define MT6373_RG_LDO_VMCH_RC8_OP_MODE_ADDR 0x1CBD 1650 #define MT6373_RG_LDO_VMCH_RC9_OP_MODE_ADDR 0x1CBD 1651 #define MT6373_RG_LDO_VMCH_RC10_OP_MODE_ADDR 0x1CBD 1652 #define MT6373_RG_LDO_VMCH_RC11_OP_MODE_ADDR 0x1CBD 1653 #define MT6373_RG_LDO_VMCH_RC12_OP_MODE_ADDR 0x1CBD 1654 #define MT6373_RG_LDO_VMCH_RC13_OP_MODE_ADDR 0x1CBD 1655 #define MT6373_RG_LDO_VMCH_HW0_OP_MODE_ADDR 0x1CBE 1656 #define MT6373_RG_LDO_VMCH_HW1_OP_MODE_ADDR 0x1CBE 1657 #define MT6373_RG_LDO_VMCH_HW2_OP_MODE_ADDR 0x1CBE 1658 #define MT6373_RG_LDO_VMCH_HW3_OP_MODE_ADDR 0x1CBE 1659 #define MT6373_RG_LDO_VMCH_HW4_OP_MODE_ADDR 0x1CBE 1660 #define MT6373_RG_LDO_VMCH_HW5_OP_MODE_ADDR 0x1CBE 1661 #define MT6373_RG_LDO_VMCH_HW6_OP_MODE_ADDR 0x1CBE 1662 #define MT6373_RG_LDO_VMC_ONLV_EN_ADDR 0x1CC1 1663 #define MT6373_RG_LDO_VMC_ONLV_EN_SHIFT 3 1664 #define MT6373_RG_LDO_VMC_RC0_OP_EN_ADDR 0x1CC5 1665 #define MT6373_RG_LDO_VMC_RC1_OP_EN_ADDR 0x1CC5 1666 #define MT6373_RG_LDO_VMC_RC2_OP_EN_ADDR 0x1CC5 1667 #define MT6373_RG_LDO_VMC_RC3_OP_EN_ADDR 0x1CC5 1668 #define MT6373_RG_LDO_VMC_RC4_OP_EN_ADDR 0x1CC5 1669 #define MT6373_RG_LDO_VMC_RC5_OP_EN_ADDR 0x1CC5 1670 #define MT6373_RG_LDO_VMC_RC6_OP_EN_ADDR 0x1CC5 1671 #define MT6373_RG_LDO_VMC_RC7_OP_EN_ADDR 0x1CC5 1672 #define MT6373_RG_LDO_VMC_RC8_OP_EN_ADDR 0x1CC6 1673 #define MT6373_RG_LDO_VMC_RC9_OP_EN_ADDR 0x1CC6 1674 #define MT6373_RG_LDO_VMC_RC10_OP_EN_ADDR 0x1CC6 1675 #define MT6373_RG_LDO_VMC_RC11_OP_EN_ADDR 0x1CC6 1676 #define MT6373_RG_LDO_VMC_RC12_OP_EN_ADDR 0x1CC6 1677 #define MT6373_RG_LDO_VMC_RC13_OP_EN_ADDR 0x1CC6 1678 #define MT6373_RG_LDO_VMC_HW0_OP_EN_ADDR 0x1CC7 1679 #define MT6373_RG_LDO_VMC_HW1_OP_EN_ADDR 0x1CC7 1680 #define MT6373_RG_LDO_VMC_HW2_OP_EN_ADDR 0x1CC7 1681 #define MT6373_RG_LDO_VMC_HW3_OP_EN_ADDR 0x1CC7 1682 #define MT6373_RG_LDO_VMC_HW4_OP_EN_ADDR 0x1CC7 1683 #define MT6373_RG_LDO_VMC_HW5_OP_EN_ADDR 0x1CC7 1684 #define MT6373_RG_LDO_VMC_HW6_OP_EN_ADDR 0x1CC7 1685 #define MT6373_RG_LDO_VMC_SW_OP_EN_ADDR 0x1CC7 1686 #define MT6373_RG_LDO_VMC_RC0_OP_CFG_ADDR 0x1CC8 1687 #define MT6373_RG_LDO_VMC_RC1_OP_CFG_ADDR 0x1CC8 1688 #define MT6373_RG_LDO_VMC_RC2_OP_CFG_ADDR 0x1CC8 1689 #define MT6373_RG_LDO_VMC_RC3_OP_CFG_ADDR 0x1CC8 1690 #define MT6373_RG_LDO_VMC_RC4_OP_CFG_ADDR 0x1CC8 1691 #define MT6373_RG_LDO_VMC_RC5_OP_CFG_ADDR 0x1CC8 1692 #define MT6373_RG_LDO_VMC_RC6_OP_CFG_ADDR 0x1CC8 1693 #define MT6373_RG_LDO_VMC_RC7_OP_CFG_ADDR 0x1CC8 1694 #define MT6373_RG_LDO_VMC_RC8_OP_CFG_ADDR 0x1CC9 1695 #define MT6373_RG_LDO_VMC_RC9_OP_CFG_ADDR 0x1CC9 1696 #define MT6373_RG_LDO_VMC_RC10_OP_CFG_ADDR 0x1CC9 1697 #define MT6373_RG_LDO_VMC_RC11_OP_CFG_ADDR 0x1CC9 1698 #define MT6373_RG_LDO_VMC_RC12_OP_CFG_ADDR 0x1CC9 1699 #define MT6373_RG_LDO_VMC_RC13_OP_CFG_ADDR 0x1CC9 1700 #define MT6373_RG_LDO_VMC_HW0_OP_CFG_ADDR 0x1CCA 1701 #define MT6373_RG_LDO_VMC_HW1_OP_CFG_ADDR 0x1CCA 1702 #define MT6373_RG_LDO_VMC_HW2_OP_CFG_ADDR 0x1CCA 1703 #define MT6373_RG_LDO_VMC_HW3_OP_CFG_ADDR 0x1CCA 1704 #define MT6373_RG_LDO_VMC_HW4_OP_CFG_ADDR 0x1CCA 1705 #define MT6373_RG_LDO_VMC_HW5_OP_CFG_ADDR 0x1CCA 1706 #define MT6373_RG_LDO_VMC_HW6_OP_CFG_ADDR 0x1CCA 1707 #define MT6373_RG_LDO_VMC_SW_OP_CFG_ADDR 0x1CCA 1708 #define MT6373_RG_LDO_VMC_RC0_OP_MODE_ADDR 0x1CCB 1709 #define MT6373_RG_LDO_VMC_RC1_OP_MODE_ADDR 0x1CCB 1710 #define MT6373_RG_LDO_VMC_RC2_OP_MODE_ADDR 0x1CCB 1711 #define MT6373_RG_LDO_VMC_RC3_OP_MODE_ADDR 0x1CCB 1712 #define MT6373_RG_LDO_VMC_RC4_OP_MODE_ADDR 0x1CCB 1713 #define MT6373_RG_LDO_VMC_RC5_OP_MODE_ADDR 0x1CCB 1714 #define MT6373_RG_LDO_VMC_RC6_OP_MODE_ADDR 0x1CCB 1715 #define MT6373_RG_LDO_VMC_RC7_OP_MODE_ADDR 0x1CCB 1716 #define MT6373_RG_LDO_VMC_RC8_OP_MODE_ADDR 0x1CCC 1717 #define MT6373_RG_LDO_VMC_RC9_OP_MODE_ADDR 0x1CCC 1718 #define MT6373_RG_LDO_VMC_RC10_OP_MODE_ADDR 0x1CCC 1719 #define MT6373_RG_LDO_VMC_RC11_OP_MODE_ADDR 0x1CCC 1720 #define MT6373_RG_LDO_VMC_RC12_OP_MODE_ADDR 0x1CCC 1721 #define MT6373_RG_LDO_VMC_RC13_OP_MODE_ADDR 0x1CCC 1722 #define MT6373_RG_LDO_VMC_HW0_OP_MODE_ADDR 0x1CCD 1723 #define MT6373_RG_LDO_VMC_HW1_OP_MODE_ADDR 0x1CCD 1724 #define MT6373_RG_LDO_VMC_HW2_OP_MODE_ADDR 0x1CCD 1725 #define MT6373_RG_LDO_VMC_HW3_OP_MODE_ADDR 0x1CCD 1726 #define MT6373_RG_LDO_VMC_HW4_OP_MODE_ADDR 0x1CCD 1727 #define MT6373_RG_LDO_VMC_HW5_OP_MODE_ADDR 0x1CCD 1728 #define MT6373_RG_LDO_VMC_HW6_OP_MODE_ADDR 0x1CCD 1729 #define MT6373_RG_LDO_VIBR_ONLV_EN_ADDR 0x1CCF 1730 #define MT6373_RG_LDO_VIBR_ONLV_EN_SHIFT 3 1731 #define MT6373_RG_LDO_VIBR_RC0_OP_EN_ADDR 0x1CD3 1732 #define MT6373_RG_LDO_VIBR_RC1_OP_EN_ADDR 0x1CD3 1733 #define MT6373_RG_LDO_VIBR_RC2_OP_EN_ADDR 0x1CD3 1734 #define MT6373_RG_LDO_VIBR_RC3_OP_EN_ADDR 0x1CD3 1735 #define MT6373_RG_LDO_VIBR_RC4_OP_EN_ADDR 0x1CD3 1736 #define MT6373_RG_LDO_VIBR_RC5_OP_EN_ADDR 0x1CD3 1737 #define MT6373_RG_LDO_VIBR_RC6_OP_EN_ADDR 0x1CD3 1738 #define MT6373_RG_LDO_VIBR_RC7_OP_EN_ADDR 0x1CD3 1739 #define MT6373_RG_LDO_VIBR_RC8_OP_EN_ADDR 0x1CD4 1740 #define MT6373_RG_LDO_VIBR_RC9_OP_EN_ADDR 0x1CD4 1741 #define MT6373_RG_LDO_VIBR_RC10_OP_EN_ADDR 0x1CD4 1742 #define MT6373_RG_LDO_VIBR_RC11_OP_EN_ADDR 0x1CD4 1743 #define MT6373_RG_LDO_VIBR_RC12_OP_EN_ADDR 0x1CD4 1744 #define MT6373_RG_LDO_VIBR_RC13_OP_EN_ADDR 0x1CD4 1745 #define MT6373_RG_LDO_VIBR_HW0_OP_EN_ADDR 0x1CD5 1746 #define MT6373_RG_LDO_VIBR_HW1_OP_EN_ADDR 0x1CD5 1747 #define MT6373_RG_LDO_VIBR_HW2_OP_EN_ADDR 0x1CD5 1748 #define MT6373_RG_LDO_VIBR_HW3_OP_EN_ADDR 0x1CD5 1749 #define MT6373_RG_LDO_VIBR_HW4_OP_EN_ADDR 0x1CD5 1750 #define MT6373_RG_LDO_VIBR_HW5_OP_EN_ADDR 0x1CD5 1751 #define MT6373_RG_LDO_VIBR_HW6_OP_EN_ADDR 0x1CD5 1752 #define MT6373_RG_LDO_VIBR_SW_OP_EN_ADDR 0x1CD5 1753 #define MT6373_RG_LDO_VIBR_RC0_OP_CFG_ADDR 0x1CD6 1754 #define MT6373_RG_LDO_VIBR_RC1_OP_CFG_ADDR 0x1CD6 1755 #define MT6373_RG_LDO_VIBR_RC2_OP_CFG_ADDR 0x1CD6 1756 #define MT6373_RG_LDO_VIBR_RC3_OP_CFG_ADDR 0x1CD6 1757 #define MT6373_RG_LDO_VIBR_RC4_OP_CFG_ADDR 0x1CD6 1758 #define MT6373_RG_LDO_VIBR_RC5_OP_CFG_ADDR 0x1CD6 1759 #define MT6373_RG_LDO_VIBR_RC6_OP_CFG_ADDR 0x1CD6 1760 #define MT6373_RG_LDO_VIBR_RC7_OP_CFG_ADDR 0x1CD6 1761 #define MT6373_RG_LDO_VIBR_RC8_OP_CFG_ADDR 0x1CD7 1762 #define MT6373_RG_LDO_VIBR_RC9_OP_CFG_ADDR 0x1CD7 1763 #define MT6373_RG_LDO_VIBR_RC10_OP_CFG_ADDR 0x1CD7 1764 #define MT6373_RG_LDO_VIBR_RC11_OP_CFG_ADDR 0x1CD7 1765 #define MT6373_RG_LDO_VIBR_RC12_OP_CFG_ADDR 0x1CD7 1766 #define MT6373_RG_LDO_VIBR_RC13_OP_CFG_ADDR 0x1CD7 1767 #define MT6373_RG_LDO_VIBR_HW0_OP_CFG_ADDR 0x1CD8 1768 #define MT6373_RG_LDO_VIBR_HW1_OP_CFG_ADDR 0x1CD8 1769 #define MT6373_RG_LDO_VIBR_HW2_OP_CFG_ADDR 0x1CD8 1770 #define MT6373_RG_LDO_VIBR_HW3_OP_CFG_ADDR 0x1CD8 1771 #define MT6373_RG_LDO_VIBR_HW4_OP_CFG_ADDR 0x1CD8 1772 #define MT6373_RG_LDO_VIBR_HW5_OP_CFG_ADDR 0x1CD8 1773 #define MT6373_RG_LDO_VIBR_HW6_OP_CFG_ADDR 0x1CD8 1774 #define MT6373_RG_LDO_VIBR_SW_OP_CFG_ADDR 0x1CD8 1775 #define MT6373_RG_LDO_VIBR_RC0_OP_MODE_ADDR 0x1CD9 1776 #define MT6373_RG_LDO_VIBR_RC1_OP_MODE_ADDR 0x1CD9 1777 #define MT6373_RG_LDO_VIBR_RC2_OP_MODE_ADDR 0x1CD9 1778 #define MT6373_RG_LDO_VIBR_RC3_OP_MODE_ADDR 0x1CD9 1779 #define MT6373_RG_LDO_VIBR_RC4_OP_MODE_ADDR 0x1CD9 1780 #define MT6373_RG_LDO_VIBR_RC5_OP_MODE_ADDR 0x1CD9 1781 #define MT6373_RG_LDO_VIBR_RC6_OP_MODE_ADDR 0x1CD9 1782 #define MT6373_RG_LDO_VIBR_RC7_OP_MODE_ADDR 0x1CD9 1783 #define MT6373_RG_LDO_VIBR_RC8_OP_MODE_ADDR 0x1CDA 1784 #define MT6373_RG_LDO_VIBR_RC9_OP_MODE_ADDR 0x1CDA 1785 #define MT6373_RG_LDO_VIBR_RC10_OP_MODE_ADDR 0x1CDA 1786 #define MT6373_RG_LDO_VIBR_RC11_OP_MODE_ADDR 0x1CDA 1787 #define MT6373_RG_LDO_VIBR_RC12_OP_MODE_ADDR 0x1CDA 1788 #define MT6373_RG_LDO_VIBR_RC13_OP_MODE_ADDR 0x1CDA 1789 #define MT6373_RG_LDO_VIBR_HW0_OP_MODE_ADDR 0x1CDB 1790 #define MT6373_RG_LDO_VIBR_HW1_OP_MODE_ADDR 0x1CDB 1791 #define MT6373_RG_LDO_VIBR_HW2_OP_MODE_ADDR 0x1CDB 1792 #define MT6373_RG_LDO_VIBR_HW3_OP_MODE_ADDR 0x1CDB 1793 #define MT6373_RG_LDO_VIBR_HW4_OP_MODE_ADDR 0x1CDB 1794 #define MT6373_RG_LDO_VIBR_HW5_OP_MODE_ADDR 0x1CDB 1795 #define MT6373_RG_LDO_VIBR_HW6_OP_MODE_ADDR 0x1CDB 1796 #define MT6373_RG_LDO_VIO28_ONLV_EN_ADDR 0x1D08 1797 #define MT6373_RG_LDO_VIO28_ONLV_EN_SHIFT 3 1798 #define MT6373_RG_LDO_VIO28_RC0_OP_EN_ADDR 0x1D0C 1799 #define MT6373_RG_LDO_VIO28_RC1_OP_EN_ADDR 0x1D0C 1800 #define MT6373_RG_LDO_VIO28_RC2_OP_EN_ADDR 0x1D0C 1801 #define MT6373_RG_LDO_VIO28_RC3_OP_EN_ADDR 0x1D0C 1802 #define MT6373_RG_LDO_VIO28_RC4_OP_EN_ADDR 0x1D0C 1803 #define MT6373_RG_LDO_VIO28_RC5_OP_EN_ADDR 0x1D0C 1804 #define MT6373_RG_LDO_VIO28_RC6_OP_EN_ADDR 0x1D0C 1805 #define MT6373_RG_LDO_VIO28_RC7_OP_EN_ADDR 0x1D0C 1806 #define MT6373_RG_LDO_VIO28_RC8_OP_EN_ADDR 0x1D0D 1807 #define MT6373_RG_LDO_VIO28_RC9_OP_EN_ADDR 0x1D0D 1808 #define MT6373_RG_LDO_VIO28_RC10_OP_EN_ADDR 0x1D0D 1809 #define MT6373_RG_LDO_VIO28_RC11_OP_EN_ADDR 0x1D0D 1810 #define MT6373_RG_LDO_VIO28_RC12_OP_EN_ADDR 0x1D0D 1811 #define MT6373_RG_LDO_VIO28_RC13_OP_EN_ADDR 0x1D0D 1812 #define MT6373_RG_LDO_VIO28_HW0_OP_EN_ADDR 0x1D0E 1813 #define MT6373_RG_LDO_VIO28_HW1_OP_EN_ADDR 0x1D0E 1814 #define MT6373_RG_LDO_VIO28_HW2_OP_EN_ADDR 0x1D0E 1815 #define MT6373_RG_LDO_VIO28_HW3_OP_EN_ADDR 0x1D0E 1816 #define MT6373_RG_LDO_VIO28_HW4_OP_EN_ADDR 0x1D0E 1817 #define MT6373_RG_LDO_VIO28_HW5_OP_EN_ADDR 0x1D0E 1818 #define MT6373_RG_LDO_VIO28_HW6_OP_EN_ADDR 0x1D0E 1819 #define MT6373_RG_LDO_VIO28_SW_OP_EN_ADDR 0x1D0E 1820 #define MT6373_RG_LDO_VIO28_RC0_OP_CFG_ADDR 0x1D0F 1821 #define MT6373_RG_LDO_VIO28_RC1_OP_CFG_ADDR 0x1D0F 1822 #define MT6373_RG_LDO_VIO28_RC2_OP_CFG_ADDR 0x1D0F 1823 #define MT6373_RG_LDO_VIO28_RC3_OP_CFG_ADDR 0x1D0F 1824 #define MT6373_RG_LDO_VIO28_RC4_OP_CFG_ADDR 0x1D0F 1825 #define MT6373_RG_LDO_VIO28_RC5_OP_CFG_ADDR 0x1D0F 1826 #define MT6373_RG_LDO_VIO28_RC6_OP_CFG_ADDR 0x1D0F 1827 #define MT6373_RG_LDO_VIO28_RC7_OP_CFG_ADDR 0x1D0F 1828 #define MT6373_RG_LDO_VIO28_RC8_OP_CFG_ADDR 0x1D10 1829 #define MT6373_RG_LDO_VIO28_RC9_OP_CFG_ADDR 0x1D10 1830 #define MT6373_RG_LDO_VIO28_RC10_OP_CFG_ADDR 0x1D10 1831 #define MT6373_RG_LDO_VIO28_RC11_OP_CFG_ADDR 0x1D10 1832 #define MT6373_RG_LDO_VIO28_RC12_OP_CFG_ADDR 0x1D10 1833 #define MT6373_RG_LDO_VIO28_RC13_OP_CFG_ADDR 0x1D10 1834 #define MT6373_RG_LDO_VIO28_HW0_OP_CFG_ADDR 0x1D11 1835 #define MT6373_RG_LDO_VIO28_HW1_OP_CFG_ADDR 0x1D11 1836 #define MT6373_RG_LDO_VIO28_HW2_OP_CFG_ADDR 0x1D11 1837 #define MT6373_RG_LDO_VIO28_HW3_OP_CFG_ADDR 0x1D11 1838 #define MT6373_RG_LDO_VIO28_HW4_OP_CFG_ADDR 0x1D11 1839 #define MT6373_RG_LDO_VIO28_HW5_OP_CFG_ADDR 0x1D11 1840 #define MT6373_RG_LDO_VIO28_HW6_OP_CFG_ADDR 0x1D11 1841 #define MT6373_RG_LDO_VIO28_SW_OP_CFG_ADDR 0x1D11 1842 #define MT6373_RG_LDO_VIO28_RC0_OP_MODE_ADDR 0x1D12 1843 #define MT6373_RG_LDO_VIO28_RC1_OP_MODE_ADDR 0x1D12 1844 #define MT6373_RG_LDO_VIO28_RC2_OP_MODE_ADDR 0x1D12 1845 #define MT6373_RG_LDO_VIO28_RC3_OP_MODE_ADDR 0x1D12 1846 #define MT6373_RG_LDO_VIO28_RC4_OP_MODE_ADDR 0x1D12 1847 #define MT6373_RG_LDO_VIO28_RC5_OP_MODE_ADDR 0x1D12 1848 #define MT6373_RG_LDO_VIO28_RC6_OP_MODE_ADDR 0x1D12 1849 #define MT6373_RG_LDO_VIO28_RC7_OP_MODE_ADDR 0x1D12 1850 #define MT6373_RG_LDO_VIO28_RC8_OP_MODE_ADDR 0x1D13 1851 #define MT6373_RG_LDO_VIO28_RC9_OP_MODE_ADDR 0x1D13 1852 #define MT6373_RG_LDO_VIO28_RC10_OP_MODE_ADDR 0x1D13 1853 #define MT6373_RG_LDO_VIO28_RC11_OP_MODE_ADDR 0x1D13 1854 #define MT6373_RG_LDO_VIO28_RC12_OP_MODE_ADDR 0x1D13 1855 #define MT6373_RG_LDO_VIO28_RC13_OP_MODE_ADDR 0x1D13 1856 #define MT6373_RG_LDO_VIO28_HW0_OP_MODE_ADDR 0x1D14 1857 #define MT6373_RG_LDO_VIO28_HW1_OP_MODE_ADDR 0x1D14 1858 #define MT6373_RG_LDO_VIO28_HW2_OP_MODE_ADDR 0x1D14 1859 #define MT6373_RG_LDO_VIO28_HW3_OP_MODE_ADDR 0x1D14 1860 #define MT6373_RG_LDO_VIO28_HW4_OP_MODE_ADDR 0x1D14 1861 #define MT6373_RG_LDO_VIO28_HW5_OP_MODE_ADDR 0x1D14 1862 #define MT6373_RG_LDO_VIO28_HW6_OP_MODE_ADDR 0x1D14 1863 #define MT6373_RG_LDO_VFP_ONLV_EN_ADDR 0x1D16 1864 #define MT6373_RG_LDO_VFP_ONLV_EN_SHIFT 3 1865 #define MT6373_RG_LDO_VFP_RC0_OP_EN_ADDR 0x1D1A 1866 #define MT6373_RG_LDO_VFP_RC1_OP_EN_ADDR 0x1D1A 1867 #define MT6373_RG_LDO_VFP_RC2_OP_EN_ADDR 0x1D1A 1868 #define MT6373_RG_LDO_VFP_RC3_OP_EN_ADDR 0x1D1A 1869 #define MT6373_RG_LDO_VFP_RC4_OP_EN_ADDR 0x1D1A 1870 #define MT6373_RG_LDO_VFP_RC5_OP_EN_ADDR 0x1D1A 1871 #define MT6373_RG_LDO_VFP_RC6_OP_EN_ADDR 0x1D1A 1872 #define MT6373_RG_LDO_VFP_RC7_OP_EN_ADDR 0x1D1A 1873 #define MT6373_RG_LDO_VFP_RC8_OP_EN_ADDR 0x1D1B 1874 #define MT6373_RG_LDO_VFP_RC9_OP_EN_ADDR 0x1D1B 1875 #define MT6373_RG_LDO_VFP_RC10_OP_EN_ADDR 0x1D1B 1876 #define MT6373_RG_LDO_VFP_RC11_OP_EN_ADDR 0x1D1B 1877 #define MT6373_RG_LDO_VFP_RC12_OP_EN_ADDR 0x1D1B 1878 #define MT6373_RG_LDO_VFP_RC13_OP_EN_ADDR 0x1D1B 1879 #define MT6373_RG_LDO_VFP_HW0_OP_EN_ADDR 0x1D1C 1880 #define MT6373_RG_LDO_VFP_HW1_OP_EN_ADDR 0x1D1C 1881 #define MT6373_RG_LDO_VFP_HW2_OP_EN_ADDR 0x1D1C 1882 #define MT6373_RG_LDO_VFP_HW3_OP_EN_ADDR 0x1D1C 1883 #define MT6373_RG_LDO_VFP_HW4_OP_EN_ADDR 0x1D1C 1884 #define MT6373_RG_LDO_VFP_HW5_OP_EN_ADDR 0x1D1C 1885 #define MT6373_RG_LDO_VFP_HW6_OP_EN_ADDR 0x1D1C 1886 #define MT6373_RG_LDO_VFP_SW_OP_EN_ADDR 0x1D1C 1887 #define MT6373_RG_LDO_VFP_RC0_OP_CFG_ADDR 0x1D1D 1888 #define MT6373_RG_LDO_VFP_RC1_OP_CFG_ADDR 0x1D1D 1889 #define MT6373_RG_LDO_VFP_RC2_OP_CFG_ADDR 0x1D1D 1890 #define MT6373_RG_LDO_VFP_RC3_OP_CFG_ADDR 0x1D1D 1891 #define MT6373_RG_LDO_VFP_RC4_OP_CFG_ADDR 0x1D1D 1892 #define MT6373_RG_LDO_VFP_RC5_OP_CFG_ADDR 0x1D1D 1893 #define MT6373_RG_LDO_VFP_RC6_OP_CFG_ADDR 0x1D1D 1894 #define MT6373_RG_LDO_VFP_RC7_OP_CFG_ADDR 0x1D1D 1895 #define MT6373_RG_LDO_VFP_RC8_OP_CFG_ADDR 0x1D1E 1896 #define MT6373_RG_LDO_VFP_RC9_OP_CFG_ADDR 0x1D1E 1897 #define MT6373_RG_LDO_VFP_RC10_OP_CFG_ADDR 0x1D1E 1898 #define MT6373_RG_LDO_VFP_RC11_OP_CFG_ADDR 0x1D1E 1899 #define MT6373_RG_LDO_VFP_RC12_OP_CFG_ADDR 0x1D1E 1900 #define MT6373_RG_LDO_VFP_RC13_OP_CFG_ADDR 0x1D1E 1901 #define MT6373_RG_LDO_VFP_HW0_OP_CFG_ADDR 0x1D1F 1902 #define MT6373_RG_LDO_VFP_HW1_OP_CFG_ADDR 0x1D1F 1903 #define MT6373_RG_LDO_VFP_HW2_OP_CFG_ADDR 0x1D1F 1904 #define MT6373_RG_LDO_VFP_HW3_OP_CFG_ADDR 0x1D1F 1905 #define MT6373_RG_LDO_VFP_HW4_OP_CFG_ADDR 0x1D1F 1906 #define MT6373_RG_LDO_VFP_HW5_OP_CFG_ADDR 0x1D1F 1907 #define MT6373_RG_LDO_VFP_HW6_OP_CFG_ADDR 0x1D1F 1908 #define MT6373_RG_LDO_VFP_SW_OP_CFG_ADDR 0x1D1F 1909 #define MT6373_RG_LDO_VFP_RC0_OP_MODE_ADDR 0x1D20 1910 #define MT6373_RG_LDO_VFP_RC1_OP_MODE_ADDR 0x1D20 1911 #define MT6373_RG_LDO_VFP_RC2_OP_MODE_ADDR 0x1D20 1912 #define MT6373_RG_LDO_VFP_RC3_OP_MODE_ADDR 0x1D20 1913 #define MT6373_RG_LDO_VFP_RC4_OP_MODE_ADDR 0x1D20 1914 #define MT6373_RG_LDO_VFP_RC5_OP_MODE_ADDR 0x1D20 1915 #define MT6373_RG_LDO_VFP_RC6_OP_MODE_ADDR 0x1D20 1916 #define MT6373_RG_LDO_VFP_RC7_OP_MODE_ADDR 0x1D20 1917 #define MT6373_RG_LDO_VFP_RC8_OP_MODE_ADDR 0x1D21 1918 #define MT6373_RG_LDO_VFP_RC9_OP_MODE_ADDR 0x1D21 1919 #define MT6373_RG_LDO_VFP_RC10_OP_MODE_ADDR 0x1D21 1920 #define MT6373_RG_LDO_VFP_RC11_OP_MODE_ADDR 0x1D21 1921 #define MT6373_RG_LDO_VFP_RC12_OP_MODE_ADDR 0x1D21 1922 #define MT6373_RG_LDO_VFP_RC13_OP_MODE_ADDR 0x1D21 1923 #define MT6373_RG_LDO_VFP_HW0_OP_MODE_ADDR 0x1D22 1924 #define MT6373_RG_LDO_VFP_HW1_OP_MODE_ADDR 0x1D22 1925 #define MT6373_RG_LDO_VFP_HW2_OP_MODE_ADDR 0x1D22 1926 #define MT6373_RG_LDO_VFP_HW3_OP_MODE_ADDR 0x1D22 1927 #define MT6373_RG_LDO_VFP_HW4_OP_MODE_ADDR 0x1D22 1928 #define MT6373_RG_LDO_VFP_HW5_OP_MODE_ADDR 0x1D22 1929 #define MT6373_RG_LDO_VFP_HW6_OP_MODE_ADDR 0x1D22 1930 #define MT6373_RG_LDO_VTP_ONLV_EN_ADDR 0x1D24 1931 #define MT6373_RG_LDO_VTP_ONLV_EN_SHIFT 3 1932 #define MT6373_RG_LDO_VTP_RC0_OP_EN_ADDR 0x1D28 1933 #define MT6373_RG_LDO_VTP_RC1_OP_EN_ADDR 0x1D28 1934 #define MT6373_RG_LDO_VTP_RC2_OP_EN_ADDR 0x1D28 1935 #define MT6373_RG_LDO_VTP_RC3_OP_EN_ADDR 0x1D28 1936 #define MT6373_RG_LDO_VTP_RC4_OP_EN_ADDR 0x1D28 1937 #define MT6373_RG_LDO_VTP_RC5_OP_EN_ADDR 0x1D28 1938 #define MT6373_RG_LDO_VTP_RC6_OP_EN_ADDR 0x1D28 1939 #define MT6373_RG_LDO_VTP_RC7_OP_EN_ADDR 0x1D28 1940 #define MT6373_RG_LDO_VTP_RC8_OP_EN_ADDR 0x1D29 1941 #define MT6373_RG_LDO_VTP_RC9_OP_EN_ADDR 0x1D29 1942 #define MT6373_RG_LDO_VTP_RC10_OP_EN_ADDR 0x1D29 1943 #define MT6373_RG_LDO_VTP_RC11_OP_EN_ADDR 0x1D29 1944 #define MT6373_RG_LDO_VTP_RC12_OP_EN_ADDR 0x1D29 1945 #define MT6373_RG_LDO_VTP_RC13_OP_EN_ADDR 0x1D29 1946 #define MT6373_RG_LDO_VTP_HW0_OP_EN_ADDR 0x1D2A 1947 #define MT6373_RG_LDO_VTP_HW1_OP_EN_ADDR 0x1D2A 1948 #define MT6373_RG_LDO_VTP_HW2_OP_EN_ADDR 0x1D2A 1949 #define MT6373_RG_LDO_VTP_HW3_OP_EN_ADDR 0x1D2A 1950 #define MT6373_RG_LDO_VTP_HW4_OP_EN_ADDR 0x1D2A 1951 #define MT6373_RG_LDO_VTP_HW5_OP_EN_ADDR 0x1D2A 1952 #define MT6373_RG_LDO_VTP_HW6_OP_EN_ADDR 0x1D2A 1953 #define MT6373_RG_LDO_VTP_SW_OP_EN_ADDR 0x1D2A 1954 #define MT6373_RG_LDO_VTP_RC0_OP_CFG_ADDR 0x1D2B 1955 #define MT6373_RG_LDO_VTP_RC1_OP_CFG_ADDR 0x1D2B 1956 #define MT6373_RG_LDO_VTP_RC2_OP_CFG_ADDR 0x1D2B 1957 #define MT6373_RG_LDO_VTP_RC3_OP_CFG_ADDR 0x1D2B 1958 #define MT6373_RG_LDO_VTP_RC4_OP_CFG_ADDR 0x1D2B 1959 #define MT6373_RG_LDO_VTP_RC5_OP_CFG_ADDR 0x1D2B 1960 #define MT6373_RG_LDO_VTP_RC6_OP_CFG_ADDR 0x1D2B 1961 #define MT6373_RG_LDO_VTP_RC7_OP_CFG_ADDR 0x1D2B 1962 #define MT6373_RG_LDO_VTP_RC8_OP_CFG_ADDR 0x1D2C 1963 #define MT6373_RG_LDO_VTP_RC9_OP_CFG_ADDR 0x1D2C 1964 #define MT6373_RG_LDO_VTP_RC10_OP_CFG_ADDR 0x1D2C 1965 #define MT6373_RG_LDO_VTP_RC11_OP_CFG_ADDR 0x1D2C 1966 #define MT6373_RG_LDO_VTP_RC12_OP_CFG_ADDR 0x1D2C 1967 #define MT6373_RG_LDO_VTP_RC13_OP_CFG_ADDR 0x1D2C 1968 #define MT6373_RG_LDO_VTP_HW0_OP_CFG_ADDR 0x1D2D 1969 #define MT6373_RG_LDO_VTP_HW1_OP_CFG_ADDR 0x1D2D 1970 #define MT6373_RG_LDO_VTP_HW2_OP_CFG_ADDR 0x1D2D 1971 #define MT6373_RG_LDO_VTP_HW3_OP_CFG_ADDR 0x1D2D 1972 #define MT6373_RG_LDO_VTP_HW4_OP_CFG_ADDR 0x1D2D 1973 #define MT6373_RG_LDO_VTP_HW5_OP_CFG_ADDR 0x1D2D 1974 #define MT6373_RG_LDO_VTP_HW6_OP_CFG_ADDR 0x1D2D 1975 #define MT6373_RG_LDO_VTP_SW_OP_CFG_ADDR 0x1D2D 1976 #define MT6373_RG_LDO_VTP_RC0_OP_MODE_ADDR 0x1D2E 1977 #define MT6373_RG_LDO_VTP_RC1_OP_MODE_ADDR 0x1D2E 1978 #define MT6373_RG_LDO_VTP_RC2_OP_MODE_ADDR 0x1D2E 1979 #define MT6373_RG_LDO_VTP_RC3_OP_MODE_ADDR 0x1D2E 1980 #define MT6373_RG_LDO_VTP_RC4_OP_MODE_ADDR 0x1D2E 1981 #define MT6373_RG_LDO_VTP_RC5_OP_MODE_ADDR 0x1D2E 1982 #define MT6373_RG_LDO_VTP_RC6_OP_MODE_ADDR 0x1D2E 1983 #define MT6373_RG_LDO_VTP_RC7_OP_MODE_ADDR 0x1D2E 1984 #define MT6373_RG_LDO_VTP_RC8_OP_MODE_ADDR 0x1D2F 1985 #define MT6373_RG_LDO_VTP_RC9_OP_MODE_ADDR 0x1D2F 1986 #define MT6373_RG_LDO_VTP_RC10_OP_MODE_ADDR 0x1D2F 1987 #define MT6373_RG_LDO_VTP_RC11_OP_MODE_ADDR 0x1D2F 1988 #define MT6373_RG_LDO_VTP_RC12_OP_MODE_ADDR 0x1D2F 1989 #define MT6373_RG_LDO_VTP_RC13_OP_MODE_ADDR 0x1D2F 1990 #define MT6373_RG_LDO_VTP_HW0_OP_MODE_ADDR 0x1D30 1991 #define MT6373_RG_LDO_VTP_HW1_OP_MODE_ADDR 0x1D30 1992 #define MT6373_RG_LDO_VTP_HW2_OP_MODE_ADDR 0x1D30 1993 #define MT6373_RG_LDO_VTP_HW3_OP_MODE_ADDR 0x1D30 1994 #define MT6373_RG_LDO_VTP_HW4_OP_MODE_ADDR 0x1D30 1995 #define MT6373_RG_LDO_VTP_HW5_OP_MODE_ADDR 0x1D30 1996 #define MT6373_RG_LDO_VTP_HW6_OP_MODE_ADDR 0x1D30 1997 #define MT6373_RG_LDO_VSIM1_ONLV_EN_ADDR 0x1D32 1998 #define MT6373_RG_LDO_VSIM1_ONLV_EN_SHIFT 3 1999 #define MT6373_RG_LDO_VSIM1_RC0_OP_EN_ADDR 0x1D36 2000 #define MT6373_RG_LDO_VSIM1_RC1_OP_EN_ADDR 0x1D36 2001 #define MT6373_RG_LDO_VSIM1_RC2_OP_EN_ADDR 0x1D36 2002 #define MT6373_RG_LDO_VSIM1_RC3_OP_EN_ADDR 0x1D36 2003 #define MT6373_RG_LDO_VSIM1_RC4_OP_EN_ADDR 0x1D36 2004 #define MT6373_RG_LDO_VSIM1_RC5_OP_EN_ADDR 0x1D36 2005 #define MT6373_RG_LDO_VSIM1_RC6_OP_EN_ADDR 0x1D36 2006 #define MT6373_RG_LDO_VSIM1_RC7_OP_EN_ADDR 0x1D36 2007 #define MT6373_RG_LDO_VSIM1_RC8_OP_EN_ADDR 0x1D37 2008 #define MT6373_RG_LDO_VSIM1_RC9_OP_EN_ADDR 0x1D37 2009 #define MT6373_RG_LDO_VSIM1_RC10_OP_EN_ADDR 0x1D37 2010 #define MT6373_RG_LDO_VSIM1_RC11_OP_EN_ADDR 0x1D37 2011 #define MT6373_RG_LDO_VSIM1_RC12_OP_EN_ADDR 0x1D37 2012 #define MT6373_RG_LDO_VSIM1_RC13_OP_EN_ADDR 0x1D37 2013 #define MT6373_RG_LDO_VSIM1_HW0_OP_EN_ADDR 0x1D38 2014 #define MT6373_RG_LDO_VSIM1_HW1_OP_EN_ADDR 0x1D38 2015 #define MT6373_RG_LDO_VSIM1_HW2_OP_EN_ADDR 0x1D38 2016 #define MT6373_RG_LDO_VSIM1_HW3_OP_EN_ADDR 0x1D38 2017 #define MT6373_RG_LDO_VSIM1_HW4_OP_EN_ADDR 0x1D38 2018 #define MT6373_RG_LDO_VSIM1_HW5_OP_EN_ADDR 0x1D38 2019 #define MT6373_RG_LDO_VSIM1_HW6_OP_EN_ADDR 0x1D38 2020 #define MT6373_RG_LDO_VSIM1_SW_OP_EN_ADDR 0x1D38 2021 #define MT6373_RG_LDO_VSIM1_RC0_OP_CFG_ADDR 0x1D39 2022 #define MT6373_RG_LDO_VSIM1_RC1_OP_CFG_ADDR 0x1D39 2023 #define MT6373_RG_LDO_VSIM1_RC2_OP_CFG_ADDR 0x1D39 2024 #define MT6373_RG_LDO_VSIM1_RC3_OP_CFG_ADDR 0x1D39 2025 #define MT6373_RG_LDO_VSIM1_RC4_OP_CFG_ADDR 0x1D39 2026 #define MT6373_RG_LDO_VSIM1_RC5_OP_CFG_ADDR 0x1D39 2027 #define MT6373_RG_LDO_VSIM1_RC6_OP_CFG_ADDR 0x1D39 2028 #define MT6373_RG_LDO_VSIM1_RC7_OP_CFG_ADDR 0x1D39 2029 #define MT6373_RG_LDO_VSIM1_RC8_OP_CFG_ADDR 0x1D3A 2030 #define MT6373_RG_LDO_VSIM1_RC9_OP_CFG_ADDR 0x1D3A 2031 #define MT6373_RG_LDO_VSIM1_RC10_OP_CFG_ADDR 0x1D3A 2032 #define MT6373_RG_LDO_VSIM1_RC11_OP_CFG_ADDR 0x1D3A 2033 #define MT6373_RG_LDO_VSIM1_RC12_OP_CFG_ADDR 0x1D3A 2034 #define MT6373_RG_LDO_VSIM1_RC13_OP_CFG_ADDR 0x1D3A 2035 #define MT6373_RG_LDO_VSIM1_HW0_OP_CFG_ADDR 0x1D3B 2036 #define MT6373_RG_LDO_VSIM1_HW1_OP_CFG_ADDR 0x1D3B 2037 #define MT6373_RG_LDO_VSIM1_HW2_OP_CFG_ADDR 0x1D3B 2038 #define MT6373_RG_LDO_VSIM1_HW3_OP_CFG_ADDR 0x1D3B 2039 #define MT6373_RG_LDO_VSIM1_HW4_OP_CFG_ADDR 0x1D3B 2040 #define MT6373_RG_LDO_VSIM1_HW5_OP_CFG_ADDR 0x1D3B 2041 #define MT6373_RG_LDO_VSIM1_HW6_OP_CFG_ADDR 0x1D3B 2042 #define MT6373_RG_LDO_VSIM1_SW_OP_CFG_ADDR 0x1D3B 2043 #define MT6373_RG_LDO_VSIM1_RC0_OP_MODE_ADDR 0x1D3C 2044 #define MT6373_RG_LDO_VSIM1_RC1_OP_MODE_ADDR 0x1D3C 2045 #define MT6373_RG_LDO_VSIM1_RC2_OP_MODE_ADDR 0x1D3C 2046 #define MT6373_RG_LDO_VSIM1_RC3_OP_MODE_ADDR 0x1D3C 2047 #define MT6373_RG_LDO_VSIM1_RC4_OP_MODE_ADDR 0x1D3C 2048 #define MT6373_RG_LDO_VSIM1_RC5_OP_MODE_ADDR 0x1D3C 2049 #define MT6373_RG_LDO_VSIM1_RC6_OP_MODE_ADDR 0x1D3C 2050 #define MT6373_RG_LDO_VSIM1_RC7_OP_MODE_ADDR 0x1D3C 2051 #define MT6373_RG_LDO_VSIM1_RC8_OP_MODE_ADDR 0x1D3D 2052 #define MT6373_RG_LDO_VSIM1_RC9_OP_MODE_ADDR 0x1D3D 2053 #define MT6373_RG_LDO_VSIM1_RC10_OP_MODE_ADDR 0x1D3D 2054 #define MT6373_RG_LDO_VSIM1_RC11_OP_MODE_ADDR 0x1D3D 2055 #define MT6373_RG_LDO_VSIM1_RC12_OP_MODE_ADDR 0x1D3D 2056 #define MT6373_RG_LDO_VSIM1_RC13_OP_MODE_ADDR 0x1D3D 2057 #define MT6373_RG_LDO_VSIM1_HW0_OP_MODE_ADDR 0x1D3E 2058 #define MT6373_RG_LDO_VSIM1_HW1_OP_MODE_ADDR 0x1D3E 2059 #define MT6373_RG_LDO_VSIM1_HW2_OP_MODE_ADDR 0x1D3E 2060 #define MT6373_RG_LDO_VSIM1_HW3_OP_MODE_ADDR 0x1D3E 2061 #define MT6373_RG_LDO_VSIM1_HW4_OP_MODE_ADDR 0x1D3E 2062 #define MT6373_RG_LDO_VSIM1_HW5_OP_MODE_ADDR 0x1D3E 2063 #define MT6373_RG_LDO_VSIM1_HW6_OP_MODE_ADDR 0x1D3E 2064 #define MT6373_RG_LDO_VSIM2_ONLV_EN_ADDR 0x1D41 2065 #define MT6373_RG_LDO_VSIM2_ONLV_EN_SHIFT 3 2066 #define MT6373_RG_LDO_VSIM2_RC0_OP_EN_ADDR 0x1D45 2067 #define MT6373_RG_LDO_VSIM2_RC1_OP_EN_ADDR 0x1D45 2068 #define MT6373_RG_LDO_VSIM2_RC2_OP_EN_ADDR 0x1D45 2069 #define MT6373_RG_LDO_VSIM2_RC3_OP_EN_ADDR 0x1D45 2070 #define MT6373_RG_LDO_VSIM2_RC4_OP_EN_ADDR 0x1D45 2071 #define MT6373_RG_LDO_VSIM2_RC5_OP_EN_ADDR 0x1D45 2072 #define MT6373_RG_LDO_VSIM2_RC6_OP_EN_ADDR 0x1D45 2073 #define MT6373_RG_LDO_VSIM2_RC7_OP_EN_ADDR 0x1D45 2074 #define MT6373_RG_LDO_VSIM2_RC8_OP_EN_ADDR 0x1D46 2075 #define MT6373_RG_LDO_VSIM2_RC9_OP_EN_ADDR 0x1D46 2076 #define MT6373_RG_LDO_VSIM2_RC10_OP_EN_ADDR 0x1D46 2077 #define MT6373_RG_LDO_VSIM2_RC11_OP_EN_ADDR 0x1D46 2078 #define MT6373_RG_LDO_VSIM2_RC12_OP_EN_ADDR 0x1D46 2079 #define MT6373_RG_LDO_VSIM2_RC13_OP_EN_ADDR 0x1D46 2080 #define MT6373_RG_LDO_VSIM2_HW0_OP_EN_ADDR 0x1D47 2081 #define MT6373_RG_LDO_VSIM2_HW1_OP_EN_ADDR 0x1D47 2082 #define MT6373_RG_LDO_VSIM2_HW2_OP_EN_ADDR 0x1D47 2083 #define MT6373_RG_LDO_VSIM2_HW3_OP_EN_ADDR 0x1D47 2084 #define MT6373_RG_LDO_VSIM2_HW4_OP_EN_ADDR 0x1D47 2085 #define MT6373_RG_LDO_VSIM2_HW5_OP_EN_ADDR 0x1D47 2086 #define MT6373_RG_LDO_VSIM2_HW6_OP_EN_ADDR 0x1D47 2087 #define MT6373_RG_LDO_VSIM2_SW_OP_EN_ADDR 0x1D47 2088 #define MT6373_RG_LDO_VSIM2_RC0_OP_CFG_ADDR 0x1D48 2089 #define MT6373_RG_LDO_VSIM2_RC1_OP_CFG_ADDR 0x1D48 2090 #define MT6373_RG_LDO_VSIM2_RC2_OP_CFG_ADDR 0x1D48 2091 #define MT6373_RG_LDO_VSIM2_RC3_OP_CFG_ADDR 0x1D48 2092 #define MT6373_RG_LDO_VSIM2_RC4_OP_CFG_ADDR 0x1D48 2093 #define MT6373_RG_LDO_VSIM2_RC5_OP_CFG_ADDR 0x1D48 2094 #define MT6373_RG_LDO_VSIM2_RC6_OP_CFG_ADDR 0x1D48 2095 #define MT6373_RG_LDO_VSIM2_RC7_OP_CFG_ADDR 0x1D48 2096 #define MT6373_RG_LDO_VSIM2_RC8_OP_CFG_ADDR 0x1D49 2097 #define MT6373_RG_LDO_VSIM2_RC9_OP_CFG_ADDR 0x1D49 2098 #define MT6373_RG_LDO_VSIM2_RC10_OP_CFG_ADDR 0x1D49 2099 #define MT6373_RG_LDO_VSIM2_RC11_OP_CFG_ADDR 0x1D49 2100 #define MT6373_RG_LDO_VSIM2_RC12_OP_CFG_ADDR 0x1D49 2101 #define MT6373_RG_LDO_VSIM2_RC13_OP_CFG_ADDR 0x1D49 2102 #define MT6373_RG_LDO_VSIM2_HW0_OP_CFG_ADDR 0x1D4A 2103 #define MT6373_RG_LDO_VSIM2_HW1_OP_CFG_ADDR 0x1D4A 2104 #define MT6373_RG_LDO_VSIM2_HW2_OP_CFG_ADDR 0x1D4A 2105 #define MT6373_RG_LDO_VSIM2_HW3_OP_CFG_ADDR 0x1D4A 2106 #define MT6373_RG_LDO_VSIM2_HW4_OP_CFG_ADDR 0x1D4A 2107 #define MT6373_RG_LDO_VSIM2_HW5_OP_CFG_ADDR 0x1D4A 2108 #define MT6373_RG_LDO_VSIM2_HW6_OP_CFG_ADDR 0x1D4A 2109 #define MT6373_RG_LDO_VSIM2_SW_OP_CFG_ADDR 0x1D4A 2110 #define MT6373_RG_LDO_VSIM2_RC0_OP_MODE_ADDR 0x1D4B 2111 #define MT6373_RG_LDO_VSIM2_RC1_OP_MODE_ADDR 0x1D4B 2112 #define MT6373_RG_LDO_VSIM2_RC2_OP_MODE_ADDR 0x1D4B 2113 #define MT6373_RG_LDO_VSIM2_RC3_OP_MODE_ADDR 0x1D4B 2114 #define MT6373_RG_LDO_VSIM2_RC4_OP_MODE_ADDR 0x1D4B 2115 #define MT6373_RG_LDO_VSIM2_RC5_OP_MODE_ADDR 0x1D4B 2116 #define MT6373_RG_LDO_VSIM2_RC6_OP_MODE_ADDR 0x1D4B 2117 #define MT6373_RG_LDO_VSIM2_RC7_OP_MODE_ADDR 0x1D4B 2118 #define MT6373_RG_LDO_VSIM2_RC8_OP_MODE_ADDR 0x1D4C 2119 #define MT6373_RG_LDO_VSIM2_RC9_OP_MODE_ADDR 0x1D4C 2120 #define MT6373_RG_LDO_VSIM2_RC10_OP_MODE_ADDR 0x1D4C 2121 #define MT6373_RG_LDO_VSIM2_RC11_OP_MODE_ADDR 0x1D4C 2122 #define MT6373_RG_LDO_VSIM2_RC12_OP_MODE_ADDR 0x1D4C 2123 #define MT6373_RG_LDO_VSIM2_RC13_OP_MODE_ADDR 0x1D4C 2124 #define MT6373_RG_LDO_VSIM2_HW0_OP_MODE_ADDR 0x1D4D 2125 #define MT6373_RG_LDO_VSIM2_HW1_OP_MODE_ADDR 0x1D4D 2126 #define MT6373_RG_LDO_VSIM2_HW2_OP_MODE_ADDR 0x1D4D 2127 #define MT6373_RG_LDO_VSIM2_HW3_OP_MODE_ADDR 0x1D4D 2128 #define MT6373_RG_LDO_VSIM2_HW4_OP_MODE_ADDR 0x1D4D 2129 #define MT6373_RG_LDO_VSIM2_HW5_OP_MODE_ADDR 0x1D4D 2130 #define MT6373_RG_LDO_VSIM2_HW6_OP_MODE_ADDR 0x1D4D 2131 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_ONLV_EN_ADDR 0x1D88 2132 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_ONLV_EN_SHIFT 3 2133 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_VOSEL_SLEEP_ADDR 0x1D8D 2134 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC0_OP_EN_ADDR 0x1D94 2135 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC1_OP_EN_ADDR 0x1D94 2136 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC2_OP_EN_ADDR 0x1D94 2137 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC3_OP_EN_ADDR 0x1D94 2138 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC4_OP_EN_ADDR 0x1D94 2139 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC5_OP_EN_ADDR 0x1D94 2140 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC6_OP_EN_ADDR 0x1D94 2141 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC7_OP_EN_ADDR 0x1D94 2142 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC8_OP_EN_ADDR 0x1D95 2143 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC9_OP_EN_ADDR 0x1D95 2144 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC10_OP_EN_ADDR 0x1D95 2145 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC11_OP_EN_ADDR 0x1D95 2146 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC12_OP_EN_ADDR 0x1D95 2147 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC13_OP_EN_ADDR 0x1D95 2148 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW0_OP_EN_ADDR 0x1D96 2149 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW1_OP_EN_ADDR 0x1D96 2150 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW2_OP_EN_ADDR 0x1D96 2151 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW3_OP_EN_ADDR 0x1D96 2152 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW4_OP_EN_ADDR 0x1D96 2153 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW5_OP_EN_ADDR 0x1D96 2154 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW6_OP_EN_ADDR 0x1D96 2155 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_SW_OP_EN_ADDR 0x1D96 2156 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC0_OP_CFG_ADDR 0x1D97 2157 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC1_OP_CFG_ADDR 0x1D97 2158 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC2_OP_CFG_ADDR 0x1D97 2159 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC3_OP_CFG_ADDR 0x1D97 2160 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC4_OP_CFG_ADDR 0x1D97 2161 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC5_OP_CFG_ADDR 0x1D97 2162 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC6_OP_CFG_ADDR 0x1D97 2163 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC7_OP_CFG_ADDR 0x1D97 2164 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC8_OP_CFG_ADDR 0x1D98 2165 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC9_OP_CFG_ADDR 0x1D98 2166 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC10_OP_CFG_ADDR 0x1D98 2167 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC11_OP_CFG_ADDR 0x1D98 2168 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC12_OP_CFG_ADDR 0x1D98 2169 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC13_OP_CFG_ADDR 0x1D98 2170 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW0_OP_CFG_ADDR 0x1D99 2171 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW1_OP_CFG_ADDR 0x1D99 2172 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW2_OP_CFG_ADDR 0x1D99 2173 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW3_OP_CFG_ADDR 0x1D99 2174 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW4_OP_CFG_ADDR 0x1D99 2175 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW5_OP_CFG_ADDR 0x1D99 2176 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW6_OP_CFG_ADDR 0x1D99 2177 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_SW_OP_CFG_ADDR 0x1D99 2178 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC0_OP_MODE_ADDR 0x1D9A 2179 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC1_OP_MODE_ADDR 0x1D9A 2180 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC2_OP_MODE_ADDR 0x1D9A 2181 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC3_OP_MODE_ADDR 0x1D9A 2182 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC4_OP_MODE_ADDR 0x1D9A 2183 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC5_OP_MODE_ADDR 0x1D9A 2184 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC6_OP_MODE_ADDR 0x1D9A 2185 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC7_OP_MODE_ADDR 0x1D9A 2186 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC8_OP_MODE_ADDR 0x1D9B 2187 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC9_OP_MODE_ADDR 0x1D9B 2188 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC10_OP_MODE_ADDR 0x1D9B 2189 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC11_OP_MODE_ADDR 0x1D9B 2190 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC12_OP_MODE_ADDR 0x1D9B 2191 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_RC13_OP_MODE_ADDR 0x1D9B 2192 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW0_OP_MODE_ADDR 0x1D9C 2193 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW1_OP_MODE_ADDR 0x1D9C 2194 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW2_OP_MODE_ADDR 0x1D9C 2195 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW3_OP_MODE_ADDR 0x1D9C 2196 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW4_OP_MODE_ADDR 0x1D9C 2197 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW5_OP_MODE_ADDR 0x1D9C 2198 #define MT6373_RG_LDO_VSRAM_DIGRF_AIF_HW6_OP_MODE_ADDR 0x1D9C 2199 2200 #endif /* MT6373_LOWPOWER_REG_H */ 2201