1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved 3 * SPDX-License-Identifier: BSD-3-Clause 4 */ 5 6 #ifndef MT6359P_LOWPOWER_REG_H 7 #define MT6359P_LOWPOWER_REG_H 8 9 #define MT6359P_RG_BUCK_VPU_VOSEL_SLEEP_ADDR 0x148e 10 #define MT6359P_RG_BUCK_VPU_HW0_OP_EN_ADDR 0x1494 11 #define MT6359P_RG_BUCK_VPU_HW1_OP_EN_ADDR 0x1494 12 #define MT6359P_RG_BUCK_VPU_HW2_OP_EN_ADDR 0x1494 13 #define MT6359P_RG_BUCK_VPU_HW3_OP_EN_ADDR 0x1494 14 #define MT6359P_RG_BUCK_VPU_HW4_OP_EN_ADDR 0x1494 15 #define MT6359P_RG_BUCK_VPU_HW5_OP_EN_ADDR 0x1494 16 #define MT6359P_RG_BUCK_VPU_HW6_OP_EN_ADDR 0x1494 17 #define MT6359P_RG_BUCK_VPU_HW7_OP_EN_ADDR 0x1494 18 #define MT6359P_RG_BUCK_VPU_HW8_OP_EN_ADDR 0x1494 19 #define MT6359P_RG_BUCK_VPU_HW9_OP_EN_ADDR 0x1494 20 #define MT6359P_RG_BUCK_VPU_HW10_OP_EN_ADDR 0x1494 21 #define MT6359P_RG_BUCK_VPU_HW11_OP_EN_ADDR 0x1494 22 #define MT6359P_RG_BUCK_VPU_HW12_OP_EN_ADDR 0x1494 23 #define MT6359P_RG_BUCK_VPU_HW13_OP_EN_ADDR 0x1494 24 #define MT6359P_RG_BUCK_VPU_HW14_OP_EN_ADDR 0x1494 25 #define MT6359P_RG_BUCK_VPU_SW_OP_EN_ADDR 0x1494 26 #define MT6359P_RG_BUCK_VPU_HW0_OP_CFG_ADDR 0x149a 27 #define MT6359P_RG_BUCK_VPU_HW1_OP_CFG_ADDR 0x149a 28 #define MT6359P_RG_BUCK_VPU_HW2_OP_CFG_ADDR 0x149a 29 #define MT6359P_RG_BUCK_VPU_HW3_OP_CFG_ADDR 0x149a 30 #define MT6359P_RG_BUCK_VPU_HW4_OP_CFG_ADDR 0x149a 31 #define MT6359P_RG_BUCK_VPU_HW5_OP_CFG_ADDR 0x149a 32 #define MT6359P_RG_BUCK_VPU_HW6_OP_CFG_ADDR 0x149a 33 #define MT6359P_RG_BUCK_VPU_HW7_OP_CFG_ADDR 0x149a 34 #define MT6359P_RG_BUCK_VPU_HW8_OP_CFG_ADDR 0x149a 35 #define MT6359P_RG_BUCK_VPU_HW9_OP_CFG_ADDR 0x149a 36 #define MT6359P_RG_BUCK_VPU_HW10_OP_CFG_ADDR 0x149a 37 #define MT6359P_RG_BUCK_VPU_HW11_OP_CFG_ADDR 0x149a 38 #define MT6359P_RG_BUCK_VPU_HW12_OP_CFG_ADDR 0x149a 39 #define MT6359P_RG_BUCK_VPU_HW13_OP_CFG_ADDR 0x149a 40 #define MT6359P_RG_BUCK_VPU_HW14_OP_CFG_ADDR 0x149a 41 #define MT6359P_RG_BUCK_VPU_HW0_OP_MODE_ADDR 0x14a0 42 #define MT6359P_RG_BUCK_VPU_HW0_OP_MODE_SHIFT 0 43 #define MT6359P_RG_BUCK_VPU_HW1_OP_MODE_ADDR 0x14a0 44 #define MT6359P_RG_BUCK_VPU_HW1_OP_MODE_SHIFT 1 45 #define MT6359P_RG_BUCK_VPU_HW2_OP_MODE_ADDR 0x14a0 46 #define MT6359P_RG_BUCK_VPU_HW2_OP_MODE_SHIFT 2 47 #define MT6359P_RG_BUCK_VPU_HW3_OP_MODE_ADDR 0x14a0 48 #define MT6359P_RG_BUCK_VPU_HW3_OP_MODE_SHIFT 3 49 #define MT6359P_RG_BUCK_VPU_HW4_OP_MODE_ADDR 0x14a0 50 #define MT6359P_RG_BUCK_VPU_HW4_OP_MODE_SHIFT 4 51 #define MT6359P_RG_BUCK_VPU_HW5_OP_MODE_ADDR 0x14a0 52 #define MT6359P_RG_BUCK_VPU_HW5_OP_MODE_SHIFT 5 53 #define MT6359P_RG_BUCK_VPU_HW6_OP_MODE_ADDR 0x14a0 54 #define MT6359P_RG_BUCK_VPU_HW6_OP_MODE_SHIFT 6 55 #define MT6359P_RG_BUCK_VPU_HW7_OP_MODE_ADDR 0x14a0 56 #define MT6359P_RG_BUCK_VPU_HW7_OP_MODE_SHIFT 7 57 #define MT6359P_RG_BUCK_VPU_HW8_OP_MODE_ADDR 0x14a0 58 #define MT6359P_RG_BUCK_VPU_HW8_OP_MODE_SHIFT 8 59 #define MT6359P_RG_BUCK_VPU_HW9_OP_MODE_ADDR 0x14a0 60 #define MT6359P_RG_BUCK_VPU_HW9_OP_MODE_SHIFT 9 61 #define MT6359P_RG_BUCK_VPU_HW10_OP_MODE_ADDR 0x14a0 62 #define MT6359P_RG_BUCK_VPU_HW10_OP_MODE_SHIFT 10 63 #define MT6359P_RG_BUCK_VPU_HW11_OP_MODE_ADDR 0x14a0 64 #define MT6359P_RG_BUCK_VPU_HW11_OP_MODE_SHIFT 11 65 #define MT6359P_RG_BUCK_VPU_HW12_OP_MODE_ADDR 0x14a0 66 #define MT6359P_RG_BUCK_VPU_HW12_OP_MODE_SHIFT 12 67 #define MT6359P_RG_BUCK_VPU_HW13_OP_MODE_ADDR 0x14a0 68 #define MT6359P_RG_BUCK_VPU_HW13_OP_MODE_SHIFT 13 69 #define MT6359P_RG_BUCK_VPU_HW14_OP_MODE_ADDR 0x14a0 70 #define MT6359P_RG_BUCK_VPU_HW14_OP_MODE_SHIFT 14 71 #define MT6359P_RG_BUCK_VCORE_VOSEL_SLEEP_ADDR 0x150e 72 #define MT6359P_RG_BUCK_VCORE_HW0_OP_EN_ADDR 0x1514 73 #define MT6359P_RG_BUCK_VCORE_HW1_OP_EN_ADDR 0x1514 74 #define MT6359P_RG_BUCK_VCORE_HW2_OP_EN_ADDR 0x1514 75 #define MT6359P_RG_BUCK_VCORE_HW3_OP_EN_ADDR 0x1514 76 #define MT6359P_RG_BUCK_VCORE_HW4_OP_EN_ADDR 0x1514 77 #define MT6359P_RG_BUCK_VCORE_HW5_OP_EN_ADDR 0x1514 78 #define MT6359P_RG_BUCK_VCORE_HW6_OP_EN_ADDR 0x1514 79 #define MT6359P_RG_BUCK_VCORE_HW7_OP_EN_ADDR 0x1514 80 #define MT6359P_RG_BUCK_VCORE_HW8_OP_EN_ADDR 0x1514 81 #define MT6359P_RG_BUCK_VCORE_HW9_OP_EN_ADDR 0x1514 82 #define MT6359P_RG_BUCK_VCORE_HW10_OP_EN_ADDR 0x1514 83 #define MT6359P_RG_BUCK_VCORE_HW11_OP_EN_ADDR 0x1514 84 #define MT6359P_RG_BUCK_VCORE_HW12_OP_EN_ADDR 0x1514 85 #define MT6359P_RG_BUCK_VCORE_HW13_OP_EN_ADDR 0x1514 86 #define MT6359P_RG_BUCK_VCORE_HW14_OP_EN_ADDR 0x1514 87 #define MT6359P_RG_BUCK_VCORE_SW_OP_EN_ADDR 0x1514 88 #define MT6359P_RG_BUCK_VCORE_HW0_OP_CFG_ADDR 0x151a 89 #define MT6359P_RG_BUCK_VCORE_HW1_OP_CFG_ADDR 0x151a 90 #define MT6359P_RG_BUCK_VCORE_HW2_OP_CFG_ADDR 0x151a 91 #define MT6359P_RG_BUCK_VCORE_HW3_OP_CFG_ADDR 0x151a 92 #define MT6359P_RG_BUCK_VCORE_HW4_OP_CFG_ADDR 0x151a 93 #define MT6359P_RG_BUCK_VCORE_HW5_OP_CFG_ADDR 0x151a 94 #define MT6359P_RG_BUCK_VCORE_HW6_OP_CFG_ADDR 0x151a 95 #define MT6359P_RG_BUCK_VCORE_HW7_OP_CFG_ADDR 0x151a 96 #define MT6359P_RG_BUCK_VCORE_HW8_OP_CFG_ADDR 0x151a 97 #define MT6359P_RG_BUCK_VCORE_HW9_OP_CFG_ADDR 0x151a 98 #define MT6359P_RG_BUCK_VCORE_HW10_OP_CFG_ADDR 0x151a 99 #define MT6359P_RG_BUCK_VCORE_HW11_OP_CFG_ADDR 0x151a 100 #define MT6359P_RG_BUCK_VCORE_HW12_OP_CFG_ADDR 0x151a 101 #define MT6359P_RG_BUCK_VCORE_HW13_OP_CFG_ADDR 0x151a 102 #define MT6359P_RG_BUCK_VCORE_HW14_OP_CFG_ADDR 0x151a 103 #define MT6359P_RG_BUCK_VCORE_HW0_OP_MODE_ADDR 0x1520 104 #define MT6359P_RG_BUCK_VCORE_HW0_OP_MODE_SHIFT 0 105 #define MT6359P_RG_BUCK_VCORE_HW1_OP_MODE_ADDR 0x1520 106 #define MT6359P_RG_BUCK_VCORE_HW1_OP_MODE_SHIFT 1 107 #define MT6359P_RG_BUCK_VCORE_HW2_OP_MODE_ADDR 0x1520 108 #define MT6359P_RG_BUCK_VCORE_HW2_OP_MODE_SHIFT 2 109 #define MT6359P_RG_BUCK_VCORE_HW3_OP_MODE_ADDR 0x1520 110 #define MT6359P_RG_BUCK_VCORE_HW3_OP_MODE_SHIFT 3 111 #define MT6359P_RG_BUCK_VCORE_HW4_OP_MODE_ADDR 0x1520 112 #define MT6359P_RG_BUCK_VCORE_HW4_OP_MODE_SHIFT 4 113 #define MT6359P_RG_BUCK_VCORE_HW5_OP_MODE_ADDR 0x1520 114 #define MT6359P_RG_BUCK_VCORE_HW5_OP_MODE_SHIFT 5 115 #define MT6359P_RG_BUCK_VCORE_HW6_OP_MODE_ADDR 0x1520 116 #define MT6359P_RG_BUCK_VCORE_HW6_OP_MODE_SHIFT 6 117 #define MT6359P_RG_BUCK_VCORE_HW7_OP_MODE_ADDR 0x1520 118 #define MT6359P_RG_BUCK_VCORE_HW7_OP_MODE_SHIFT 7 119 #define MT6359P_RG_BUCK_VCORE_HW8_OP_MODE_ADDR 0x1520 120 #define MT6359P_RG_BUCK_VCORE_HW8_OP_MODE_SHIFT 8 121 #define MT6359P_RG_BUCK_VCORE_HW9_OP_MODE_ADDR 0x1520 122 #define MT6359P_RG_BUCK_VCORE_HW9_OP_MODE_SHIFT 9 123 #define MT6359P_RG_BUCK_VCORE_HW10_OP_MODE_ADDR 0x1520 124 #define MT6359P_RG_BUCK_VCORE_HW10_OP_MODE_SHIFT 10 125 #define MT6359P_RG_BUCK_VCORE_HW11_OP_MODE_ADDR 0x1520 126 #define MT6359P_RG_BUCK_VCORE_HW11_OP_MODE_SHIFT 11 127 #define MT6359P_RG_BUCK_VCORE_HW12_OP_MODE_ADDR 0x1520 128 #define MT6359P_RG_BUCK_VCORE_HW12_OP_MODE_SHIFT 12 129 #define MT6359P_RG_BUCK_VCORE_HW13_OP_MODE_ADDR 0x1520 130 #define MT6359P_RG_BUCK_VCORE_HW13_OP_MODE_SHIFT 13 131 #define MT6359P_RG_BUCK_VCORE_HW14_OP_MODE_ADDR 0x1520 132 #define MT6359P_RG_BUCK_VCORE_HW14_OP_MODE_SHIFT 14 133 #define MT6359P_RG_BUCK_VGPU11_VOSEL_SLEEP_ADDR 0x158e 134 #define MT6359P_RG_BUCK_VGPU11_HW0_OP_EN_ADDR 0x1594 135 #define MT6359P_RG_BUCK_VGPU11_HW1_OP_EN_ADDR 0x1594 136 #define MT6359P_RG_BUCK_VGPU11_HW2_OP_EN_ADDR 0x1594 137 #define MT6359P_RG_BUCK_VGPU11_HW3_OP_EN_ADDR 0x1594 138 #define MT6359P_RG_BUCK_VGPU11_HW4_OP_EN_ADDR 0x1594 139 #define MT6359P_RG_BUCK_VGPU11_HW5_OP_EN_ADDR 0x1594 140 #define MT6359P_RG_BUCK_VGPU11_HW6_OP_EN_ADDR 0x1594 141 #define MT6359P_RG_BUCK_VGPU11_HW7_OP_EN_ADDR 0x1594 142 #define MT6359P_RG_BUCK_VGPU11_HW8_OP_EN_ADDR 0x1594 143 #define MT6359P_RG_BUCK_VGPU11_HW9_OP_EN_ADDR 0x1594 144 #define MT6359P_RG_BUCK_VGPU11_HW10_OP_EN_ADDR 0x1594 145 #define MT6359P_RG_BUCK_VGPU11_HW11_OP_EN_ADDR 0x1594 146 #define MT6359P_RG_BUCK_VGPU11_HW12_OP_EN_ADDR 0x1594 147 #define MT6359P_RG_BUCK_VGPU11_HW13_OP_EN_ADDR 0x1594 148 #define MT6359P_RG_BUCK_VGPU11_HW14_OP_EN_ADDR 0x1594 149 #define MT6359P_RG_BUCK_VGPU11_SW_OP_EN_ADDR 0x1594 150 #define MT6359P_RG_BUCK_VGPU11_HW0_OP_CFG_ADDR 0x159a 151 #define MT6359P_RG_BUCK_VGPU11_HW1_OP_CFG_ADDR 0x159a 152 #define MT6359P_RG_BUCK_VGPU11_HW2_OP_CFG_ADDR 0x159a 153 #define MT6359P_RG_BUCK_VGPU11_HW3_OP_CFG_ADDR 0x159a 154 #define MT6359P_RG_BUCK_VGPU11_HW4_OP_CFG_ADDR 0x159a 155 #define MT6359P_RG_BUCK_VGPU11_HW5_OP_CFG_ADDR 0x159a 156 #define MT6359P_RG_BUCK_VGPU11_HW6_OP_CFG_ADDR 0x159a 157 #define MT6359P_RG_BUCK_VGPU11_HW7_OP_CFG_ADDR 0x159a 158 #define MT6359P_RG_BUCK_VGPU11_HW8_OP_CFG_ADDR 0x159a 159 #define MT6359P_RG_BUCK_VGPU11_HW9_OP_CFG_ADDR 0x159a 160 #define MT6359P_RG_BUCK_VGPU11_HW10_OP_CFG_ADDR 0x159a 161 #define MT6359P_RG_BUCK_VGPU11_HW11_OP_CFG_ADDR 0x159a 162 #define MT6359P_RG_BUCK_VGPU11_HW12_OP_CFG_ADDR 0x159a 163 #define MT6359P_RG_BUCK_VGPU11_HW13_OP_CFG_ADDR 0x159a 164 #define MT6359P_RG_BUCK_VGPU11_HW14_OP_CFG_ADDR 0x159a 165 #define MT6359P_RG_BUCK_VGPU11_HW0_OP_MODE_ADDR 0x15a0 166 #define MT6359P_RG_BUCK_VGPU11_HW0_OP_MODE_SHIFT 0 167 #define MT6359P_RG_BUCK_VGPU11_HW1_OP_MODE_ADDR 0x15a0 168 #define MT6359P_RG_BUCK_VGPU11_HW1_OP_MODE_SHIFT 1 169 #define MT6359P_RG_BUCK_VGPU11_HW2_OP_MODE_ADDR 0x15a0 170 #define MT6359P_RG_BUCK_VGPU11_HW2_OP_MODE_SHIFT 2 171 #define MT6359P_RG_BUCK_VGPU11_HW3_OP_MODE_ADDR 0x15a0 172 #define MT6359P_RG_BUCK_VGPU11_HW3_OP_MODE_SHIFT 3 173 #define MT6359P_RG_BUCK_VGPU11_HW4_OP_MODE_ADDR 0x15a0 174 #define MT6359P_RG_BUCK_VGPU11_HW4_OP_MODE_SHIFT 4 175 #define MT6359P_RG_BUCK_VGPU11_HW5_OP_MODE_ADDR 0x15a0 176 #define MT6359P_RG_BUCK_VGPU11_HW5_OP_MODE_SHIFT 5 177 #define MT6359P_RG_BUCK_VGPU11_HW6_OP_MODE_ADDR 0x15a0 178 #define MT6359P_RG_BUCK_VGPU11_HW6_OP_MODE_SHIFT 6 179 #define MT6359P_RG_BUCK_VGPU11_HW7_OP_MODE_ADDR 0x15a0 180 #define MT6359P_RG_BUCK_VGPU11_HW7_OP_MODE_SHIFT 7 181 #define MT6359P_RG_BUCK_VGPU11_HW8_OP_MODE_ADDR 0x15a0 182 #define MT6359P_RG_BUCK_VGPU11_HW8_OP_MODE_SHIFT 8 183 #define MT6359P_RG_BUCK_VGPU11_HW9_OP_MODE_ADDR 0x15a0 184 #define MT6359P_RG_BUCK_VGPU11_HW9_OP_MODE_SHIFT 9 185 #define MT6359P_RG_BUCK_VGPU11_HW10_OP_MODE_ADDR 0x15a0 186 #define MT6359P_RG_BUCK_VGPU11_HW10_OP_MODE_SHIFT 10 187 #define MT6359P_RG_BUCK_VGPU11_HW11_OP_MODE_ADDR 0x15a0 188 #define MT6359P_RG_BUCK_VGPU11_HW11_OP_MODE_SHIFT 11 189 #define MT6359P_RG_BUCK_VGPU11_HW12_OP_MODE_ADDR 0x15a0 190 #define MT6359P_RG_BUCK_VGPU11_HW12_OP_MODE_SHIFT 12 191 #define MT6359P_RG_BUCK_VGPU11_HW13_OP_MODE_ADDR 0x15a0 192 #define MT6359P_RG_BUCK_VGPU11_HW13_OP_MODE_SHIFT 13 193 #define MT6359P_RG_BUCK_VGPU11_HW14_OP_MODE_ADDR 0x15a0 194 #define MT6359P_RG_BUCK_VGPU11_HW14_OP_MODE_SHIFT 14 195 #define MT6359P_RG_BUCK_VGPU12_VOSEL_SLEEP_ADDR 0x160e 196 #define MT6359P_RG_BUCK_VGPU12_HW0_OP_EN_ADDR 0x1614 197 #define MT6359P_RG_BUCK_VGPU12_HW1_OP_EN_ADDR 0x1614 198 #define MT6359P_RG_BUCK_VGPU12_HW2_OP_EN_ADDR 0x1614 199 #define MT6359P_RG_BUCK_VGPU12_HW3_OP_EN_ADDR 0x1614 200 #define MT6359P_RG_BUCK_VGPU12_HW4_OP_EN_ADDR 0x1614 201 #define MT6359P_RG_BUCK_VGPU12_HW5_OP_EN_ADDR 0x1614 202 #define MT6359P_RG_BUCK_VGPU12_HW6_OP_EN_ADDR 0x1614 203 #define MT6359P_RG_BUCK_VGPU12_HW7_OP_EN_ADDR 0x1614 204 #define MT6359P_RG_BUCK_VGPU12_HW8_OP_EN_ADDR 0x1614 205 #define MT6359P_RG_BUCK_VGPU12_HW9_OP_EN_ADDR 0x1614 206 #define MT6359P_RG_BUCK_VGPU12_HW10_OP_EN_ADDR 0x1614 207 #define MT6359P_RG_BUCK_VGPU12_HW11_OP_EN_ADDR 0x1614 208 #define MT6359P_RG_BUCK_VGPU12_HW12_OP_EN_ADDR 0x1614 209 #define MT6359P_RG_BUCK_VGPU12_HW13_OP_EN_ADDR 0x1614 210 #define MT6359P_RG_BUCK_VGPU12_HW14_OP_EN_ADDR 0x1614 211 #define MT6359P_RG_BUCK_VGPU12_SW_OP_EN_ADDR 0x1614 212 #define MT6359P_RG_BUCK_VGPU12_HW0_OP_CFG_ADDR 0x161a 213 #define MT6359P_RG_BUCK_VGPU12_HW1_OP_CFG_ADDR 0x161a 214 #define MT6359P_RG_BUCK_VGPU12_HW2_OP_CFG_ADDR 0x161a 215 #define MT6359P_RG_BUCK_VGPU12_HW3_OP_CFG_ADDR 0x161a 216 #define MT6359P_RG_BUCK_VGPU12_HW4_OP_CFG_ADDR 0x161a 217 #define MT6359P_RG_BUCK_VGPU12_HW5_OP_CFG_ADDR 0x161a 218 #define MT6359P_RG_BUCK_VGPU12_HW6_OP_CFG_ADDR 0x161a 219 #define MT6359P_RG_BUCK_VGPU12_HW7_OP_CFG_ADDR 0x161a 220 #define MT6359P_RG_BUCK_VGPU12_HW8_OP_CFG_ADDR 0x161a 221 #define MT6359P_RG_BUCK_VGPU12_HW9_OP_CFG_ADDR 0x161a 222 #define MT6359P_RG_BUCK_VGPU12_HW10_OP_CFG_ADDR 0x161a 223 #define MT6359P_RG_BUCK_VGPU12_HW11_OP_CFG_ADDR 0x161a 224 #define MT6359P_RG_BUCK_VGPU12_HW12_OP_CFG_ADDR 0x161a 225 #define MT6359P_RG_BUCK_VGPU12_HW13_OP_CFG_ADDR 0x161a 226 #define MT6359P_RG_BUCK_VGPU12_HW14_OP_CFG_ADDR 0x161a 227 #define MT6359P_RG_BUCK_VGPU12_HW0_OP_MODE_ADDR 0x1620 228 #define MT6359P_RG_BUCK_VGPU12_HW0_OP_MODE_SHIFT 0 229 #define MT6359P_RG_BUCK_VGPU12_HW1_OP_MODE_ADDR 0x1620 230 #define MT6359P_RG_BUCK_VGPU12_HW1_OP_MODE_SHIFT 1 231 #define MT6359P_RG_BUCK_VGPU12_HW2_OP_MODE_ADDR 0x1620 232 #define MT6359P_RG_BUCK_VGPU12_HW2_OP_MODE_SHIFT 2 233 #define MT6359P_RG_BUCK_VGPU12_HW3_OP_MODE_ADDR 0x1620 234 #define MT6359P_RG_BUCK_VGPU12_HW3_OP_MODE_SHIFT 3 235 #define MT6359P_RG_BUCK_VGPU12_HW4_OP_MODE_ADDR 0x1620 236 #define MT6359P_RG_BUCK_VGPU12_HW4_OP_MODE_SHIFT 4 237 #define MT6359P_RG_BUCK_VGPU12_HW5_OP_MODE_ADDR 0x1620 238 #define MT6359P_RG_BUCK_VGPU12_HW5_OP_MODE_SHIFT 5 239 #define MT6359P_RG_BUCK_VGPU12_HW6_OP_MODE_ADDR 0x1620 240 #define MT6359P_RG_BUCK_VGPU12_HW6_OP_MODE_SHIFT 6 241 #define MT6359P_RG_BUCK_VGPU12_HW7_OP_MODE_ADDR 0x1620 242 #define MT6359P_RG_BUCK_VGPU12_HW7_OP_MODE_SHIFT 7 243 #define MT6359P_RG_BUCK_VGPU12_HW8_OP_MODE_ADDR 0x1620 244 #define MT6359P_RG_BUCK_VGPU12_HW8_OP_MODE_SHIFT 8 245 #define MT6359P_RG_BUCK_VGPU12_HW9_OP_MODE_ADDR 0x1620 246 #define MT6359P_RG_BUCK_VGPU12_HW9_OP_MODE_SHIFT 9 247 #define MT6359P_RG_BUCK_VGPU12_HW10_OP_MODE_ADDR 0x1620 248 #define MT6359P_RG_BUCK_VGPU12_HW10_OP_MODE_SHIFT 10 249 #define MT6359P_RG_BUCK_VGPU12_HW11_OP_MODE_ADDR 0x1620 250 #define MT6359P_RG_BUCK_VGPU12_HW11_OP_MODE_SHIFT 11 251 #define MT6359P_RG_BUCK_VGPU12_HW12_OP_MODE_ADDR 0x1620 252 #define MT6359P_RG_BUCK_VGPU12_HW12_OP_MODE_SHIFT 12 253 #define MT6359P_RG_BUCK_VGPU12_HW13_OP_MODE_ADDR 0x1620 254 #define MT6359P_RG_BUCK_VGPU12_HW13_OP_MODE_SHIFT 13 255 #define MT6359P_RG_BUCK_VGPU12_HW14_OP_MODE_ADDR 0x1620 256 #define MT6359P_RG_BUCK_VGPU12_HW14_OP_MODE_SHIFT 14 257 #define MT6359P_RG_BUCK_VMODEM_VOSEL_SLEEP_ADDR 0x168e 258 #define MT6359P_RG_BUCK_VMODEM_HW0_OP_EN_ADDR 0x1694 259 #define MT6359P_RG_BUCK_VMODEM_HW1_OP_EN_ADDR 0x1694 260 #define MT6359P_RG_BUCK_VMODEM_HW2_OP_EN_ADDR 0x1694 261 #define MT6359P_RG_BUCK_VMODEM_HW3_OP_EN_ADDR 0x1694 262 #define MT6359P_RG_BUCK_VMODEM_HW4_OP_EN_ADDR 0x1694 263 #define MT6359P_RG_BUCK_VMODEM_HW5_OP_EN_ADDR 0x1694 264 #define MT6359P_RG_BUCK_VMODEM_HW6_OP_EN_ADDR 0x1694 265 #define MT6359P_RG_BUCK_VMODEM_HW7_OP_EN_ADDR 0x1694 266 #define MT6359P_RG_BUCK_VMODEM_HW8_OP_EN_ADDR 0x1694 267 #define MT6359P_RG_BUCK_VMODEM_HW9_OP_EN_ADDR 0x1694 268 #define MT6359P_RG_BUCK_VMODEM_HW10_OP_EN_ADDR 0x1694 269 #define MT6359P_RG_BUCK_VMODEM_HW11_OP_EN_ADDR 0x1694 270 #define MT6359P_RG_BUCK_VMODEM_HW12_OP_EN_ADDR 0x1694 271 #define MT6359P_RG_BUCK_VMODEM_HW13_OP_EN_ADDR 0x1694 272 #define MT6359P_RG_BUCK_VMODEM_HW14_OP_EN_ADDR 0x1694 273 #define MT6359P_RG_BUCK_VMODEM_SW_OP_EN_ADDR 0x1694 274 #define MT6359P_RG_BUCK_VMODEM_HW0_OP_CFG_ADDR 0x169a 275 #define MT6359P_RG_BUCK_VMODEM_HW1_OP_CFG_ADDR 0x169a 276 #define MT6359P_RG_BUCK_VMODEM_HW2_OP_CFG_ADDR 0x169a 277 #define MT6359P_RG_BUCK_VMODEM_HW3_OP_CFG_ADDR 0x169a 278 #define MT6359P_RG_BUCK_VMODEM_HW4_OP_CFG_ADDR 0x169a 279 #define MT6359P_RG_BUCK_VMODEM_HW5_OP_CFG_ADDR 0x169a 280 #define MT6359P_RG_BUCK_VMODEM_HW6_OP_CFG_ADDR 0x169a 281 #define MT6359P_RG_BUCK_VMODEM_HW7_OP_CFG_ADDR 0x169a 282 #define MT6359P_RG_BUCK_VMODEM_HW8_OP_CFG_ADDR 0x169a 283 #define MT6359P_RG_BUCK_VMODEM_HW9_OP_CFG_ADDR 0x169a 284 #define MT6359P_RG_BUCK_VMODEM_HW10_OP_CFG_ADDR 0x169a 285 #define MT6359P_RG_BUCK_VMODEM_HW11_OP_CFG_ADDR 0x169a 286 #define MT6359P_RG_BUCK_VMODEM_HW12_OP_CFG_ADDR 0x169a 287 #define MT6359P_RG_BUCK_VMODEM_HW13_OP_CFG_ADDR 0x169a 288 #define MT6359P_RG_BUCK_VMODEM_HW14_OP_CFG_ADDR 0x169a 289 #define MT6359P_RG_BUCK_VMODEM_HW0_OP_MODE_ADDR 0x16a0 290 #define MT6359P_RG_BUCK_VMODEM_HW0_OP_MODE_SHIFT 0 291 #define MT6359P_RG_BUCK_VMODEM_HW1_OP_MODE_ADDR 0x16a0 292 #define MT6359P_RG_BUCK_VMODEM_HW1_OP_MODE_SHIFT 1 293 #define MT6359P_RG_BUCK_VMODEM_HW2_OP_MODE_ADDR 0x16a0 294 #define MT6359P_RG_BUCK_VMODEM_HW2_OP_MODE_SHIFT 2 295 #define MT6359P_RG_BUCK_VMODEM_HW3_OP_MODE_ADDR 0x16a0 296 #define MT6359P_RG_BUCK_VMODEM_HW3_OP_MODE_SHIFT 3 297 #define MT6359P_RG_BUCK_VMODEM_HW4_OP_MODE_ADDR 0x16a0 298 #define MT6359P_RG_BUCK_VMODEM_HW4_OP_MODE_SHIFT 4 299 #define MT6359P_RG_BUCK_VMODEM_HW5_OP_MODE_ADDR 0x16a0 300 #define MT6359P_RG_BUCK_VMODEM_HW5_OP_MODE_SHIFT 5 301 #define MT6359P_RG_BUCK_VMODEM_HW6_OP_MODE_ADDR 0x16a0 302 #define MT6359P_RG_BUCK_VMODEM_HW6_OP_MODE_SHIFT 6 303 #define MT6359P_RG_BUCK_VMODEM_HW7_OP_MODE_ADDR 0x16a0 304 #define MT6359P_RG_BUCK_VMODEM_HW7_OP_MODE_SHIFT 7 305 #define MT6359P_RG_BUCK_VMODEM_HW8_OP_MODE_ADDR 0x16a0 306 #define MT6359P_RG_BUCK_VMODEM_HW8_OP_MODE_SHIFT 8 307 #define MT6359P_RG_BUCK_VMODEM_HW9_OP_MODE_ADDR 0x16a0 308 #define MT6359P_RG_BUCK_VMODEM_HW9_OP_MODE_SHIFT 9 309 #define MT6359P_RG_BUCK_VMODEM_HW10_OP_MODE_ADDR 0x16a0 310 #define MT6359P_RG_BUCK_VMODEM_HW10_OP_MODE_SHIFT 10 311 #define MT6359P_RG_BUCK_VMODEM_HW11_OP_MODE_ADDR 0x16a0 312 #define MT6359P_RG_BUCK_VMODEM_HW11_OP_MODE_SHIFT 11 313 #define MT6359P_RG_BUCK_VMODEM_HW12_OP_MODE_ADDR 0x16a0 314 #define MT6359P_RG_BUCK_VMODEM_HW12_OP_MODE_SHIFT 12 315 #define MT6359P_RG_BUCK_VMODEM_HW13_OP_MODE_ADDR 0x16a0 316 #define MT6359P_RG_BUCK_VMODEM_HW13_OP_MODE_SHIFT 13 317 #define MT6359P_RG_BUCK_VMODEM_HW14_OP_MODE_ADDR 0x16a0 318 #define MT6359P_RG_BUCK_VMODEM_HW14_OP_MODE_SHIFT 14 319 #define MT6359P_RG_BUCK_VPROC1_VOSEL_SLEEP_ADDR 0x170e 320 #define MT6359P_RG_BUCK_VPROC1_HW0_OP_EN_ADDR 0x1714 321 #define MT6359P_RG_BUCK_VPROC1_HW1_OP_EN_ADDR 0x1714 322 #define MT6359P_RG_BUCK_VPROC1_HW2_OP_EN_ADDR 0x1714 323 #define MT6359P_RG_BUCK_VPROC1_HW3_OP_EN_ADDR 0x1714 324 #define MT6359P_RG_BUCK_VPROC1_HW4_OP_EN_ADDR 0x1714 325 #define MT6359P_RG_BUCK_VPROC1_HW5_OP_EN_ADDR 0x1714 326 #define MT6359P_RG_BUCK_VPROC1_HW6_OP_EN_ADDR 0x1714 327 #define MT6359P_RG_BUCK_VPROC1_HW7_OP_EN_ADDR 0x1714 328 #define MT6359P_RG_BUCK_VPROC1_HW8_OP_EN_ADDR 0x1714 329 #define MT6359P_RG_BUCK_VPROC1_HW9_OP_EN_ADDR 0x1714 330 #define MT6359P_RG_BUCK_VPROC1_HW10_OP_EN_ADDR 0x1714 331 #define MT6359P_RG_BUCK_VPROC1_HW11_OP_EN_ADDR 0x1714 332 #define MT6359P_RG_BUCK_VPROC1_HW12_OP_EN_ADDR 0x1714 333 #define MT6359P_RG_BUCK_VPROC1_HW13_OP_EN_ADDR 0x1714 334 #define MT6359P_RG_BUCK_VPROC1_HW14_OP_EN_ADDR 0x1714 335 #define MT6359P_RG_BUCK_VPROC1_SW_OP_EN_ADDR 0x1714 336 #define MT6359P_RG_BUCK_VPROC1_HW0_OP_CFG_ADDR 0x171a 337 #define MT6359P_RG_BUCK_VPROC1_HW1_OP_CFG_ADDR 0x171a 338 #define MT6359P_RG_BUCK_VPROC1_HW2_OP_CFG_ADDR 0x171a 339 #define MT6359P_RG_BUCK_VPROC1_HW3_OP_CFG_ADDR 0x171a 340 #define MT6359P_RG_BUCK_VPROC1_HW4_OP_CFG_ADDR 0x171a 341 #define MT6359P_RG_BUCK_VPROC1_HW5_OP_CFG_ADDR 0x171a 342 #define MT6359P_RG_BUCK_VPROC1_HW6_OP_CFG_ADDR 0x171a 343 #define MT6359P_RG_BUCK_VPROC1_HW7_OP_CFG_ADDR 0x171a 344 #define MT6359P_RG_BUCK_VPROC1_HW8_OP_CFG_ADDR 0x171a 345 #define MT6359P_RG_BUCK_VPROC1_HW9_OP_CFG_ADDR 0x171a 346 #define MT6359P_RG_BUCK_VPROC1_HW10_OP_CFG_ADDR 0x171a 347 #define MT6359P_RG_BUCK_VPROC1_HW11_OP_CFG_ADDR 0x171a 348 #define MT6359P_RG_BUCK_VPROC1_HW12_OP_CFG_ADDR 0x171a 349 #define MT6359P_RG_BUCK_VPROC1_HW13_OP_CFG_ADDR 0x171a 350 #define MT6359P_RG_BUCK_VPROC1_HW14_OP_CFG_ADDR 0x171a 351 #define MT6359P_RG_BUCK_VPROC1_HW0_OP_MODE_ADDR 0x1720 352 #define MT6359P_RG_BUCK_VPROC1_HW0_OP_MODE_SHIFT 0 353 #define MT6359P_RG_BUCK_VPROC1_HW1_OP_MODE_ADDR 0x1720 354 #define MT6359P_RG_BUCK_VPROC1_HW1_OP_MODE_SHIFT 1 355 #define MT6359P_RG_BUCK_VPROC1_HW2_OP_MODE_ADDR 0x1720 356 #define MT6359P_RG_BUCK_VPROC1_HW2_OP_MODE_SHIFT 2 357 #define MT6359P_RG_BUCK_VPROC1_HW3_OP_MODE_ADDR 0x1720 358 #define MT6359P_RG_BUCK_VPROC1_HW3_OP_MODE_SHIFT 3 359 #define MT6359P_RG_BUCK_VPROC1_HW4_OP_MODE_ADDR 0x1720 360 #define MT6359P_RG_BUCK_VPROC1_HW4_OP_MODE_SHIFT 4 361 #define MT6359P_RG_BUCK_VPROC1_HW5_OP_MODE_ADDR 0x1720 362 #define MT6359P_RG_BUCK_VPROC1_HW5_OP_MODE_SHIFT 5 363 #define MT6359P_RG_BUCK_VPROC1_HW6_OP_MODE_ADDR 0x1720 364 #define MT6359P_RG_BUCK_VPROC1_HW6_OP_MODE_SHIFT 6 365 #define MT6359P_RG_BUCK_VPROC1_HW7_OP_MODE_ADDR 0x1720 366 #define MT6359P_RG_BUCK_VPROC1_HW7_OP_MODE_SHIFT 7 367 #define MT6359P_RG_BUCK_VPROC1_HW8_OP_MODE_ADDR 0x1720 368 #define MT6359P_RG_BUCK_VPROC1_HW8_OP_MODE_SHIFT 8 369 #define MT6359P_RG_BUCK_VPROC1_HW9_OP_MODE_ADDR 0x1720 370 #define MT6359P_RG_BUCK_VPROC1_HW9_OP_MODE_SHIFT 9 371 #define MT6359P_RG_BUCK_VPROC1_HW10_OP_MODE_ADDR 0x1720 372 #define MT6359P_RG_BUCK_VPROC1_HW10_OP_MODE_SHIFT 10 373 #define MT6359P_RG_BUCK_VPROC1_HW11_OP_MODE_ADDR 0x1720 374 #define MT6359P_RG_BUCK_VPROC1_HW11_OP_MODE_SHIFT 11 375 #define MT6359P_RG_BUCK_VPROC1_HW12_OP_MODE_ADDR 0x1720 376 #define MT6359P_RG_BUCK_VPROC1_HW12_OP_MODE_SHIFT 12 377 #define MT6359P_RG_BUCK_VPROC1_HW13_OP_MODE_ADDR 0x1720 378 #define MT6359P_RG_BUCK_VPROC1_HW13_OP_MODE_SHIFT 13 379 #define MT6359P_RG_BUCK_VPROC1_HW14_OP_MODE_ADDR 0x1720 380 #define MT6359P_RG_BUCK_VPROC1_HW14_OP_MODE_SHIFT 14 381 #define MT6359P_RG_BUCK_VPROC2_VOSEL_SLEEP_ADDR 0x178e 382 #define MT6359P_RG_BUCK_VPROC2_HW0_OP_EN_ADDR 0x1794 383 #define MT6359P_RG_BUCK_VPROC2_HW1_OP_EN_ADDR 0x1794 384 #define MT6359P_RG_BUCK_VPROC2_HW2_OP_EN_ADDR 0x1794 385 #define MT6359P_RG_BUCK_VPROC2_HW3_OP_EN_ADDR 0x1794 386 #define MT6359P_RG_BUCK_VPROC2_HW4_OP_EN_ADDR 0x1794 387 #define MT6359P_RG_BUCK_VPROC2_HW5_OP_EN_ADDR 0x1794 388 #define MT6359P_RG_BUCK_VPROC2_HW6_OP_EN_ADDR 0x1794 389 #define MT6359P_RG_BUCK_VPROC2_HW7_OP_EN_ADDR 0x1794 390 #define MT6359P_RG_BUCK_VPROC2_HW8_OP_EN_ADDR 0x1794 391 #define MT6359P_RG_BUCK_VPROC2_HW9_OP_EN_ADDR 0x1794 392 #define MT6359P_RG_BUCK_VPROC2_HW10_OP_EN_ADDR 0x1794 393 #define MT6359P_RG_BUCK_VPROC2_HW11_OP_EN_ADDR 0x1794 394 #define MT6359P_RG_BUCK_VPROC2_HW12_OP_EN_ADDR 0x1794 395 #define MT6359P_RG_BUCK_VPROC2_HW13_OP_EN_ADDR 0x1794 396 #define MT6359P_RG_BUCK_VPROC2_HW14_OP_EN_ADDR 0x1794 397 #define MT6359P_RG_BUCK_VPROC2_SW_OP_EN_ADDR 0x1794 398 #define MT6359P_RG_BUCK_VPROC2_HW0_OP_CFG_ADDR 0x179a 399 #define MT6359P_RG_BUCK_VPROC2_HW1_OP_CFG_ADDR 0x179a 400 #define MT6359P_RG_BUCK_VPROC2_HW2_OP_CFG_ADDR 0x179a 401 #define MT6359P_RG_BUCK_VPROC2_HW3_OP_CFG_ADDR 0x179a 402 #define MT6359P_RG_BUCK_VPROC2_HW4_OP_CFG_ADDR 0x179a 403 #define MT6359P_RG_BUCK_VPROC2_HW5_OP_CFG_ADDR 0x179a 404 #define MT6359P_RG_BUCK_VPROC2_HW6_OP_CFG_ADDR 0x179a 405 #define MT6359P_RG_BUCK_VPROC2_HW7_OP_CFG_ADDR 0x179a 406 #define MT6359P_RG_BUCK_VPROC2_HW8_OP_CFG_ADDR 0x179a 407 #define MT6359P_RG_BUCK_VPROC2_HW9_OP_CFG_ADDR 0x179a 408 #define MT6359P_RG_BUCK_VPROC2_HW10_OP_CFG_ADDR 0x179a 409 #define MT6359P_RG_BUCK_VPROC2_HW11_OP_CFG_ADDR 0x179a 410 #define MT6359P_RG_BUCK_VPROC2_HW12_OP_CFG_ADDR 0x179a 411 #define MT6359P_RG_BUCK_VPROC2_HW13_OP_CFG_ADDR 0x179a 412 #define MT6359P_RG_BUCK_VPROC2_HW14_OP_CFG_ADDR 0x179a 413 #define MT6359P_RG_BUCK_VPROC2_HW0_OP_MODE_ADDR 0x17a0 414 #define MT6359P_RG_BUCK_VPROC2_HW0_OP_MODE_SHIFT 0 415 #define MT6359P_RG_BUCK_VPROC2_HW1_OP_MODE_ADDR 0x17a0 416 #define MT6359P_RG_BUCK_VPROC2_HW1_OP_MODE_SHIFT 1 417 #define MT6359P_RG_BUCK_VPROC2_HW2_OP_MODE_ADDR 0x17a0 418 #define MT6359P_RG_BUCK_VPROC2_HW2_OP_MODE_SHIFT 2 419 #define MT6359P_RG_BUCK_VPROC2_HW3_OP_MODE_ADDR 0x17a0 420 #define MT6359P_RG_BUCK_VPROC2_HW3_OP_MODE_SHIFT 3 421 #define MT6359P_RG_BUCK_VPROC2_HW4_OP_MODE_ADDR 0x17a0 422 #define MT6359P_RG_BUCK_VPROC2_HW4_OP_MODE_SHIFT 4 423 #define MT6359P_RG_BUCK_VPROC2_HW5_OP_MODE_ADDR 0x17a0 424 #define MT6359P_RG_BUCK_VPROC2_HW5_OP_MODE_SHIFT 5 425 #define MT6359P_RG_BUCK_VPROC2_HW6_OP_MODE_ADDR 0x17a0 426 #define MT6359P_RG_BUCK_VPROC2_HW6_OP_MODE_SHIFT 6 427 #define MT6359P_RG_BUCK_VPROC2_HW7_OP_MODE_ADDR 0x17a0 428 #define MT6359P_RG_BUCK_VPROC2_HW7_OP_MODE_SHIFT 7 429 #define MT6359P_RG_BUCK_VPROC2_HW8_OP_MODE_ADDR 0x17a0 430 #define MT6359P_RG_BUCK_VPROC2_HW8_OP_MODE_SHIFT 8 431 #define MT6359P_RG_BUCK_VPROC2_HW9_OP_MODE_ADDR 0x17a0 432 #define MT6359P_RG_BUCK_VPROC2_HW9_OP_MODE_SHIFT 9 433 #define MT6359P_RG_BUCK_VPROC2_HW10_OP_MODE_ADDR 0x17a0 434 #define MT6359P_RG_BUCK_VPROC2_HW10_OP_MODE_SHIFT 10 435 #define MT6359P_RG_BUCK_VPROC2_HW11_OP_MODE_ADDR 0x17a0 436 #define MT6359P_RG_BUCK_VPROC2_HW11_OP_MODE_SHIFT 11 437 #define MT6359P_RG_BUCK_VPROC2_HW12_OP_MODE_ADDR 0x17a0 438 #define MT6359P_RG_BUCK_VPROC2_HW12_OP_MODE_SHIFT 12 439 #define MT6359P_RG_BUCK_VPROC2_HW13_OP_MODE_ADDR 0x17a0 440 #define MT6359P_RG_BUCK_VPROC2_HW13_OP_MODE_SHIFT 13 441 #define MT6359P_RG_BUCK_VPROC2_HW14_OP_MODE_ADDR 0x17a0 442 #define MT6359P_RG_BUCK_VPROC2_HW14_OP_MODE_SHIFT 14 443 #define MT6359P_RG_BUCK_VS1_VOSEL_SLEEP_ADDR 0x180e 444 #define MT6359P_RG_BUCK_VS1_HW0_OP_EN_ADDR 0x1814 445 #define MT6359P_RG_BUCK_VS1_HW1_OP_EN_ADDR 0x1814 446 #define MT6359P_RG_BUCK_VS1_HW2_OP_EN_ADDR 0x1814 447 #define MT6359P_RG_BUCK_VS1_HW3_OP_EN_ADDR 0x1814 448 #define MT6359P_RG_BUCK_VS1_HW4_OP_EN_ADDR 0x1814 449 #define MT6359P_RG_BUCK_VS1_HW5_OP_EN_ADDR 0x1814 450 #define MT6359P_RG_BUCK_VS1_HW6_OP_EN_ADDR 0x1814 451 #define MT6359P_RG_BUCK_VS1_HW7_OP_EN_ADDR 0x1814 452 #define MT6359P_RG_BUCK_VS1_HW8_OP_EN_ADDR 0x1814 453 #define MT6359P_RG_BUCK_VS1_HW9_OP_EN_ADDR 0x1814 454 #define MT6359P_RG_BUCK_VS1_HW10_OP_EN_ADDR 0x1814 455 #define MT6359P_RG_BUCK_VS1_HW11_OP_EN_ADDR 0x1814 456 #define MT6359P_RG_BUCK_VS1_HW12_OP_EN_ADDR 0x1814 457 #define MT6359P_RG_BUCK_VS1_HW13_OP_EN_ADDR 0x1814 458 #define MT6359P_RG_BUCK_VS1_HW14_OP_EN_ADDR 0x1814 459 #define MT6359P_RG_BUCK_VS1_SW_OP_EN_ADDR 0x1814 460 #define MT6359P_RG_BUCK_VS1_HW0_OP_CFG_ADDR 0x181a 461 #define MT6359P_RG_BUCK_VS1_HW1_OP_CFG_ADDR 0x181a 462 #define MT6359P_RG_BUCK_VS1_HW2_OP_CFG_ADDR 0x181a 463 #define MT6359P_RG_BUCK_VS1_HW3_OP_CFG_ADDR 0x181a 464 #define MT6359P_RG_BUCK_VS1_HW4_OP_CFG_ADDR 0x181a 465 #define MT6359P_RG_BUCK_VS1_HW5_OP_CFG_ADDR 0x181a 466 #define MT6359P_RG_BUCK_VS1_HW6_OP_CFG_ADDR 0x181a 467 #define MT6359P_RG_BUCK_VS1_HW7_OP_CFG_ADDR 0x181a 468 #define MT6359P_RG_BUCK_VS1_HW8_OP_CFG_ADDR 0x181a 469 #define MT6359P_RG_BUCK_VS1_HW9_OP_CFG_ADDR 0x181a 470 #define MT6359P_RG_BUCK_VS1_HW10_OP_CFG_ADDR 0x181a 471 #define MT6359P_RG_BUCK_VS1_HW11_OP_CFG_ADDR 0x181a 472 #define MT6359P_RG_BUCK_VS1_HW12_OP_CFG_ADDR 0x181a 473 #define MT6359P_RG_BUCK_VS1_HW13_OP_CFG_ADDR 0x181a 474 #define MT6359P_RG_BUCK_VS1_HW14_OP_CFG_ADDR 0x181a 475 #define MT6359P_RG_BUCK_VS1_HW0_OP_MODE_ADDR 0x1820 476 #define MT6359P_RG_BUCK_VS1_HW0_OP_MODE_SHIFT 0 477 #define MT6359P_RG_BUCK_VS1_HW1_OP_MODE_ADDR 0x1820 478 #define MT6359P_RG_BUCK_VS1_HW1_OP_MODE_SHIFT 1 479 #define MT6359P_RG_BUCK_VS1_HW2_OP_MODE_ADDR 0x1820 480 #define MT6359P_RG_BUCK_VS1_HW2_OP_MODE_SHIFT 2 481 #define MT6359P_RG_BUCK_VS1_HW3_OP_MODE_ADDR 0x1820 482 #define MT6359P_RG_BUCK_VS1_HW3_OP_MODE_SHIFT 3 483 #define MT6359P_RG_BUCK_VS1_HW4_OP_MODE_ADDR 0x1820 484 #define MT6359P_RG_BUCK_VS1_HW4_OP_MODE_SHIFT 4 485 #define MT6359P_RG_BUCK_VS1_HW5_OP_MODE_ADDR 0x1820 486 #define MT6359P_RG_BUCK_VS1_HW5_OP_MODE_SHIFT 5 487 #define MT6359P_RG_BUCK_VS1_HW6_OP_MODE_ADDR 0x1820 488 #define MT6359P_RG_BUCK_VS1_HW6_OP_MODE_SHIFT 6 489 #define MT6359P_RG_BUCK_VS1_HW7_OP_MODE_ADDR 0x1820 490 #define MT6359P_RG_BUCK_VS1_HW7_OP_MODE_SHIFT 7 491 #define MT6359P_RG_BUCK_VS1_HW8_OP_MODE_ADDR 0x1820 492 #define MT6359P_RG_BUCK_VS1_HW8_OP_MODE_SHIFT 8 493 #define MT6359P_RG_BUCK_VS1_HW9_OP_MODE_ADDR 0x1820 494 #define MT6359P_RG_BUCK_VS1_HW9_OP_MODE_SHIFT 9 495 #define MT6359P_RG_BUCK_VS1_HW10_OP_MODE_ADDR 0x1820 496 #define MT6359P_RG_BUCK_VS1_HW10_OP_MODE_SHIFT 10 497 #define MT6359P_RG_BUCK_VS1_HW11_OP_MODE_ADDR 0x1820 498 #define MT6359P_RG_BUCK_VS1_HW11_OP_MODE_SHIFT 11 499 #define MT6359P_RG_BUCK_VS1_HW12_OP_MODE_ADDR 0x1820 500 #define MT6359P_RG_BUCK_VS1_HW12_OP_MODE_SHIFT 12 501 #define MT6359P_RG_BUCK_VS1_HW13_OP_MODE_ADDR 0x1820 502 #define MT6359P_RG_BUCK_VS1_HW13_OP_MODE_SHIFT 13 503 #define MT6359P_RG_BUCK_VS1_HW14_OP_MODE_ADDR 0x1820 504 #define MT6359P_RG_BUCK_VS1_HW14_OP_MODE_SHIFT 14 505 #define MT6359P_RG_BUCK_VS2_VOSEL_SLEEP_ADDR 0x188e 506 #define MT6359P_RG_BUCK_VS2_HW0_OP_EN_ADDR 0x1894 507 #define MT6359P_RG_BUCK_VS2_HW1_OP_EN_ADDR 0x1894 508 #define MT6359P_RG_BUCK_VS2_HW2_OP_EN_ADDR 0x1894 509 #define MT6359P_RG_BUCK_VS2_HW3_OP_EN_ADDR 0x1894 510 #define MT6359P_RG_BUCK_VS2_HW4_OP_EN_ADDR 0x1894 511 #define MT6359P_RG_BUCK_VS2_HW5_OP_EN_ADDR 0x1894 512 #define MT6359P_RG_BUCK_VS2_HW6_OP_EN_ADDR 0x1894 513 #define MT6359P_RG_BUCK_VS2_HW7_OP_EN_ADDR 0x1894 514 #define MT6359P_RG_BUCK_VS2_HW8_OP_EN_ADDR 0x1894 515 #define MT6359P_RG_BUCK_VS2_HW9_OP_EN_ADDR 0x1894 516 #define MT6359P_RG_BUCK_VS2_HW10_OP_EN_ADDR 0x1894 517 #define MT6359P_RG_BUCK_VS2_HW11_OP_EN_ADDR 0x1894 518 #define MT6359P_RG_BUCK_VS2_HW12_OP_EN_ADDR 0x1894 519 #define MT6359P_RG_BUCK_VS2_HW13_OP_EN_ADDR 0x1894 520 #define MT6359P_RG_BUCK_VS2_HW14_OP_EN_ADDR 0x1894 521 #define MT6359P_RG_BUCK_VS2_SW_OP_EN_ADDR 0x1894 522 #define MT6359P_RG_BUCK_VS2_HW0_OP_CFG_ADDR 0x189a 523 #define MT6359P_RG_BUCK_VS2_HW1_OP_CFG_ADDR 0x189a 524 #define MT6359P_RG_BUCK_VS2_HW2_OP_CFG_ADDR 0x189a 525 #define MT6359P_RG_BUCK_VS2_HW3_OP_CFG_ADDR 0x189a 526 #define MT6359P_RG_BUCK_VS2_HW4_OP_CFG_ADDR 0x189a 527 #define MT6359P_RG_BUCK_VS2_HW5_OP_CFG_ADDR 0x189a 528 #define MT6359P_RG_BUCK_VS2_HW6_OP_CFG_ADDR 0x189a 529 #define MT6359P_RG_BUCK_VS2_HW7_OP_CFG_ADDR 0x189a 530 #define MT6359P_RG_BUCK_VS2_HW8_OP_CFG_ADDR 0x189a 531 #define MT6359P_RG_BUCK_VS2_HW9_OP_CFG_ADDR 0x189a 532 #define MT6359P_RG_BUCK_VS2_HW10_OP_CFG_ADDR 0x189a 533 #define MT6359P_RG_BUCK_VS2_HW11_OP_CFG_ADDR 0x189a 534 #define MT6359P_RG_BUCK_VS2_HW12_OP_CFG_ADDR 0x189a 535 #define MT6359P_RG_BUCK_VS2_HW13_OP_CFG_ADDR 0x189a 536 #define MT6359P_RG_BUCK_VS2_HW14_OP_CFG_ADDR 0x189a 537 #define MT6359P_RG_BUCK_VS2_HW0_OP_MODE_ADDR 0x18a0 538 #define MT6359P_RG_BUCK_VS2_HW0_OP_MODE_SHIFT 0 539 #define MT6359P_RG_BUCK_VS2_HW1_OP_MODE_ADDR 0x18a0 540 #define MT6359P_RG_BUCK_VS2_HW1_OP_MODE_SHIFT 1 541 #define MT6359P_RG_BUCK_VS2_HW2_OP_MODE_ADDR 0x18a0 542 #define MT6359P_RG_BUCK_VS2_HW2_OP_MODE_SHIFT 2 543 #define MT6359P_RG_BUCK_VS2_HW3_OP_MODE_ADDR 0x18a0 544 #define MT6359P_RG_BUCK_VS2_HW3_OP_MODE_SHIFT 3 545 #define MT6359P_RG_BUCK_VS2_HW4_OP_MODE_ADDR 0x18a0 546 #define MT6359P_RG_BUCK_VS2_HW4_OP_MODE_SHIFT 4 547 #define MT6359P_RG_BUCK_VS2_HW5_OP_MODE_ADDR 0x18a0 548 #define MT6359P_RG_BUCK_VS2_HW5_OP_MODE_SHIFT 5 549 #define MT6359P_RG_BUCK_VS2_HW6_OP_MODE_ADDR 0x18a0 550 #define MT6359P_RG_BUCK_VS2_HW6_OP_MODE_SHIFT 6 551 #define MT6359P_RG_BUCK_VS2_HW7_OP_MODE_ADDR 0x18a0 552 #define MT6359P_RG_BUCK_VS2_HW7_OP_MODE_SHIFT 7 553 #define MT6359P_RG_BUCK_VS2_HW8_OP_MODE_ADDR 0x18a0 554 #define MT6359P_RG_BUCK_VS2_HW8_OP_MODE_SHIFT 8 555 #define MT6359P_RG_BUCK_VS2_HW9_OP_MODE_ADDR 0x18a0 556 #define MT6359P_RG_BUCK_VS2_HW9_OP_MODE_SHIFT 9 557 #define MT6359P_RG_BUCK_VS2_HW10_OP_MODE_ADDR 0x18a0 558 #define MT6359P_RG_BUCK_VS2_HW10_OP_MODE_SHIFT 10 559 #define MT6359P_RG_BUCK_VS2_HW11_OP_MODE_ADDR 0x18a0 560 #define MT6359P_RG_BUCK_VS2_HW11_OP_MODE_SHIFT 11 561 #define MT6359P_RG_BUCK_VS2_HW12_OP_MODE_ADDR 0x18a0 562 #define MT6359P_RG_BUCK_VS2_HW12_OP_MODE_SHIFT 12 563 #define MT6359P_RG_BUCK_VS2_HW13_OP_MODE_ADDR 0x18a0 564 #define MT6359P_RG_BUCK_VS2_HW13_OP_MODE_SHIFT 13 565 #define MT6359P_RG_BUCK_VS2_HW14_OP_MODE_ADDR 0x18a0 566 #define MT6359P_RG_BUCK_VS2_HW14_OP_MODE_SHIFT 14 567 #define MT6359P_RG_LDO_VFE28_OP_MODE_ADDR 0x1b8a 568 #define MT6359P_RG_LDO_VFE28_OP_MODE_SHIFT 10 569 #define MT6359P_RG_LDO_VFE28_HW0_OP_EN_ADDR 0x1b8e 570 #define MT6359P_RG_LDO_VFE28_HW1_OP_EN_ADDR 0x1b8e 571 #define MT6359P_RG_LDO_VFE28_HW2_OP_EN_ADDR 0x1b8e 572 #define MT6359P_RG_LDO_VFE28_HW3_OP_EN_ADDR 0x1b8e 573 #define MT6359P_RG_LDO_VFE28_HW4_OP_EN_ADDR 0x1b8e 574 #define MT6359P_RG_LDO_VFE28_HW5_OP_EN_ADDR 0x1b8e 575 #define MT6359P_RG_LDO_VFE28_HW6_OP_EN_ADDR 0x1b8e 576 #define MT6359P_RG_LDO_VFE28_HW7_OP_EN_ADDR 0x1b8e 577 #define MT6359P_RG_LDO_VFE28_HW8_OP_EN_ADDR 0x1b8e 578 #define MT6359P_RG_LDO_VFE28_HW9_OP_EN_ADDR 0x1b8e 579 #define MT6359P_RG_LDO_VFE28_HW10_OP_EN_ADDR 0x1b8e 580 #define MT6359P_RG_LDO_VFE28_HW11_OP_EN_ADDR 0x1b8e 581 #define MT6359P_RG_LDO_VFE28_HW12_OP_EN_ADDR 0x1b8e 582 #define MT6359P_RG_LDO_VFE28_HW13_OP_EN_ADDR 0x1b8e 583 #define MT6359P_RG_LDO_VFE28_HW14_OP_EN_ADDR 0x1b8e 584 #define MT6359P_RG_LDO_VFE28_SW_OP_EN_ADDR 0x1b8e 585 #define MT6359P_RG_LDO_VFE28_HW0_OP_CFG_ADDR 0x1b94 586 #define MT6359P_RG_LDO_VFE28_HW1_OP_CFG_ADDR 0x1b94 587 #define MT6359P_RG_LDO_VFE28_HW2_OP_CFG_ADDR 0x1b94 588 #define MT6359P_RG_LDO_VFE28_HW3_OP_CFG_ADDR 0x1b94 589 #define MT6359P_RG_LDO_VFE28_HW4_OP_CFG_ADDR 0x1b94 590 #define MT6359P_RG_LDO_VFE28_HW5_OP_CFG_ADDR 0x1b94 591 #define MT6359P_RG_LDO_VFE28_HW6_OP_CFG_ADDR 0x1b94 592 #define MT6359P_RG_LDO_VFE28_HW7_OP_CFG_ADDR 0x1b94 593 #define MT6359P_RG_LDO_VFE28_HW8_OP_CFG_ADDR 0x1b94 594 #define MT6359P_RG_LDO_VFE28_HW9_OP_CFG_ADDR 0x1b94 595 #define MT6359P_RG_LDO_VFE28_HW10_OP_CFG_ADDR 0x1b94 596 #define MT6359P_RG_LDO_VFE28_HW11_OP_CFG_ADDR 0x1b94 597 #define MT6359P_RG_LDO_VFE28_HW12_OP_CFG_ADDR 0x1b94 598 #define MT6359P_RG_LDO_VFE28_HW13_OP_CFG_ADDR 0x1b94 599 #define MT6359P_RG_LDO_VFE28_HW14_OP_CFG_ADDR 0x1b94 600 #define MT6359P_RG_LDO_VFE28_SW_OP_CFG_ADDR 0x1b94 601 #define MT6359P_RG_LDO_VXO22_OP_MODE_ADDR 0x1b9c 602 #define MT6359P_RG_LDO_VXO22_OP_MODE_SHIFT 10 603 #define MT6359P_RG_LDO_VXO22_HW0_OP_EN_ADDR 0x1ba0 604 #define MT6359P_RG_LDO_VXO22_HW1_OP_EN_ADDR 0x1ba0 605 #define MT6359P_RG_LDO_VXO22_HW2_OP_EN_ADDR 0x1ba0 606 #define MT6359P_RG_LDO_VXO22_HW3_OP_EN_ADDR 0x1ba0 607 #define MT6359P_RG_LDO_VXO22_HW4_OP_EN_ADDR 0x1ba0 608 #define MT6359P_RG_LDO_VXO22_HW5_OP_EN_ADDR 0x1ba0 609 #define MT6359P_RG_LDO_VXO22_HW6_OP_EN_ADDR 0x1ba0 610 #define MT6359P_RG_LDO_VXO22_HW7_OP_EN_ADDR 0x1ba0 611 #define MT6359P_RG_LDO_VXO22_HW8_OP_EN_ADDR 0x1ba0 612 #define MT6359P_RG_LDO_VXO22_HW9_OP_EN_ADDR 0x1ba0 613 #define MT6359P_RG_LDO_VXO22_HW10_OP_EN_ADDR 0x1ba0 614 #define MT6359P_RG_LDO_VXO22_HW11_OP_EN_ADDR 0x1ba0 615 #define MT6359P_RG_LDO_VXO22_HW12_OP_EN_ADDR 0x1ba0 616 #define MT6359P_RG_LDO_VXO22_HW13_OP_EN_ADDR 0x1ba0 617 #define MT6359P_RG_LDO_VXO22_HW14_OP_EN_ADDR 0x1ba0 618 #define MT6359P_RG_LDO_VXO22_SW_OP_EN_ADDR 0x1ba0 619 #define MT6359P_RG_LDO_VXO22_HW0_OP_CFG_ADDR 0x1ba6 620 #define MT6359P_RG_LDO_VXO22_HW1_OP_CFG_ADDR 0x1ba6 621 #define MT6359P_RG_LDO_VXO22_HW2_OP_CFG_ADDR 0x1ba6 622 #define MT6359P_RG_LDO_VXO22_HW3_OP_CFG_ADDR 0x1ba6 623 #define MT6359P_RG_LDO_VXO22_HW4_OP_CFG_ADDR 0x1ba6 624 #define MT6359P_RG_LDO_VXO22_HW5_OP_CFG_ADDR 0x1ba6 625 #define MT6359P_RG_LDO_VXO22_HW6_OP_CFG_ADDR 0x1ba6 626 #define MT6359P_RG_LDO_VXO22_HW7_OP_CFG_ADDR 0x1ba6 627 #define MT6359P_RG_LDO_VXO22_HW8_OP_CFG_ADDR 0x1ba6 628 #define MT6359P_RG_LDO_VXO22_HW9_OP_CFG_ADDR 0x1ba6 629 #define MT6359P_RG_LDO_VXO22_HW10_OP_CFG_ADDR 0x1ba6 630 #define MT6359P_RG_LDO_VXO22_HW11_OP_CFG_ADDR 0x1ba6 631 #define MT6359P_RG_LDO_VXO22_HW12_OP_CFG_ADDR 0x1ba6 632 #define MT6359P_RG_LDO_VXO22_HW13_OP_CFG_ADDR 0x1ba6 633 #define MT6359P_RG_LDO_VXO22_HW14_OP_CFG_ADDR 0x1ba6 634 #define MT6359P_RG_LDO_VXO22_SW_OP_CFG_ADDR 0x1ba6 635 #define MT6359P_RG_LDO_VRF18_OP_MODE_ADDR 0x1bae 636 #define MT6359P_RG_LDO_VRF18_OP_MODE_SHIFT 10 637 #define MT6359P_RG_LDO_VRF18_HW0_OP_EN_ADDR 0x1bb2 638 #define MT6359P_RG_LDO_VRF18_HW1_OP_EN_ADDR 0x1bb2 639 #define MT6359P_RG_LDO_VRF18_HW2_OP_EN_ADDR 0x1bb2 640 #define MT6359P_RG_LDO_VRF18_HW3_OP_EN_ADDR 0x1bb2 641 #define MT6359P_RG_LDO_VRF18_HW4_OP_EN_ADDR 0x1bb2 642 #define MT6359P_RG_LDO_VRF18_HW5_OP_EN_ADDR 0x1bb2 643 #define MT6359P_RG_LDO_VRF18_HW6_OP_EN_ADDR 0x1bb2 644 #define MT6359P_RG_LDO_VRF18_HW7_OP_EN_ADDR 0x1bb2 645 #define MT6359P_RG_LDO_VRF18_HW8_OP_EN_ADDR 0x1bb2 646 #define MT6359P_RG_LDO_VRF18_HW9_OP_EN_ADDR 0x1bb2 647 #define MT6359P_RG_LDO_VRF18_HW10_OP_EN_ADDR 0x1bb2 648 #define MT6359P_RG_LDO_VRF18_HW11_OP_EN_ADDR 0x1bb2 649 #define MT6359P_RG_LDO_VRF18_HW12_OP_EN_ADDR 0x1bb2 650 #define MT6359P_RG_LDO_VRF18_HW13_OP_EN_ADDR 0x1bb2 651 #define MT6359P_RG_LDO_VRF18_HW14_OP_EN_ADDR 0x1bb2 652 #define MT6359P_RG_LDO_VRF18_SW_OP_EN_ADDR 0x1bb2 653 #define MT6359P_RG_LDO_VRF18_HW0_OP_CFG_ADDR 0x1bb8 654 #define MT6359P_RG_LDO_VRF18_HW1_OP_CFG_ADDR 0x1bb8 655 #define MT6359P_RG_LDO_VRF18_HW2_OP_CFG_ADDR 0x1bb8 656 #define MT6359P_RG_LDO_VRF18_HW3_OP_CFG_ADDR 0x1bb8 657 #define MT6359P_RG_LDO_VRF18_HW4_OP_CFG_ADDR 0x1bb8 658 #define MT6359P_RG_LDO_VRF18_HW5_OP_CFG_ADDR 0x1bb8 659 #define MT6359P_RG_LDO_VRF18_HW6_OP_CFG_ADDR 0x1bb8 660 #define MT6359P_RG_LDO_VRF18_HW7_OP_CFG_ADDR 0x1bb8 661 #define MT6359P_RG_LDO_VRF18_HW8_OP_CFG_ADDR 0x1bb8 662 #define MT6359P_RG_LDO_VRF18_HW9_OP_CFG_ADDR 0x1bb8 663 #define MT6359P_RG_LDO_VRF18_HW10_OP_CFG_ADDR 0x1bb8 664 #define MT6359P_RG_LDO_VRF18_HW11_OP_CFG_ADDR 0x1bb8 665 #define MT6359P_RG_LDO_VRF18_HW12_OP_CFG_ADDR 0x1bb8 666 #define MT6359P_RG_LDO_VRF18_HW13_OP_CFG_ADDR 0x1bb8 667 #define MT6359P_RG_LDO_VRF18_HW14_OP_CFG_ADDR 0x1bb8 668 #define MT6359P_RG_LDO_VRF18_SW_OP_CFG_ADDR 0x1bb8 669 #define MT6359P_RG_LDO_VRF12_OP_MODE_ADDR 0x1bc0 670 #define MT6359P_RG_LDO_VRF12_OP_MODE_SHIFT 10 671 #define MT6359P_RG_LDO_VRF12_HW0_OP_EN_ADDR 0x1bc4 672 #define MT6359P_RG_LDO_VRF12_HW1_OP_EN_ADDR 0x1bc4 673 #define MT6359P_RG_LDO_VRF12_HW2_OP_EN_ADDR 0x1bc4 674 #define MT6359P_RG_LDO_VRF12_HW3_OP_EN_ADDR 0x1bc4 675 #define MT6359P_RG_LDO_VRF12_HW4_OP_EN_ADDR 0x1bc4 676 #define MT6359P_RG_LDO_VRF12_HW5_OP_EN_ADDR 0x1bc4 677 #define MT6359P_RG_LDO_VRF12_HW6_OP_EN_ADDR 0x1bc4 678 #define MT6359P_RG_LDO_VRF12_HW7_OP_EN_ADDR 0x1bc4 679 #define MT6359P_RG_LDO_VRF12_HW8_OP_EN_ADDR 0x1bc4 680 #define MT6359P_RG_LDO_VRF12_HW9_OP_EN_ADDR 0x1bc4 681 #define MT6359P_RG_LDO_VRF12_HW10_OP_EN_ADDR 0x1bc4 682 #define MT6359P_RG_LDO_VRF12_HW11_OP_EN_ADDR 0x1bc4 683 #define MT6359P_RG_LDO_VRF12_HW12_OP_EN_ADDR 0x1bc4 684 #define MT6359P_RG_LDO_VRF12_HW13_OP_EN_ADDR 0x1bc4 685 #define MT6359P_RG_LDO_VRF12_HW14_OP_EN_ADDR 0x1bc4 686 #define MT6359P_RG_LDO_VRF12_SW_OP_EN_ADDR 0x1bc4 687 #define MT6359P_RG_LDO_VRF12_HW0_OP_CFG_ADDR 0x1bca 688 #define MT6359P_RG_LDO_VRF12_HW1_OP_CFG_ADDR 0x1bca 689 #define MT6359P_RG_LDO_VRF12_HW2_OP_CFG_ADDR 0x1bca 690 #define MT6359P_RG_LDO_VRF12_HW3_OP_CFG_ADDR 0x1bca 691 #define MT6359P_RG_LDO_VRF12_HW4_OP_CFG_ADDR 0x1bca 692 #define MT6359P_RG_LDO_VRF12_HW5_OP_CFG_ADDR 0x1bca 693 #define MT6359P_RG_LDO_VRF12_HW6_OP_CFG_ADDR 0x1bca 694 #define MT6359P_RG_LDO_VRF12_HW7_OP_CFG_ADDR 0x1bca 695 #define MT6359P_RG_LDO_VRF12_HW8_OP_CFG_ADDR 0x1bca 696 #define MT6359P_RG_LDO_VRF12_HW9_OP_CFG_ADDR 0x1bca 697 #define MT6359P_RG_LDO_VRF12_HW10_OP_CFG_ADDR 0x1bca 698 #define MT6359P_RG_LDO_VRF12_HW11_OP_CFG_ADDR 0x1bca 699 #define MT6359P_RG_LDO_VRF12_HW12_OP_CFG_ADDR 0x1bca 700 #define MT6359P_RG_LDO_VRF12_HW13_OP_CFG_ADDR 0x1bca 701 #define MT6359P_RG_LDO_VRF12_HW14_OP_CFG_ADDR 0x1bca 702 #define MT6359P_RG_LDO_VRF12_SW_OP_CFG_ADDR 0x1bca 703 #define MT6359P_RG_LDO_VEFUSE_OP_MODE_ADDR 0x1bd2 704 #define MT6359P_RG_LDO_VEFUSE_OP_MODE_SHIFT 10 705 #define MT6359P_RG_LDO_VEFUSE_HW0_OP_EN_ADDR 0x1bd6 706 #define MT6359P_RG_LDO_VEFUSE_HW1_OP_EN_ADDR 0x1bd6 707 #define MT6359P_RG_LDO_VEFUSE_HW2_OP_EN_ADDR 0x1bd6 708 #define MT6359P_RG_LDO_VEFUSE_HW3_OP_EN_ADDR 0x1bd6 709 #define MT6359P_RG_LDO_VEFUSE_HW4_OP_EN_ADDR 0x1bd6 710 #define MT6359P_RG_LDO_VEFUSE_HW5_OP_EN_ADDR 0x1bd6 711 #define MT6359P_RG_LDO_VEFUSE_HW6_OP_EN_ADDR 0x1bd6 712 #define MT6359P_RG_LDO_VEFUSE_HW7_OP_EN_ADDR 0x1bd6 713 #define MT6359P_RG_LDO_VEFUSE_HW8_OP_EN_ADDR 0x1bd6 714 #define MT6359P_RG_LDO_VEFUSE_HW9_OP_EN_ADDR 0x1bd6 715 #define MT6359P_RG_LDO_VEFUSE_HW10_OP_EN_ADDR 0x1bd6 716 #define MT6359P_RG_LDO_VEFUSE_HW11_OP_EN_ADDR 0x1bd6 717 #define MT6359P_RG_LDO_VEFUSE_HW12_OP_EN_ADDR 0x1bd6 718 #define MT6359P_RG_LDO_VEFUSE_HW13_OP_EN_ADDR 0x1bd6 719 #define MT6359P_RG_LDO_VEFUSE_HW14_OP_EN_ADDR 0x1bd6 720 #define MT6359P_RG_LDO_VEFUSE_SW_OP_EN_ADDR 0x1bd6 721 #define MT6359P_RG_LDO_VEFUSE_HW0_OP_CFG_ADDR 0x1bdc 722 #define MT6359P_RG_LDO_VEFUSE_HW1_OP_CFG_ADDR 0x1bdc 723 #define MT6359P_RG_LDO_VEFUSE_HW2_OP_CFG_ADDR 0x1bdc 724 #define MT6359P_RG_LDO_VEFUSE_HW3_OP_CFG_ADDR 0x1bdc 725 #define MT6359P_RG_LDO_VEFUSE_HW4_OP_CFG_ADDR 0x1bdc 726 #define MT6359P_RG_LDO_VEFUSE_HW5_OP_CFG_ADDR 0x1bdc 727 #define MT6359P_RG_LDO_VEFUSE_HW6_OP_CFG_ADDR 0x1bdc 728 #define MT6359P_RG_LDO_VEFUSE_HW7_OP_CFG_ADDR 0x1bdc 729 #define MT6359P_RG_LDO_VEFUSE_HW8_OP_CFG_ADDR 0x1bdc 730 #define MT6359P_RG_LDO_VEFUSE_HW9_OP_CFG_ADDR 0x1bdc 731 #define MT6359P_RG_LDO_VEFUSE_HW10_OP_CFG_ADDR 0x1bdc 732 #define MT6359P_RG_LDO_VEFUSE_HW11_OP_CFG_ADDR 0x1bdc 733 #define MT6359P_RG_LDO_VEFUSE_HW12_OP_CFG_ADDR 0x1bdc 734 #define MT6359P_RG_LDO_VEFUSE_HW13_OP_CFG_ADDR 0x1bdc 735 #define MT6359P_RG_LDO_VEFUSE_HW14_OP_CFG_ADDR 0x1bdc 736 #define MT6359P_RG_LDO_VEFUSE_SW_OP_CFG_ADDR 0x1bdc 737 #define MT6359P_RG_LDO_VCN33_1_OP_MODE_ADDR 0x1be4 738 #define MT6359P_RG_LDO_VCN33_1_OP_MODE_SHIFT 10 739 #define MT6359P_RG_LDO_VCN33_1_HW0_OP_EN_ADDR 0x1be8 740 #define MT6359P_RG_LDO_VCN33_1_HW1_OP_EN_ADDR 0x1be8 741 #define MT6359P_RG_LDO_VCN33_1_HW2_OP_EN_ADDR 0x1be8 742 #define MT6359P_RG_LDO_VCN33_1_HW3_OP_EN_ADDR 0x1be8 743 #define MT6359P_RG_LDO_VCN33_1_HW4_OP_EN_ADDR 0x1be8 744 #define MT6359P_RG_LDO_VCN33_1_HW5_OP_EN_ADDR 0x1be8 745 #define MT6359P_RG_LDO_VCN33_1_HW6_OP_EN_ADDR 0x1be8 746 #define MT6359P_RG_LDO_VCN33_1_HW7_OP_EN_ADDR 0x1be8 747 #define MT6359P_RG_LDO_VCN33_1_HW8_OP_EN_ADDR 0x1be8 748 #define MT6359P_RG_LDO_VCN33_1_HW9_OP_EN_ADDR 0x1be8 749 #define MT6359P_RG_LDO_VCN33_1_HW10_OP_EN_ADDR 0x1be8 750 #define MT6359P_RG_LDO_VCN33_1_HW11_OP_EN_ADDR 0x1be8 751 #define MT6359P_RG_LDO_VCN33_1_HW12_OP_EN_ADDR 0x1be8 752 #define MT6359P_RG_LDO_VCN33_1_HW13_OP_EN_ADDR 0x1be8 753 #define MT6359P_RG_LDO_VCN33_1_HW14_OP_EN_ADDR 0x1be8 754 #define MT6359P_RG_LDO_VCN33_1_SW_OP_EN_ADDR 0x1be8 755 #define MT6359P_RG_LDO_VCN33_1_HW0_OP_CFG_ADDR 0x1bee 756 #define MT6359P_RG_LDO_VCN33_1_HW1_OP_CFG_ADDR 0x1bee 757 #define MT6359P_RG_LDO_VCN33_1_HW2_OP_CFG_ADDR 0x1bee 758 #define MT6359P_RG_LDO_VCN33_1_HW3_OP_CFG_ADDR 0x1bee 759 #define MT6359P_RG_LDO_VCN33_1_HW4_OP_CFG_ADDR 0x1bee 760 #define MT6359P_RG_LDO_VCN33_1_HW5_OP_CFG_ADDR 0x1bee 761 #define MT6359P_RG_LDO_VCN33_1_HW6_OP_CFG_ADDR 0x1bee 762 #define MT6359P_RG_LDO_VCN33_1_HW7_OP_CFG_ADDR 0x1bee 763 #define MT6359P_RG_LDO_VCN33_1_HW8_OP_CFG_ADDR 0x1bee 764 #define MT6359P_RG_LDO_VCN33_1_HW9_OP_CFG_ADDR 0x1bee 765 #define MT6359P_RG_LDO_VCN33_1_HW10_OP_CFG_ADDR 0x1bee 766 #define MT6359P_RG_LDO_VCN33_1_HW11_OP_CFG_ADDR 0x1bee 767 #define MT6359P_RG_LDO_VCN33_1_HW12_OP_CFG_ADDR 0x1bee 768 #define MT6359P_RG_LDO_VCN33_1_HW13_OP_CFG_ADDR 0x1bee 769 #define MT6359P_RG_LDO_VCN33_1_HW14_OP_CFG_ADDR 0x1bee 770 #define MT6359P_RG_LDO_VCN33_1_SW_OP_CFG_ADDR 0x1bee 771 #define MT6359P_RG_LDO_VCN33_2_OP_MODE_ADDR 0x1c0a 772 #define MT6359P_RG_LDO_VCN33_2_OP_MODE_SHIFT 10 773 #define MT6359P_RG_LDO_VCN33_2_HW0_OP_EN_ADDR 0x1c0e 774 #define MT6359P_RG_LDO_VCN33_2_HW1_OP_EN_ADDR 0x1c0e 775 #define MT6359P_RG_LDO_VCN33_2_HW2_OP_EN_ADDR 0x1c0e 776 #define MT6359P_RG_LDO_VCN33_2_HW3_OP_EN_ADDR 0x1c0e 777 #define MT6359P_RG_LDO_VCN33_2_HW4_OP_EN_ADDR 0x1c0e 778 #define MT6359P_RG_LDO_VCN33_2_HW5_OP_EN_ADDR 0x1c0e 779 #define MT6359P_RG_LDO_VCN33_2_HW6_OP_EN_ADDR 0x1c0e 780 #define MT6359P_RG_LDO_VCN33_2_HW7_OP_EN_ADDR 0x1c0e 781 #define MT6359P_RG_LDO_VCN33_2_HW8_OP_EN_ADDR 0x1c0e 782 #define MT6359P_RG_LDO_VCN33_2_HW9_OP_EN_ADDR 0x1c0e 783 #define MT6359P_RG_LDO_VCN33_2_HW10_OP_EN_ADDR 0x1c0e 784 #define MT6359P_RG_LDO_VCN33_2_HW11_OP_EN_ADDR 0x1c0e 785 #define MT6359P_RG_LDO_VCN33_2_HW12_OP_EN_ADDR 0x1c0e 786 #define MT6359P_RG_LDO_VCN33_2_HW13_OP_EN_ADDR 0x1c0e 787 #define MT6359P_RG_LDO_VCN33_2_HW14_OP_EN_ADDR 0x1c0e 788 #define MT6359P_RG_LDO_VCN33_2_SW_OP_EN_ADDR 0x1c0e 789 #define MT6359P_RG_LDO_VCN33_2_HW0_OP_CFG_ADDR 0x1c14 790 #define MT6359P_RG_LDO_VCN33_2_HW1_OP_CFG_ADDR 0x1c14 791 #define MT6359P_RG_LDO_VCN33_2_HW2_OP_CFG_ADDR 0x1c14 792 #define MT6359P_RG_LDO_VCN33_2_HW3_OP_CFG_ADDR 0x1c14 793 #define MT6359P_RG_LDO_VCN33_2_HW4_OP_CFG_ADDR 0x1c14 794 #define MT6359P_RG_LDO_VCN33_2_HW5_OP_CFG_ADDR 0x1c14 795 #define MT6359P_RG_LDO_VCN33_2_HW6_OP_CFG_ADDR 0x1c14 796 #define MT6359P_RG_LDO_VCN33_2_HW7_OP_CFG_ADDR 0x1c14 797 #define MT6359P_RG_LDO_VCN33_2_HW8_OP_CFG_ADDR 0x1c14 798 #define MT6359P_RG_LDO_VCN33_2_HW9_OP_CFG_ADDR 0x1c14 799 #define MT6359P_RG_LDO_VCN33_2_HW10_OP_CFG_ADDR 0x1c14 800 #define MT6359P_RG_LDO_VCN33_2_HW11_OP_CFG_ADDR 0x1c14 801 #define MT6359P_RG_LDO_VCN33_2_HW12_OP_CFG_ADDR 0x1c14 802 #define MT6359P_RG_LDO_VCN33_2_HW13_OP_CFG_ADDR 0x1c14 803 #define MT6359P_RG_LDO_VCN33_2_HW14_OP_CFG_ADDR 0x1c14 804 #define MT6359P_RG_LDO_VCN33_2_SW_OP_CFG_ADDR 0x1c14 805 #define MT6359P_RG_LDO_VCN13_OP_MODE_ADDR 0x1c1e 806 #define MT6359P_RG_LDO_VCN13_OP_MODE_SHIFT 10 807 #define MT6359P_RG_LDO_VCN13_HW0_OP_EN_ADDR 0x1c22 808 #define MT6359P_RG_LDO_VCN13_HW1_OP_EN_ADDR 0x1c22 809 #define MT6359P_RG_LDO_VCN13_HW2_OP_EN_ADDR 0x1c22 810 #define MT6359P_RG_LDO_VCN13_HW3_OP_EN_ADDR 0x1c22 811 #define MT6359P_RG_LDO_VCN13_HW4_OP_EN_ADDR 0x1c22 812 #define MT6359P_RG_LDO_VCN13_HW5_OP_EN_ADDR 0x1c22 813 #define MT6359P_RG_LDO_VCN13_HW6_OP_EN_ADDR 0x1c22 814 #define MT6359P_RG_LDO_VCN13_HW7_OP_EN_ADDR 0x1c22 815 #define MT6359P_RG_LDO_VCN13_HW8_OP_EN_ADDR 0x1c22 816 #define MT6359P_RG_LDO_VCN13_HW9_OP_EN_ADDR 0x1c22 817 #define MT6359P_RG_LDO_VCN13_HW10_OP_EN_ADDR 0x1c22 818 #define MT6359P_RG_LDO_VCN13_HW11_OP_EN_ADDR 0x1c22 819 #define MT6359P_RG_LDO_VCN13_HW12_OP_EN_ADDR 0x1c22 820 #define MT6359P_RG_LDO_VCN13_HW13_OP_EN_ADDR 0x1c22 821 #define MT6359P_RG_LDO_VCN13_HW14_OP_EN_ADDR 0x1c22 822 #define MT6359P_RG_LDO_VCN13_SW_OP_EN_ADDR 0x1c22 823 #define MT6359P_RG_LDO_VCN13_HW0_OP_CFG_ADDR 0x1c28 824 #define MT6359P_RG_LDO_VCN13_HW1_OP_CFG_ADDR 0x1c28 825 #define MT6359P_RG_LDO_VCN13_HW2_OP_CFG_ADDR 0x1c28 826 #define MT6359P_RG_LDO_VCN13_HW3_OP_CFG_ADDR 0x1c28 827 #define MT6359P_RG_LDO_VCN13_HW4_OP_CFG_ADDR 0x1c28 828 #define MT6359P_RG_LDO_VCN13_HW5_OP_CFG_ADDR 0x1c28 829 #define MT6359P_RG_LDO_VCN13_HW6_OP_CFG_ADDR 0x1c28 830 #define MT6359P_RG_LDO_VCN13_HW7_OP_CFG_ADDR 0x1c28 831 #define MT6359P_RG_LDO_VCN13_HW8_OP_CFG_ADDR 0x1c28 832 #define MT6359P_RG_LDO_VCN13_HW9_OP_CFG_ADDR 0x1c28 833 #define MT6359P_RG_LDO_VCN13_HW10_OP_CFG_ADDR 0x1c28 834 #define MT6359P_RG_LDO_VCN13_HW11_OP_CFG_ADDR 0x1c28 835 #define MT6359P_RG_LDO_VCN13_HW12_OP_CFG_ADDR 0x1c28 836 #define MT6359P_RG_LDO_VCN13_HW13_OP_CFG_ADDR 0x1c28 837 #define MT6359P_RG_LDO_VCN13_HW14_OP_CFG_ADDR 0x1c28 838 #define MT6359P_RG_LDO_VCN13_SW_OP_CFG_ADDR 0x1c28 839 #define MT6359P_RG_LDO_VCN18_OP_MODE_ADDR 0x1c30 840 #define MT6359P_RG_LDO_VCN18_OP_MODE_SHIFT 10 841 #define MT6359P_RG_LDO_VCN18_HW0_OP_EN_ADDR 0x1c34 842 #define MT6359P_RG_LDO_VCN18_HW1_OP_EN_ADDR 0x1c34 843 #define MT6359P_RG_LDO_VCN18_HW2_OP_EN_ADDR 0x1c34 844 #define MT6359P_RG_LDO_VCN18_HW3_OP_EN_ADDR 0x1c34 845 #define MT6359P_RG_LDO_VCN18_HW4_OP_EN_ADDR 0x1c34 846 #define MT6359P_RG_LDO_VCN18_HW5_OP_EN_ADDR 0x1c34 847 #define MT6359P_RG_LDO_VCN18_HW6_OP_EN_ADDR 0x1c34 848 #define MT6359P_RG_LDO_VCN18_HW7_OP_EN_ADDR 0x1c34 849 #define MT6359P_RG_LDO_VCN18_HW8_OP_EN_ADDR 0x1c34 850 #define MT6359P_RG_LDO_VCN18_HW9_OP_EN_ADDR 0x1c34 851 #define MT6359P_RG_LDO_VCN18_HW10_OP_EN_ADDR 0x1c34 852 #define MT6359P_RG_LDO_VCN18_HW11_OP_EN_ADDR 0x1c34 853 #define MT6359P_RG_LDO_VCN18_HW12_OP_EN_ADDR 0x1c34 854 #define MT6359P_RG_LDO_VCN18_HW13_OP_EN_ADDR 0x1c34 855 #define MT6359P_RG_LDO_VCN18_HW14_OP_EN_ADDR 0x1c34 856 #define MT6359P_RG_LDO_VCN18_SW_OP_EN_ADDR 0x1c34 857 #define MT6359P_RG_LDO_VCN18_HW0_OP_CFG_ADDR 0x1c3a 858 #define MT6359P_RG_LDO_VCN18_HW1_OP_CFG_ADDR 0x1c3a 859 #define MT6359P_RG_LDO_VCN18_HW2_OP_CFG_ADDR 0x1c3a 860 #define MT6359P_RG_LDO_VCN18_HW3_OP_CFG_ADDR 0x1c3a 861 #define MT6359P_RG_LDO_VCN18_HW4_OP_CFG_ADDR 0x1c3a 862 #define MT6359P_RG_LDO_VCN18_HW5_OP_CFG_ADDR 0x1c3a 863 #define MT6359P_RG_LDO_VCN18_HW6_OP_CFG_ADDR 0x1c3a 864 #define MT6359P_RG_LDO_VCN18_HW7_OP_CFG_ADDR 0x1c3a 865 #define MT6359P_RG_LDO_VCN18_HW8_OP_CFG_ADDR 0x1c3a 866 #define MT6359P_RG_LDO_VCN18_HW9_OP_CFG_ADDR 0x1c3a 867 #define MT6359P_RG_LDO_VCN18_HW10_OP_CFG_ADDR 0x1c3a 868 #define MT6359P_RG_LDO_VCN18_HW11_OP_CFG_ADDR 0x1c3a 869 #define MT6359P_RG_LDO_VCN18_HW12_OP_CFG_ADDR 0x1c3a 870 #define MT6359P_RG_LDO_VCN18_HW13_OP_CFG_ADDR 0x1c3a 871 #define MT6359P_RG_LDO_VCN18_HW14_OP_CFG_ADDR 0x1c3a 872 #define MT6359P_RG_LDO_VCN18_SW_OP_CFG_ADDR 0x1c3a 873 #define MT6359P_RG_LDO_VA09_OP_MODE_ADDR 0x1c42 874 #define MT6359P_RG_LDO_VA09_OP_MODE_SHIFT 10 875 #define MT6359P_RG_LDO_VA09_HW0_OP_EN_ADDR 0x1c46 876 #define MT6359P_RG_LDO_VA09_HW1_OP_EN_ADDR 0x1c46 877 #define MT6359P_RG_LDO_VA09_HW2_OP_EN_ADDR 0x1c46 878 #define MT6359P_RG_LDO_VA09_HW3_OP_EN_ADDR 0x1c46 879 #define MT6359P_RG_LDO_VA09_HW4_OP_EN_ADDR 0x1c46 880 #define MT6359P_RG_LDO_VA09_HW5_OP_EN_ADDR 0x1c46 881 #define MT6359P_RG_LDO_VA09_HW6_OP_EN_ADDR 0x1c46 882 #define MT6359P_RG_LDO_VA09_HW7_OP_EN_ADDR 0x1c46 883 #define MT6359P_RG_LDO_VA09_HW8_OP_EN_ADDR 0x1c46 884 #define MT6359P_RG_LDO_VA09_HW9_OP_EN_ADDR 0x1c46 885 #define MT6359P_RG_LDO_VA09_HW10_OP_EN_ADDR 0x1c46 886 #define MT6359P_RG_LDO_VA09_HW11_OP_EN_ADDR 0x1c46 887 #define MT6359P_RG_LDO_VA09_HW12_OP_EN_ADDR 0x1c46 888 #define MT6359P_RG_LDO_VA09_HW13_OP_EN_ADDR 0x1c46 889 #define MT6359P_RG_LDO_VA09_HW14_OP_EN_ADDR 0x1c46 890 #define MT6359P_RG_LDO_VA09_SW_OP_EN_ADDR 0x1c46 891 #define MT6359P_RG_LDO_VA09_HW0_OP_CFG_ADDR 0x1c4c 892 #define MT6359P_RG_LDO_VA09_HW1_OP_CFG_ADDR 0x1c4c 893 #define MT6359P_RG_LDO_VA09_HW2_OP_CFG_ADDR 0x1c4c 894 #define MT6359P_RG_LDO_VA09_HW3_OP_CFG_ADDR 0x1c4c 895 #define MT6359P_RG_LDO_VA09_HW4_OP_CFG_ADDR 0x1c4c 896 #define MT6359P_RG_LDO_VA09_HW5_OP_CFG_ADDR 0x1c4c 897 #define MT6359P_RG_LDO_VA09_HW6_OP_CFG_ADDR 0x1c4c 898 #define MT6359P_RG_LDO_VA09_HW7_OP_CFG_ADDR 0x1c4c 899 #define MT6359P_RG_LDO_VA09_HW8_OP_CFG_ADDR 0x1c4c 900 #define MT6359P_RG_LDO_VA09_HW9_OP_CFG_ADDR 0x1c4c 901 #define MT6359P_RG_LDO_VA09_HW10_OP_CFG_ADDR 0x1c4c 902 #define MT6359P_RG_LDO_VA09_HW11_OP_CFG_ADDR 0x1c4c 903 #define MT6359P_RG_LDO_VA09_HW12_OP_CFG_ADDR 0x1c4c 904 #define MT6359P_RG_LDO_VA09_HW13_OP_CFG_ADDR 0x1c4c 905 #define MT6359P_RG_LDO_VA09_HW14_OP_CFG_ADDR 0x1c4c 906 #define MT6359P_RG_LDO_VA09_SW_OP_CFG_ADDR 0x1c4c 907 #define MT6359P_RG_LDO_VCAMIO_OP_MODE_ADDR 0x1c54 908 #define MT6359P_RG_LDO_VCAMIO_OP_MODE_SHIFT 10 909 #define MT6359P_RG_LDO_VCAMIO_HW0_OP_EN_ADDR 0x1c58 910 #define MT6359P_RG_LDO_VCAMIO_HW1_OP_EN_ADDR 0x1c58 911 #define MT6359P_RG_LDO_VCAMIO_HW2_OP_EN_ADDR 0x1c58 912 #define MT6359P_RG_LDO_VCAMIO_HW3_OP_EN_ADDR 0x1c58 913 #define MT6359P_RG_LDO_VCAMIO_HW4_OP_EN_ADDR 0x1c58 914 #define MT6359P_RG_LDO_VCAMIO_HW5_OP_EN_ADDR 0x1c58 915 #define MT6359P_RG_LDO_VCAMIO_HW6_OP_EN_ADDR 0x1c58 916 #define MT6359P_RG_LDO_VCAMIO_HW7_OP_EN_ADDR 0x1c58 917 #define MT6359P_RG_LDO_VCAMIO_HW8_OP_EN_ADDR 0x1c58 918 #define MT6359P_RG_LDO_VCAMIO_HW9_OP_EN_ADDR 0x1c58 919 #define MT6359P_RG_LDO_VCAMIO_HW10_OP_EN_ADDR 0x1c58 920 #define MT6359P_RG_LDO_VCAMIO_HW11_OP_EN_ADDR 0x1c58 921 #define MT6359P_RG_LDO_VCAMIO_HW12_OP_EN_ADDR 0x1c58 922 #define MT6359P_RG_LDO_VCAMIO_HW13_OP_EN_ADDR 0x1c58 923 #define MT6359P_RG_LDO_VCAMIO_HW14_OP_EN_ADDR 0x1c58 924 #define MT6359P_RG_LDO_VCAMIO_SW_OP_EN_ADDR 0x1c58 925 #define MT6359P_RG_LDO_VCAMIO_HW0_OP_CFG_ADDR 0x1c5e 926 #define MT6359P_RG_LDO_VCAMIO_HW1_OP_CFG_ADDR 0x1c5e 927 #define MT6359P_RG_LDO_VCAMIO_HW2_OP_CFG_ADDR 0x1c5e 928 #define MT6359P_RG_LDO_VCAMIO_HW3_OP_CFG_ADDR 0x1c5e 929 #define MT6359P_RG_LDO_VCAMIO_HW4_OP_CFG_ADDR 0x1c5e 930 #define MT6359P_RG_LDO_VCAMIO_HW5_OP_CFG_ADDR 0x1c5e 931 #define MT6359P_RG_LDO_VCAMIO_HW6_OP_CFG_ADDR 0x1c5e 932 #define MT6359P_RG_LDO_VCAMIO_HW7_OP_CFG_ADDR 0x1c5e 933 #define MT6359P_RG_LDO_VCAMIO_HW8_OP_CFG_ADDR 0x1c5e 934 #define MT6359P_RG_LDO_VCAMIO_HW9_OP_CFG_ADDR 0x1c5e 935 #define MT6359P_RG_LDO_VCAMIO_HW10_OP_CFG_ADDR 0x1c5e 936 #define MT6359P_RG_LDO_VCAMIO_HW11_OP_CFG_ADDR 0x1c5e 937 #define MT6359P_RG_LDO_VCAMIO_HW12_OP_CFG_ADDR 0x1c5e 938 #define MT6359P_RG_LDO_VCAMIO_HW13_OP_CFG_ADDR 0x1c5e 939 #define MT6359P_RG_LDO_VCAMIO_HW14_OP_CFG_ADDR 0x1c5e 940 #define MT6359P_RG_LDO_VCAMIO_SW_OP_CFG_ADDR 0x1c5e 941 #define MT6359P_RG_LDO_VA12_OP_MODE_ADDR 0x1c66 942 #define MT6359P_RG_LDO_VA12_OP_MODE_SHIFT 10 943 #define MT6359P_RG_LDO_VA12_HW0_OP_EN_ADDR 0x1c6a 944 #define MT6359P_RG_LDO_VA12_HW1_OP_EN_ADDR 0x1c6a 945 #define MT6359P_RG_LDO_VA12_HW2_OP_EN_ADDR 0x1c6a 946 #define MT6359P_RG_LDO_VA12_HW3_OP_EN_ADDR 0x1c6a 947 #define MT6359P_RG_LDO_VA12_HW4_OP_EN_ADDR 0x1c6a 948 #define MT6359P_RG_LDO_VA12_HW5_OP_EN_ADDR 0x1c6a 949 #define MT6359P_RG_LDO_VA12_HW6_OP_EN_ADDR 0x1c6a 950 #define MT6359P_RG_LDO_VA12_HW7_OP_EN_ADDR 0x1c6a 951 #define MT6359P_RG_LDO_VA12_HW8_OP_EN_ADDR 0x1c6a 952 #define MT6359P_RG_LDO_VA12_HW9_OP_EN_ADDR 0x1c6a 953 #define MT6359P_RG_LDO_VA12_HW10_OP_EN_ADDR 0x1c6a 954 #define MT6359P_RG_LDO_VA12_HW11_OP_EN_ADDR 0x1c6a 955 #define MT6359P_RG_LDO_VA12_HW12_OP_EN_ADDR 0x1c6a 956 #define MT6359P_RG_LDO_VA12_HW13_OP_EN_ADDR 0x1c6a 957 #define MT6359P_RG_LDO_VA12_HW14_OP_EN_ADDR 0x1c6a 958 #define MT6359P_RG_LDO_VA12_SW_OP_EN_ADDR 0x1c6a 959 #define MT6359P_RG_LDO_VA12_HW0_OP_CFG_ADDR 0x1c70 960 #define MT6359P_RG_LDO_VA12_HW1_OP_CFG_ADDR 0x1c70 961 #define MT6359P_RG_LDO_VA12_HW2_OP_CFG_ADDR 0x1c70 962 #define MT6359P_RG_LDO_VA12_HW3_OP_CFG_ADDR 0x1c70 963 #define MT6359P_RG_LDO_VA12_HW4_OP_CFG_ADDR 0x1c70 964 #define MT6359P_RG_LDO_VA12_HW5_OP_CFG_ADDR 0x1c70 965 #define MT6359P_RG_LDO_VA12_HW6_OP_CFG_ADDR 0x1c70 966 #define MT6359P_RG_LDO_VA12_HW7_OP_CFG_ADDR 0x1c70 967 #define MT6359P_RG_LDO_VA12_HW8_OP_CFG_ADDR 0x1c70 968 #define MT6359P_RG_LDO_VA12_HW9_OP_CFG_ADDR 0x1c70 969 #define MT6359P_RG_LDO_VA12_HW10_OP_CFG_ADDR 0x1c70 970 #define MT6359P_RG_LDO_VA12_HW11_OP_CFG_ADDR 0x1c70 971 #define MT6359P_RG_LDO_VA12_HW12_OP_CFG_ADDR 0x1c70 972 #define MT6359P_RG_LDO_VA12_HW13_OP_CFG_ADDR 0x1c70 973 #define MT6359P_RG_LDO_VA12_HW14_OP_CFG_ADDR 0x1c70 974 #define MT6359P_RG_LDO_VA12_SW_OP_CFG_ADDR 0x1c70 975 #define MT6359P_RG_LDO_VAUX18_OP_MODE_ADDR 0x1c8a 976 #define MT6359P_RG_LDO_VAUX18_OP_MODE_SHIFT 10 977 #define MT6359P_RG_LDO_VAUX18_HW0_OP_EN_ADDR 0x1c8e 978 #define MT6359P_RG_LDO_VAUX18_HW1_OP_EN_ADDR 0x1c8e 979 #define MT6359P_RG_LDO_VAUX18_HW2_OP_EN_ADDR 0x1c8e 980 #define MT6359P_RG_LDO_VAUX18_HW3_OP_EN_ADDR 0x1c8e 981 #define MT6359P_RG_LDO_VAUX18_HW4_OP_EN_ADDR 0x1c8e 982 #define MT6359P_RG_LDO_VAUX18_HW5_OP_EN_ADDR 0x1c8e 983 #define MT6359P_RG_LDO_VAUX18_HW6_OP_EN_ADDR 0x1c8e 984 #define MT6359P_RG_LDO_VAUX18_HW7_OP_EN_ADDR 0x1c8e 985 #define MT6359P_RG_LDO_VAUX18_HW8_OP_EN_ADDR 0x1c8e 986 #define MT6359P_RG_LDO_VAUX18_HW9_OP_EN_ADDR 0x1c8e 987 #define MT6359P_RG_LDO_VAUX18_HW10_OP_EN_ADDR 0x1c8e 988 #define MT6359P_RG_LDO_VAUX18_HW11_OP_EN_ADDR 0x1c8e 989 #define MT6359P_RG_LDO_VAUX18_HW12_OP_EN_ADDR 0x1c8e 990 #define MT6359P_RG_LDO_VAUX18_HW13_OP_EN_ADDR 0x1c8e 991 #define MT6359P_RG_LDO_VAUX18_HW14_OP_EN_ADDR 0x1c8e 992 #define MT6359P_RG_LDO_VAUX18_SW_OP_EN_ADDR 0x1c8e 993 #define MT6359P_RG_LDO_VAUX18_HW0_OP_CFG_ADDR 0x1c94 994 #define MT6359P_RG_LDO_VAUX18_HW1_OP_CFG_ADDR 0x1c94 995 #define MT6359P_RG_LDO_VAUX18_HW2_OP_CFG_ADDR 0x1c94 996 #define MT6359P_RG_LDO_VAUX18_HW3_OP_CFG_ADDR 0x1c94 997 #define MT6359P_RG_LDO_VAUX18_HW4_OP_CFG_ADDR 0x1c94 998 #define MT6359P_RG_LDO_VAUX18_HW5_OP_CFG_ADDR 0x1c94 999 #define MT6359P_RG_LDO_VAUX18_HW6_OP_CFG_ADDR 0x1c94 1000 #define MT6359P_RG_LDO_VAUX18_HW7_OP_CFG_ADDR 0x1c94 1001 #define MT6359P_RG_LDO_VAUX18_HW8_OP_CFG_ADDR 0x1c94 1002 #define MT6359P_RG_LDO_VAUX18_HW9_OP_CFG_ADDR 0x1c94 1003 #define MT6359P_RG_LDO_VAUX18_HW10_OP_CFG_ADDR 0x1c94 1004 #define MT6359P_RG_LDO_VAUX18_HW11_OP_CFG_ADDR 0x1c94 1005 #define MT6359P_RG_LDO_VAUX18_HW12_OP_CFG_ADDR 0x1c94 1006 #define MT6359P_RG_LDO_VAUX18_HW13_OP_CFG_ADDR 0x1c94 1007 #define MT6359P_RG_LDO_VAUX18_HW14_OP_CFG_ADDR 0x1c94 1008 #define MT6359P_RG_LDO_VAUX18_SW_OP_CFG_ADDR 0x1c94 1009 #define MT6359P_RG_LDO_VAUD18_OP_MODE_ADDR 0x1c9c 1010 #define MT6359P_RG_LDO_VAUD18_OP_MODE_SHIFT 10 1011 #define MT6359P_RG_LDO_VAUD18_HW0_OP_EN_ADDR 0x1ca0 1012 #define MT6359P_RG_LDO_VAUD18_HW1_OP_EN_ADDR 0x1ca0 1013 #define MT6359P_RG_LDO_VAUD18_HW2_OP_EN_ADDR 0x1ca0 1014 #define MT6359P_RG_LDO_VAUD18_HW3_OP_EN_ADDR 0x1ca0 1015 #define MT6359P_RG_LDO_VAUD18_HW4_OP_EN_ADDR 0x1ca0 1016 #define MT6359P_RG_LDO_VAUD18_HW5_OP_EN_ADDR 0x1ca0 1017 #define MT6359P_RG_LDO_VAUD18_HW6_OP_EN_ADDR 0x1ca0 1018 #define MT6359P_RG_LDO_VAUD18_HW7_OP_EN_ADDR 0x1ca0 1019 #define MT6359P_RG_LDO_VAUD18_HW8_OP_EN_ADDR 0x1ca0 1020 #define MT6359P_RG_LDO_VAUD18_HW9_OP_EN_ADDR 0x1ca0 1021 #define MT6359P_RG_LDO_VAUD18_HW10_OP_EN_ADDR 0x1ca0 1022 #define MT6359P_RG_LDO_VAUD18_HW11_OP_EN_ADDR 0x1ca0 1023 #define MT6359P_RG_LDO_VAUD18_HW12_OP_EN_ADDR 0x1ca0 1024 #define MT6359P_RG_LDO_VAUD18_HW13_OP_EN_ADDR 0x1ca0 1025 #define MT6359P_RG_LDO_VAUD18_HW14_OP_EN_ADDR 0x1ca0 1026 #define MT6359P_RG_LDO_VAUD18_SW_OP_EN_ADDR 0x1ca0 1027 #define MT6359P_RG_LDO_VAUD18_HW0_OP_CFG_ADDR 0x1ca6 1028 #define MT6359P_RG_LDO_VAUD18_HW1_OP_CFG_ADDR 0x1ca6 1029 #define MT6359P_RG_LDO_VAUD18_HW2_OP_CFG_ADDR 0x1ca6 1030 #define MT6359P_RG_LDO_VAUD18_HW3_OP_CFG_ADDR 0x1ca6 1031 #define MT6359P_RG_LDO_VAUD18_HW4_OP_CFG_ADDR 0x1ca6 1032 #define MT6359P_RG_LDO_VAUD18_HW5_OP_CFG_ADDR 0x1ca6 1033 #define MT6359P_RG_LDO_VAUD18_HW6_OP_CFG_ADDR 0x1ca6 1034 #define MT6359P_RG_LDO_VAUD18_HW7_OP_CFG_ADDR 0x1ca6 1035 #define MT6359P_RG_LDO_VAUD18_HW8_OP_CFG_ADDR 0x1ca6 1036 #define MT6359P_RG_LDO_VAUD18_HW9_OP_CFG_ADDR 0x1ca6 1037 #define MT6359P_RG_LDO_VAUD18_HW10_OP_CFG_ADDR 0x1ca6 1038 #define MT6359P_RG_LDO_VAUD18_HW11_OP_CFG_ADDR 0x1ca6 1039 #define MT6359P_RG_LDO_VAUD18_HW12_OP_CFG_ADDR 0x1ca6 1040 #define MT6359P_RG_LDO_VAUD18_HW13_OP_CFG_ADDR 0x1ca6 1041 #define MT6359P_RG_LDO_VAUD18_HW14_OP_CFG_ADDR 0x1ca6 1042 #define MT6359P_RG_LDO_VAUD18_SW_OP_CFG_ADDR 0x1ca6 1043 #define MT6359P_RG_LDO_VIO18_OP_MODE_ADDR 0x1cae 1044 #define MT6359P_RG_LDO_VIO18_OP_MODE_SHIFT 10 1045 #define MT6359P_RG_LDO_VIO18_HW0_OP_EN_ADDR 0x1cb2 1046 #define MT6359P_RG_LDO_VIO18_HW1_OP_EN_ADDR 0x1cb2 1047 #define MT6359P_RG_LDO_VIO18_HW2_OP_EN_ADDR 0x1cb2 1048 #define MT6359P_RG_LDO_VIO18_HW3_OP_EN_ADDR 0x1cb2 1049 #define MT6359P_RG_LDO_VIO18_HW4_OP_EN_ADDR 0x1cb2 1050 #define MT6359P_RG_LDO_VIO18_HW5_OP_EN_ADDR 0x1cb2 1051 #define MT6359P_RG_LDO_VIO18_HW6_OP_EN_ADDR 0x1cb2 1052 #define MT6359P_RG_LDO_VIO18_HW7_OP_EN_ADDR 0x1cb2 1053 #define MT6359P_RG_LDO_VIO18_HW8_OP_EN_ADDR 0x1cb2 1054 #define MT6359P_RG_LDO_VIO18_HW9_OP_EN_ADDR 0x1cb2 1055 #define MT6359P_RG_LDO_VIO18_HW10_OP_EN_ADDR 0x1cb2 1056 #define MT6359P_RG_LDO_VIO18_HW11_OP_EN_ADDR 0x1cb2 1057 #define MT6359P_RG_LDO_VIO18_HW12_OP_EN_ADDR 0x1cb2 1058 #define MT6359P_RG_LDO_VIO18_HW13_OP_EN_ADDR 0x1cb2 1059 #define MT6359P_RG_LDO_VIO18_HW14_OP_EN_ADDR 0x1cb2 1060 #define MT6359P_RG_LDO_VIO18_SW_OP_EN_ADDR 0x1cb2 1061 #define MT6359P_RG_LDO_VIO18_HW0_OP_CFG_ADDR 0x1cb8 1062 #define MT6359P_RG_LDO_VIO18_HW1_OP_CFG_ADDR 0x1cb8 1063 #define MT6359P_RG_LDO_VIO18_HW2_OP_CFG_ADDR 0x1cb8 1064 #define MT6359P_RG_LDO_VIO18_HW3_OP_CFG_ADDR 0x1cb8 1065 #define MT6359P_RG_LDO_VIO18_HW4_OP_CFG_ADDR 0x1cb8 1066 #define MT6359P_RG_LDO_VIO18_HW5_OP_CFG_ADDR 0x1cb8 1067 #define MT6359P_RG_LDO_VIO18_HW6_OP_CFG_ADDR 0x1cb8 1068 #define MT6359P_RG_LDO_VIO18_HW7_OP_CFG_ADDR 0x1cb8 1069 #define MT6359P_RG_LDO_VIO18_HW8_OP_CFG_ADDR 0x1cb8 1070 #define MT6359P_RG_LDO_VIO18_HW9_OP_CFG_ADDR 0x1cb8 1071 #define MT6359P_RG_LDO_VIO18_HW10_OP_CFG_ADDR 0x1cb8 1072 #define MT6359P_RG_LDO_VIO18_HW11_OP_CFG_ADDR 0x1cb8 1073 #define MT6359P_RG_LDO_VIO18_HW12_OP_CFG_ADDR 0x1cb8 1074 #define MT6359P_RG_LDO_VIO18_HW13_OP_CFG_ADDR 0x1cb8 1075 #define MT6359P_RG_LDO_VIO18_HW14_OP_CFG_ADDR 0x1cb8 1076 #define MT6359P_RG_LDO_VIO18_SW_OP_CFG_ADDR 0x1cb8 1077 #define MT6359P_RG_LDO_VEMC_OP_MODE_ADDR 0x1cc0 1078 #define MT6359P_RG_LDO_VEMC_OP_MODE_SHIFT 10 1079 #define MT6359P_RG_LDO_VEMC_HW0_OP_EN_ADDR 0x1cc4 1080 #define MT6359P_RG_LDO_VEMC_HW1_OP_EN_ADDR 0x1cc4 1081 #define MT6359P_RG_LDO_VEMC_HW2_OP_EN_ADDR 0x1cc4 1082 #define MT6359P_RG_LDO_VEMC_HW3_OP_EN_ADDR 0x1cc4 1083 #define MT6359P_RG_LDO_VEMC_HW4_OP_EN_ADDR 0x1cc4 1084 #define MT6359P_RG_LDO_VEMC_HW5_OP_EN_ADDR 0x1cc4 1085 #define MT6359P_RG_LDO_VEMC_HW6_OP_EN_ADDR 0x1cc4 1086 #define MT6359P_RG_LDO_VEMC_HW7_OP_EN_ADDR 0x1cc4 1087 #define MT6359P_RG_LDO_VEMC_HW8_OP_EN_ADDR 0x1cc4 1088 #define MT6359P_RG_LDO_VEMC_HW9_OP_EN_ADDR 0x1cc4 1089 #define MT6359P_RG_LDO_VEMC_HW10_OP_EN_ADDR 0x1cc4 1090 #define MT6359P_RG_LDO_VEMC_HW11_OP_EN_ADDR 0x1cc4 1091 #define MT6359P_RG_LDO_VEMC_HW12_OP_EN_ADDR 0x1cc4 1092 #define MT6359P_RG_LDO_VEMC_HW13_OP_EN_ADDR 0x1cc4 1093 #define MT6359P_RG_LDO_VEMC_HW14_OP_EN_ADDR 0x1cc4 1094 #define MT6359P_RG_LDO_VEMC_SW_OP_EN_ADDR 0x1cc4 1095 #define MT6359P_RG_LDO_VEMC_HW0_OP_CFG_ADDR 0x1cca 1096 #define MT6359P_RG_LDO_VEMC_HW1_OP_CFG_ADDR 0x1cca 1097 #define MT6359P_RG_LDO_VEMC_HW2_OP_CFG_ADDR 0x1cca 1098 #define MT6359P_RG_LDO_VEMC_HW3_OP_CFG_ADDR 0x1cca 1099 #define MT6359P_RG_LDO_VEMC_HW4_OP_CFG_ADDR 0x1cca 1100 #define MT6359P_RG_LDO_VEMC_HW5_OP_CFG_ADDR 0x1cca 1101 #define MT6359P_RG_LDO_VEMC_HW6_OP_CFG_ADDR 0x1cca 1102 #define MT6359P_RG_LDO_VEMC_HW7_OP_CFG_ADDR 0x1cca 1103 #define MT6359P_RG_LDO_VEMC_HW8_OP_CFG_ADDR 0x1cca 1104 #define MT6359P_RG_LDO_VEMC_HW9_OP_CFG_ADDR 0x1cca 1105 #define MT6359P_RG_LDO_VEMC_HW10_OP_CFG_ADDR 0x1cca 1106 #define MT6359P_RG_LDO_VEMC_HW11_OP_CFG_ADDR 0x1cca 1107 #define MT6359P_RG_LDO_VEMC_HW12_OP_CFG_ADDR 0x1cca 1108 #define MT6359P_RG_LDO_VEMC_HW13_OP_CFG_ADDR 0x1cca 1109 #define MT6359P_RG_LDO_VEMC_HW14_OP_CFG_ADDR 0x1cca 1110 #define MT6359P_RG_LDO_VEMC_SW_OP_CFG_ADDR 0x1cca 1111 #define MT6359P_RG_LDO_VSIM1_OP_MODE_ADDR 0x1cd2 1112 #define MT6359P_RG_LDO_VSIM1_OP_MODE_SHIFT 10 1113 #define MT6359P_RG_LDO_VSIM1_HW0_OP_EN_ADDR 0x1cd6 1114 #define MT6359P_RG_LDO_VSIM1_HW1_OP_EN_ADDR 0x1cd6 1115 #define MT6359P_RG_LDO_VSIM1_HW2_OP_EN_ADDR 0x1cd6 1116 #define MT6359P_RG_LDO_VSIM1_HW3_OP_EN_ADDR 0x1cd6 1117 #define MT6359P_RG_LDO_VSIM1_HW4_OP_EN_ADDR 0x1cd6 1118 #define MT6359P_RG_LDO_VSIM1_HW5_OP_EN_ADDR 0x1cd6 1119 #define MT6359P_RG_LDO_VSIM1_HW6_OP_EN_ADDR 0x1cd6 1120 #define MT6359P_RG_LDO_VSIM1_HW7_OP_EN_ADDR 0x1cd6 1121 #define MT6359P_RG_LDO_VSIM1_HW8_OP_EN_ADDR 0x1cd6 1122 #define MT6359P_RG_LDO_VSIM1_HW9_OP_EN_ADDR 0x1cd6 1123 #define MT6359P_RG_LDO_VSIM1_HW10_OP_EN_ADDR 0x1cd6 1124 #define MT6359P_RG_LDO_VSIM1_HW11_OP_EN_ADDR 0x1cd6 1125 #define MT6359P_RG_LDO_VSIM1_HW12_OP_EN_ADDR 0x1cd6 1126 #define MT6359P_RG_LDO_VSIM1_HW13_OP_EN_ADDR 0x1cd6 1127 #define MT6359P_RG_LDO_VSIM1_HW14_OP_EN_ADDR 0x1cd6 1128 #define MT6359P_RG_LDO_VSIM1_SW_OP_EN_ADDR 0x1cd6 1129 #define MT6359P_RG_LDO_VSIM1_HW0_OP_CFG_ADDR 0x1cdc 1130 #define MT6359P_RG_LDO_VSIM1_HW1_OP_CFG_ADDR 0x1cdc 1131 #define MT6359P_RG_LDO_VSIM1_HW2_OP_CFG_ADDR 0x1cdc 1132 #define MT6359P_RG_LDO_VSIM1_HW3_OP_CFG_ADDR 0x1cdc 1133 #define MT6359P_RG_LDO_VSIM1_HW4_OP_CFG_ADDR 0x1cdc 1134 #define MT6359P_RG_LDO_VSIM1_HW5_OP_CFG_ADDR 0x1cdc 1135 #define MT6359P_RG_LDO_VSIM1_HW6_OP_CFG_ADDR 0x1cdc 1136 #define MT6359P_RG_LDO_VSIM1_HW7_OP_CFG_ADDR 0x1cdc 1137 #define MT6359P_RG_LDO_VSIM1_HW8_OP_CFG_ADDR 0x1cdc 1138 #define MT6359P_RG_LDO_VSIM1_HW9_OP_CFG_ADDR 0x1cdc 1139 #define MT6359P_RG_LDO_VSIM1_HW10_OP_CFG_ADDR 0x1cdc 1140 #define MT6359P_RG_LDO_VSIM1_HW11_OP_CFG_ADDR 0x1cdc 1141 #define MT6359P_RG_LDO_VSIM1_HW12_OP_CFG_ADDR 0x1cdc 1142 #define MT6359P_RG_LDO_VSIM1_HW13_OP_CFG_ADDR 0x1cdc 1143 #define MT6359P_RG_LDO_VSIM1_HW14_OP_CFG_ADDR 0x1cdc 1144 #define MT6359P_RG_LDO_VSIM1_SW_OP_CFG_ADDR 0x1cdc 1145 #define MT6359P_RG_LDO_VSIM2_OP_MODE_ADDR 0x1ce4 1146 #define MT6359P_RG_LDO_VSIM2_OP_MODE_SHIFT 10 1147 #define MT6359P_RG_LDO_VSIM2_HW0_OP_EN_ADDR 0x1ce8 1148 #define MT6359P_RG_LDO_VSIM2_HW1_OP_EN_ADDR 0x1ce8 1149 #define MT6359P_RG_LDO_VSIM2_HW2_OP_EN_ADDR 0x1ce8 1150 #define MT6359P_RG_LDO_VSIM2_HW3_OP_EN_ADDR 0x1ce8 1151 #define MT6359P_RG_LDO_VSIM2_HW4_OP_EN_ADDR 0x1ce8 1152 #define MT6359P_RG_LDO_VSIM2_HW5_OP_EN_ADDR 0x1ce8 1153 #define MT6359P_RG_LDO_VSIM2_HW6_OP_EN_ADDR 0x1ce8 1154 #define MT6359P_RG_LDO_VSIM2_HW7_OP_EN_ADDR 0x1ce8 1155 #define MT6359P_RG_LDO_VSIM2_HW8_OP_EN_ADDR 0x1ce8 1156 #define MT6359P_RG_LDO_VSIM2_HW9_OP_EN_ADDR 0x1ce8 1157 #define MT6359P_RG_LDO_VSIM2_HW10_OP_EN_ADDR 0x1ce8 1158 #define MT6359P_RG_LDO_VSIM2_HW11_OP_EN_ADDR 0x1ce8 1159 #define MT6359P_RG_LDO_VSIM2_HW12_OP_EN_ADDR 0x1ce8 1160 #define MT6359P_RG_LDO_VSIM2_HW13_OP_EN_ADDR 0x1ce8 1161 #define MT6359P_RG_LDO_VSIM2_HW14_OP_EN_ADDR 0x1ce8 1162 #define MT6359P_RG_LDO_VSIM2_SW_OP_EN_ADDR 0x1ce8 1163 #define MT6359P_RG_LDO_VSIM2_HW0_OP_CFG_ADDR 0x1cee 1164 #define MT6359P_RG_LDO_VSIM2_HW1_OP_CFG_ADDR 0x1cee 1165 #define MT6359P_RG_LDO_VSIM2_HW2_OP_CFG_ADDR 0x1cee 1166 #define MT6359P_RG_LDO_VSIM2_HW3_OP_CFG_ADDR 0x1cee 1167 #define MT6359P_RG_LDO_VSIM2_HW4_OP_CFG_ADDR 0x1cee 1168 #define MT6359P_RG_LDO_VSIM2_HW5_OP_CFG_ADDR 0x1cee 1169 #define MT6359P_RG_LDO_VSIM2_HW6_OP_CFG_ADDR 0x1cee 1170 #define MT6359P_RG_LDO_VSIM2_HW7_OP_CFG_ADDR 0x1cee 1171 #define MT6359P_RG_LDO_VSIM2_HW8_OP_CFG_ADDR 0x1cee 1172 #define MT6359P_RG_LDO_VSIM2_HW9_OP_CFG_ADDR 0x1cee 1173 #define MT6359P_RG_LDO_VSIM2_HW10_OP_CFG_ADDR 0x1cee 1174 #define MT6359P_RG_LDO_VSIM2_HW11_OP_CFG_ADDR 0x1cee 1175 #define MT6359P_RG_LDO_VSIM2_HW12_OP_CFG_ADDR 0x1cee 1176 #define MT6359P_RG_LDO_VSIM2_HW13_OP_CFG_ADDR 0x1cee 1177 #define MT6359P_RG_LDO_VSIM2_HW14_OP_CFG_ADDR 0x1cee 1178 #define MT6359P_RG_LDO_VSIM2_SW_OP_CFG_ADDR 0x1cee 1179 #define MT6359P_RG_LDO_VUSB_OP_MODE_ADDR 0x1d0a 1180 #define MT6359P_RG_LDO_VUSB_OP_MODE_SHIFT 10 1181 #define MT6359P_RG_LDO_VUSB_HW0_OP_EN_ADDR 0x1d0e 1182 #define MT6359P_RG_LDO_VUSB_HW1_OP_EN_ADDR 0x1d0e 1183 #define MT6359P_RG_LDO_VUSB_HW2_OP_EN_ADDR 0x1d0e 1184 #define MT6359P_RG_LDO_VUSB_HW3_OP_EN_ADDR 0x1d0e 1185 #define MT6359P_RG_LDO_VUSB_HW4_OP_EN_ADDR 0x1d0e 1186 #define MT6359P_RG_LDO_VUSB_HW5_OP_EN_ADDR 0x1d0e 1187 #define MT6359P_RG_LDO_VUSB_HW6_OP_EN_ADDR 0x1d0e 1188 #define MT6359P_RG_LDO_VUSB_HW7_OP_EN_ADDR 0x1d0e 1189 #define MT6359P_RG_LDO_VUSB_HW8_OP_EN_ADDR 0x1d0e 1190 #define MT6359P_RG_LDO_VUSB_HW9_OP_EN_ADDR 0x1d0e 1191 #define MT6359P_RG_LDO_VUSB_HW10_OP_EN_ADDR 0x1d0e 1192 #define MT6359P_RG_LDO_VUSB_HW11_OP_EN_ADDR 0x1d0e 1193 #define MT6359P_RG_LDO_VUSB_HW12_OP_EN_ADDR 0x1d0e 1194 #define MT6359P_RG_LDO_VUSB_HW13_OP_EN_ADDR 0x1d0e 1195 #define MT6359P_RG_LDO_VUSB_HW14_OP_EN_ADDR 0x1d0e 1196 #define MT6359P_RG_LDO_VUSB_SW_OP_EN_ADDR 0x1d0e 1197 #define MT6359P_RG_LDO_VUSB_HW0_OP_CFG_ADDR 0x1d14 1198 #define MT6359P_RG_LDO_VUSB_HW1_OP_CFG_ADDR 0x1d14 1199 #define MT6359P_RG_LDO_VUSB_HW2_OP_CFG_ADDR 0x1d14 1200 #define MT6359P_RG_LDO_VUSB_HW3_OP_CFG_ADDR 0x1d14 1201 #define MT6359P_RG_LDO_VUSB_HW4_OP_CFG_ADDR 0x1d14 1202 #define MT6359P_RG_LDO_VUSB_HW5_OP_CFG_ADDR 0x1d14 1203 #define MT6359P_RG_LDO_VUSB_HW6_OP_CFG_ADDR 0x1d14 1204 #define MT6359P_RG_LDO_VUSB_HW7_OP_CFG_ADDR 0x1d14 1205 #define MT6359P_RG_LDO_VUSB_HW8_OP_CFG_ADDR 0x1d14 1206 #define MT6359P_RG_LDO_VUSB_HW9_OP_CFG_ADDR 0x1d14 1207 #define MT6359P_RG_LDO_VUSB_HW10_OP_CFG_ADDR 0x1d14 1208 #define MT6359P_RG_LDO_VUSB_HW11_OP_CFG_ADDR 0x1d14 1209 #define MT6359P_RG_LDO_VUSB_HW12_OP_CFG_ADDR 0x1d14 1210 #define MT6359P_RG_LDO_VUSB_HW13_OP_CFG_ADDR 0x1d14 1211 #define MT6359P_RG_LDO_VUSB_HW14_OP_CFG_ADDR 0x1d14 1212 #define MT6359P_RG_LDO_VUSB_SW_OP_CFG_ADDR 0x1d14 1213 #define MT6359P_RG_LDO_VRFCK_OP_MODE_ADDR 0x1d1e 1214 #define MT6359P_RG_LDO_VRFCK_OP_MODE_SHIFT 10 1215 #define MT6359P_RG_LDO_VRFCK_HW0_OP_EN_ADDR 0x1d22 1216 #define MT6359P_RG_LDO_VRFCK_HW1_OP_EN_ADDR 0x1d22 1217 #define MT6359P_RG_LDO_VRFCK_HW2_OP_EN_ADDR 0x1d22 1218 #define MT6359P_RG_LDO_VRFCK_HW3_OP_EN_ADDR 0x1d22 1219 #define MT6359P_RG_LDO_VRFCK_HW4_OP_EN_ADDR 0x1d22 1220 #define MT6359P_RG_LDO_VRFCK_HW5_OP_EN_ADDR 0x1d22 1221 #define MT6359P_RG_LDO_VRFCK_HW6_OP_EN_ADDR 0x1d22 1222 #define MT6359P_RG_LDO_VRFCK_HW7_OP_EN_ADDR 0x1d22 1223 #define MT6359P_RG_LDO_VRFCK_HW8_OP_EN_ADDR 0x1d22 1224 #define MT6359P_RG_LDO_VRFCK_HW9_OP_EN_ADDR 0x1d22 1225 #define MT6359P_RG_LDO_VRFCK_HW10_OP_EN_ADDR 0x1d22 1226 #define MT6359P_RG_LDO_VRFCK_HW11_OP_EN_ADDR 0x1d22 1227 #define MT6359P_RG_LDO_VRFCK_HW12_OP_EN_ADDR 0x1d22 1228 #define MT6359P_RG_LDO_VRFCK_HW13_OP_EN_ADDR 0x1d22 1229 #define MT6359P_RG_LDO_VRFCK_HW14_OP_EN_ADDR 0x1d22 1230 #define MT6359P_RG_LDO_VRFCK_SW_OP_EN_ADDR 0x1d22 1231 #define MT6359P_RG_LDO_VRFCK_HW0_OP_CFG_ADDR 0x1d28 1232 #define MT6359P_RG_LDO_VRFCK_HW1_OP_CFG_ADDR 0x1d28 1233 #define MT6359P_RG_LDO_VRFCK_HW2_OP_CFG_ADDR 0x1d28 1234 #define MT6359P_RG_LDO_VRFCK_HW3_OP_CFG_ADDR 0x1d28 1235 #define MT6359P_RG_LDO_VRFCK_HW4_OP_CFG_ADDR 0x1d28 1236 #define MT6359P_RG_LDO_VRFCK_HW5_OP_CFG_ADDR 0x1d28 1237 #define MT6359P_RG_LDO_VRFCK_HW6_OP_CFG_ADDR 0x1d28 1238 #define MT6359P_RG_LDO_VRFCK_HW7_OP_CFG_ADDR 0x1d28 1239 #define MT6359P_RG_LDO_VRFCK_HW8_OP_CFG_ADDR 0x1d28 1240 #define MT6359P_RG_LDO_VRFCK_HW9_OP_CFG_ADDR 0x1d28 1241 #define MT6359P_RG_LDO_VRFCK_HW10_OP_CFG_ADDR 0x1d28 1242 #define MT6359P_RG_LDO_VRFCK_HW11_OP_CFG_ADDR 0x1d28 1243 #define MT6359P_RG_LDO_VRFCK_HW12_OP_CFG_ADDR 0x1d28 1244 #define MT6359P_RG_LDO_VRFCK_HW13_OP_CFG_ADDR 0x1d28 1245 #define MT6359P_RG_LDO_VRFCK_HW14_OP_CFG_ADDR 0x1d28 1246 #define MT6359P_RG_LDO_VRFCK_SW_OP_CFG_ADDR 0x1d28 1247 #define MT6359P_RG_LDO_VBBCK_OP_MODE_ADDR 0x1d30 1248 #define MT6359P_RG_LDO_VBBCK_OP_MODE_SHIFT 10 1249 #define MT6359P_RG_LDO_VBBCK_HW0_OP_EN_ADDR 0x1d34 1250 #define MT6359P_RG_LDO_VBBCK_HW1_OP_EN_ADDR 0x1d34 1251 #define MT6359P_RG_LDO_VBBCK_HW2_OP_EN_ADDR 0x1d34 1252 #define MT6359P_RG_LDO_VBBCK_HW3_OP_EN_ADDR 0x1d34 1253 #define MT6359P_RG_LDO_VBBCK_HW4_OP_EN_ADDR 0x1d34 1254 #define MT6359P_RG_LDO_VBBCK_HW5_OP_EN_ADDR 0x1d34 1255 #define MT6359P_RG_LDO_VBBCK_HW6_OP_EN_ADDR 0x1d34 1256 #define MT6359P_RG_LDO_VBBCK_HW7_OP_EN_ADDR 0x1d34 1257 #define MT6359P_RG_LDO_VBBCK_HW8_OP_EN_ADDR 0x1d34 1258 #define MT6359P_RG_LDO_VBBCK_HW9_OP_EN_ADDR 0x1d34 1259 #define MT6359P_RG_LDO_VBBCK_HW10_OP_EN_ADDR 0x1d34 1260 #define MT6359P_RG_LDO_VBBCK_HW11_OP_EN_ADDR 0x1d34 1261 #define MT6359P_RG_LDO_VBBCK_HW12_OP_EN_ADDR 0x1d34 1262 #define MT6359P_RG_LDO_VBBCK_HW13_OP_EN_ADDR 0x1d34 1263 #define MT6359P_RG_LDO_VBBCK_HW14_OP_EN_ADDR 0x1d34 1264 #define MT6359P_RG_LDO_VBBCK_SW_OP_EN_ADDR 0x1d34 1265 #define MT6359P_RG_LDO_VBBCK_HW0_OP_CFG_ADDR 0x1d3a 1266 #define MT6359P_RG_LDO_VBBCK_HW1_OP_CFG_ADDR 0x1d3a 1267 #define MT6359P_RG_LDO_VBBCK_HW2_OP_CFG_ADDR 0x1d3a 1268 #define MT6359P_RG_LDO_VBBCK_HW3_OP_CFG_ADDR 0x1d3a 1269 #define MT6359P_RG_LDO_VBBCK_HW4_OP_CFG_ADDR 0x1d3a 1270 #define MT6359P_RG_LDO_VBBCK_HW5_OP_CFG_ADDR 0x1d3a 1271 #define MT6359P_RG_LDO_VBBCK_HW6_OP_CFG_ADDR 0x1d3a 1272 #define MT6359P_RG_LDO_VBBCK_HW7_OP_CFG_ADDR 0x1d3a 1273 #define MT6359P_RG_LDO_VBBCK_HW8_OP_CFG_ADDR 0x1d3a 1274 #define MT6359P_RG_LDO_VBBCK_HW9_OP_CFG_ADDR 0x1d3a 1275 #define MT6359P_RG_LDO_VBBCK_HW10_OP_CFG_ADDR 0x1d3a 1276 #define MT6359P_RG_LDO_VBBCK_HW11_OP_CFG_ADDR 0x1d3a 1277 #define MT6359P_RG_LDO_VBBCK_HW12_OP_CFG_ADDR 0x1d3a 1278 #define MT6359P_RG_LDO_VBBCK_HW13_OP_CFG_ADDR 0x1d3a 1279 #define MT6359P_RG_LDO_VBBCK_HW14_OP_CFG_ADDR 0x1d3a 1280 #define MT6359P_RG_LDO_VBBCK_SW_OP_CFG_ADDR 0x1d3a 1281 #define MT6359P_RG_LDO_VBIF28_OP_MODE_ADDR 0x1d42 1282 #define MT6359P_RG_LDO_VBIF28_OP_MODE_SHIFT 10 1283 #define MT6359P_RG_LDO_VBIF28_HW0_OP_EN_ADDR 0x1d46 1284 #define MT6359P_RG_LDO_VBIF28_HW1_OP_EN_ADDR 0x1d46 1285 #define MT6359P_RG_LDO_VBIF28_HW2_OP_EN_ADDR 0x1d46 1286 #define MT6359P_RG_LDO_VBIF28_HW3_OP_EN_ADDR 0x1d46 1287 #define MT6359P_RG_LDO_VBIF28_HW4_OP_EN_ADDR 0x1d46 1288 #define MT6359P_RG_LDO_VBIF28_HW5_OP_EN_ADDR 0x1d46 1289 #define MT6359P_RG_LDO_VBIF28_HW6_OP_EN_ADDR 0x1d46 1290 #define MT6359P_RG_LDO_VBIF28_HW7_OP_EN_ADDR 0x1d46 1291 #define MT6359P_RG_LDO_VBIF28_HW8_OP_EN_ADDR 0x1d46 1292 #define MT6359P_RG_LDO_VBIF28_HW9_OP_EN_ADDR 0x1d46 1293 #define MT6359P_RG_LDO_VBIF28_HW10_OP_EN_ADDR 0x1d46 1294 #define MT6359P_RG_LDO_VBIF28_HW11_OP_EN_ADDR 0x1d46 1295 #define MT6359P_RG_LDO_VBIF28_HW12_OP_EN_ADDR 0x1d46 1296 #define MT6359P_RG_LDO_VBIF28_HW13_OP_EN_ADDR 0x1d46 1297 #define MT6359P_RG_LDO_VBIF28_HW14_OP_EN_ADDR 0x1d46 1298 #define MT6359P_RG_LDO_VBIF28_SW_OP_EN_ADDR 0x1d46 1299 #define MT6359P_RG_LDO_VBIF28_HW0_OP_CFG_ADDR 0x1d4c 1300 #define MT6359P_RG_LDO_VBIF28_HW1_OP_CFG_ADDR 0x1d4c 1301 #define MT6359P_RG_LDO_VBIF28_HW2_OP_CFG_ADDR 0x1d4c 1302 #define MT6359P_RG_LDO_VBIF28_HW3_OP_CFG_ADDR 0x1d4c 1303 #define MT6359P_RG_LDO_VBIF28_HW4_OP_CFG_ADDR 0x1d4c 1304 #define MT6359P_RG_LDO_VBIF28_HW5_OP_CFG_ADDR 0x1d4c 1305 #define MT6359P_RG_LDO_VBIF28_HW6_OP_CFG_ADDR 0x1d4c 1306 #define MT6359P_RG_LDO_VBIF28_HW7_OP_CFG_ADDR 0x1d4c 1307 #define MT6359P_RG_LDO_VBIF28_HW8_OP_CFG_ADDR 0x1d4c 1308 #define MT6359P_RG_LDO_VBIF28_HW9_OP_CFG_ADDR 0x1d4c 1309 #define MT6359P_RG_LDO_VBIF28_HW10_OP_CFG_ADDR 0x1d4c 1310 #define MT6359P_RG_LDO_VBIF28_HW11_OP_CFG_ADDR 0x1d4c 1311 #define MT6359P_RG_LDO_VBIF28_HW12_OP_CFG_ADDR 0x1d4c 1312 #define MT6359P_RG_LDO_VBIF28_HW13_OP_CFG_ADDR 0x1d4c 1313 #define MT6359P_RG_LDO_VBIF28_HW14_OP_CFG_ADDR 0x1d4c 1314 #define MT6359P_RG_LDO_VBIF28_SW_OP_CFG_ADDR 0x1d4c 1315 #define MT6359P_RG_LDO_VIBR_OP_MODE_ADDR 0x1d54 1316 #define MT6359P_RG_LDO_VIBR_OP_MODE_SHIFT 10 1317 #define MT6359P_RG_LDO_VIBR_HW0_OP_EN_ADDR 0x1d58 1318 #define MT6359P_RG_LDO_VIBR_HW1_OP_EN_ADDR 0x1d58 1319 #define MT6359P_RG_LDO_VIBR_HW2_OP_EN_ADDR 0x1d58 1320 #define MT6359P_RG_LDO_VIBR_HW3_OP_EN_ADDR 0x1d58 1321 #define MT6359P_RG_LDO_VIBR_HW4_OP_EN_ADDR 0x1d58 1322 #define MT6359P_RG_LDO_VIBR_HW5_OP_EN_ADDR 0x1d58 1323 #define MT6359P_RG_LDO_VIBR_HW6_OP_EN_ADDR 0x1d58 1324 #define MT6359P_RG_LDO_VIBR_HW7_OP_EN_ADDR 0x1d58 1325 #define MT6359P_RG_LDO_VIBR_HW8_OP_EN_ADDR 0x1d58 1326 #define MT6359P_RG_LDO_VIBR_HW9_OP_EN_ADDR 0x1d58 1327 #define MT6359P_RG_LDO_VIBR_HW10_OP_EN_ADDR 0x1d58 1328 #define MT6359P_RG_LDO_VIBR_HW11_OP_EN_ADDR 0x1d58 1329 #define MT6359P_RG_LDO_VIBR_HW12_OP_EN_ADDR 0x1d58 1330 #define MT6359P_RG_LDO_VIBR_HW13_OP_EN_ADDR 0x1d58 1331 #define MT6359P_RG_LDO_VIBR_HW14_OP_EN_ADDR 0x1d58 1332 #define MT6359P_RG_LDO_VIBR_SW_OP_EN_ADDR 0x1d58 1333 #define MT6359P_RG_LDO_VIBR_HW0_OP_CFG_ADDR 0x1d5e 1334 #define MT6359P_RG_LDO_VIBR_HW1_OP_CFG_ADDR 0x1d5e 1335 #define MT6359P_RG_LDO_VIBR_HW2_OP_CFG_ADDR 0x1d5e 1336 #define MT6359P_RG_LDO_VIBR_HW3_OP_CFG_ADDR 0x1d5e 1337 #define MT6359P_RG_LDO_VIBR_HW4_OP_CFG_ADDR 0x1d5e 1338 #define MT6359P_RG_LDO_VIBR_HW5_OP_CFG_ADDR 0x1d5e 1339 #define MT6359P_RG_LDO_VIBR_HW6_OP_CFG_ADDR 0x1d5e 1340 #define MT6359P_RG_LDO_VIBR_HW7_OP_CFG_ADDR 0x1d5e 1341 #define MT6359P_RG_LDO_VIBR_HW8_OP_CFG_ADDR 0x1d5e 1342 #define MT6359P_RG_LDO_VIBR_HW9_OP_CFG_ADDR 0x1d5e 1343 #define MT6359P_RG_LDO_VIBR_HW10_OP_CFG_ADDR 0x1d5e 1344 #define MT6359P_RG_LDO_VIBR_HW11_OP_CFG_ADDR 0x1d5e 1345 #define MT6359P_RG_LDO_VIBR_HW12_OP_CFG_ADDR 0x1d5e 1346 #define MT6359P_RG_LDO_VIBR_HW13_OP_CFG_ADDR 0x1d5e 1347 #define MT6359P_RG_LDO_VIBR_HW14_OP_CFG_ADDR 0x1d5e 1348 #define MT6359P_RG_LDO_VIBR_SW_OP_CFG_ADDR 0x1d5e 1349 #define MT6359P_RG_LDO_VIO28_OP_MODE_ADDR 0x1d66 1350 #define MT6359P_RG_LDO_VIO28_OP_MODE_SHIFT 10 1351 #define MT6359P_RG_LDO_VIO28_HW0_OP_EN_ADDR 0x1d6a 1352 #define MT6359P_RG_LDO_VIO28_HW1_OP_EN_ADDR 0x1d6a 1353 #define MT6359P_RG_LDO_VIO28_HW2_OP_EN_ADDR 0x1d6a 1354 #define MT6359P_RG_LDO_VIO28_HW3_OP_EN_ADDR 0x1d6a 1355 #define MT6359P_RG_LDO_VIO28_HW4_OP_EN_ADDR 0x1d6a 1356 #define MT6359P_RG_LDO_VIO28_HW5_OP_EN_ADDR 0x1d6a 1357 #define MT6359P_RG_LDO_VIO28_HW6_OP_EN_ADDR 0x1d6a 1358 #define MT6359P_RG_LDO_VIO28_HW7_OP_EN_ADDR 0x1d6a 1359 #define MT6359P_RG_LDO_VIO28_HW8_OP_EN_ADDR 0x1d6a 1360 #define MT6359P_RG_LDO_VIO28_HW9_OP_EN_ADDR 0x1d6a 1361 #define MT6359P_RG_LDO_VIO28_HW10_OP_EN_ADDR 0x1d6a 1362 #define MT6359P_RG_LDO_VIO28_HW11_OP_EN_ADDR 0x1d6a 1363 #define MT6359P_RG_LDO_VIO28_HW12_OP_EN_ADDR 0x1d6a 1364 #define MT6359P_RG_LDO_VIO28_HW13_OP_EN_ADDR 0x1d6a 1365 #define MT6359P_RG_LDO_VIO28_HW14_OP_EN_ADDR 0x1d6a 1366 #define MT6359P_RG_LDO_VIO28_SW_OP_EN_ADDR 0x1d6a 1367 #define MT6359P_RG_LDO_VIO28_HW0_OP_CFG_ADDR 0x1d70 1368 #define MT6359P_RG_LDO_VIO28_HW1_OP_CFG_ADDR 0x1d70 1369 #define MT6359P_RG_LDO_VIO28_HW2_OP_CFG_ADDR 0x1d70 1370 #define MT6359P_RG_LDO_VIO28_HW3_OP_CFG_ADDR 0x1d70 1371 #define MT6359P_RG_LDO_VIO28_HW4_OP_CFG_ADDR 0x1d70 1372 #define MT6359P_RG_LDO_VIO28_HW5_OP_CFG_ADDR 0x1d70 1373 #define MT6359P_RG_LDO_VIO28_HW6_OP_CFG_ADDR 0x1d70 1374 #define MT6359P_RG_LDO_VIO28_HW7_OP_CFG_ADDR 0x1d70 1375 #define MT6359P_RG_LDO_VIO28_HW8_OP_CFG_ADDR 0x1d70 1376 #define MT6359P_RG_LDO_VIO28_HW9_OP_CFG_ADDR 0x1d70 1377 #define MT6359P_RG_LDO_VIO28_HW10_OP_CFG_ADDR 0x1d70 1378 #define MT6359P_RG_LDO_VIO28_HW11_OP_CFG_ADDR 0x1d70 1379 #define MT6359P_RG_LDO_VIO28_HW12_OP_CFG_ADDR 0x1d70 1380 #define MT6359P_RG_LDO_VIO28_HW13_OP_CFG_ADDR 0x1d70 1381 #define MT6359P_RG_LDO_VIO28_HW14_OP_CFG_ADDR 0x1d70 1382 #define MT6359P_RG_LDO_VIO28_SW_OP_CFG_ADDR 0x1d70 1383 #define MT6359P_RG_LDO_VM18_OP_MODE_ADDR 0x1d8a 1384 #define MT6359P_RG_LDO_VM18_OP_MODE_SHIFT 10 1385 #define MT6359P_RG_LDO_VM18_HW0_OP_EN_ADDR 0x1d8e 1386 #define MT6359P_RG_LDO_VM18_HW1_OP_EN_ADDR 0x1d8e 1387 #define MT6359P_RG_LDO_VM18_HW2_OP_EN_ADDR 0x1d8e 1388 #define MT6359P_RG_LDO_VM18_HW3_OP_EN_ADDR 0x1d8e 1389 #define MT6359P_RG_LDO_VM18_HW4_OP_EN_ADDR 0x1d8e 1390 #define MT6359P_RG_LDO_VM18_HW5_OP_EN_ADDR 0x1d8e 1391 #define MT6359P_RG_LDO_VM18_HW6_OP_EN_ADDR 0x1d8e 1392 #define MT6359P_RG_LDO_VM18_HW7_OP_EN_ADDR 0x1d8e 1393 #define MT6359P_RG_LDO_VM18_HW8_OP_EN_ADDR 0x1d8e 1394 #define MT6359P_RG_LDO_VM18_HW9_OP_EN_ADDR 0x1d8e 1395 #define MT6359P_RG_LDO_VM18_HW10_OP_EN_ADDR 0x1d8e 1396 #define MT6359P_RG_LDO_VM18_HW11_OP_EN_ADDR 0x1d8e 1397 #define MT6359P_RG_LDO_VM18_HW12_OP_EN_ADDR 0x1d8e 1398 #define MT6359P_RG_LDO_VM18_HW13_OP_EN_ADDR 0x1d8e 1399 #define MT6359P_RG_LDO_VM18_HW14_OP_EN_ADDR 0x1d8e 1400 #define MT6359P_RG_LDO_VM18_SW_OP_EN_ADDR 0x1d8e 1401 #define MT6359P_RG_LDO_VM18_HW0_OP_CFG_ADDR 0x1d94 1402 #define MT6359P_RG_LDO_VM18_HW1_OP_CFG_ADDR 0x1d94 1403 #define MT6359P_RG_LDO_VM18_HW2_OP_CFG_ADDR 0x1d94 1404 #define MT6359P_RG_LDO_VM18_HW3_OP_CFG_ADDR 0x1d94 1405 #define MT6359P_RG_LDO_VM18_HW4_OP_CFG_ADDR 0x1d94 1406 #define MT6359P_RG_LDO_VM18_HW5_OP_CFG_ADDR 0x1d94 1407 #define MT6359P_RG_LDO_VM18_HW6_OP_CFG_ADDR 0x1d94 1408 #define MT6359P_RG_LDO_VM18_HW7_OP_CFG_ADDR 0x1d94 1409 #define MT6359P_RG_LDO_VM18_HW8_OP_CFG_ADDR 0x1d94 1410 #define MT6359P_RG_LDO_VM18_HW9_OP_CFG_ADDR 0x1d94 1411 #define MT6359P_RG_LDO_VM18_HW10_OP_CFG_ADDR 0x1d94 1412 #define MT6359P_RG_LDO_VM18_HW11_OP_CFG_ADDR 0x1d94 1413 #define MT6359P_RG_LDO_VM18_HW12_OP_CFG_ADDR 0x1d94 1414 #define MT6359P_RG_LDO_VM18_HW13_OP_CFG_ADDR 0x1d94 1415 #define MT6359P_RG_LDO_VM18_HW14_OP_CFG_ADDR 0x1d94 1416 #define MT6359P_RG_LDO_VM18_SW_OP_CFG_ADDR 0x1d94 1417 #define MT6359P_RG_LDO_VUFS_OP_MODE_ADDR 0x1d9c 1418 #define MT6359P_RG_LDO_VUFS_OP_MODE_SHIFT 10 1419 #define MT6359P_RG_LDO_VUFS_HW0_OP_EN_ADDR 0x1da0 1420 #define MT6359P_RG_LDO_VUFS_HW1_OP_EN_ADDR 0x1da0 1421 #define MT6359P_RG_LDO_VUFS_HW2_OP_EN_ADDR 0x1da0 1422 #define MT6359P_RG_LDO_VUFS_HW3_OP_EN_ADDR 0x1da0 1423 #define MT6359P_RG_LDO_VUFS_HW4_OP_EN_ADDR 0x1da0 1424 #define MT6359P_RG_LDO_VUFS_HW5_OP_EN_ADDR 0x1da0 1425 #define MT6359P_RG_LDO_VUFS_HW6_OP_EN_ADDR 0x1da0 1426 #define MT6359P_RG_LDO_VUFS_HW7_OP_EN_ADDR 0x1da0 1427 #define MT6359P_RG_LDO_VUFS_HW8_OP_EN_ADDR 0x1da0 1428 #define MT6359P_RG_LDO_VUFS_HW9_OP_EN_ADDR 0x1da0 1429 #define MT6359P_RG_LDO_VUFS_HW10_OP_EN_ADDR 0x1da0 1430 #define MT6359P_RG_LDO_VUFS_HW11_OP_EN_ADDR 0x1da0 1431 #define MT6359P_RG_LDO_VUFS_HW12_OP_EN_ADDR 0x1da0 1432 #define MT6359P_RG_LDO_VUFS_HW13_OP_EN_ADDR 0x1da0 1433 #define MT6359P_RG_LDO_VUFS_HW14_OP_EN_ADDR 0x1da0 1434 #define MT6359P_RG_LDO_VUFS_SW_OP_EN_ADDR 0x1da0 1435 #define MT6359P_RG_LDO_VUFS_HW0_OP_CFG_ADDR 0x1da6 1436 #define MT6359P_RG_LDO_VUFS_HW1_OP_CFG_ADDR 0x1da6 1437 #define MT6359P_RG_LDO_VUFS_HW2_OP_CFG_ADDR 0x1da6 1438 #define MT6359P_RG_LDO_VUFS_HW3_OP_CFG_ADDR 0x1da6 1439 #define MT6359P_RG_LDO_VUFS_HW4_OP_CFG_ADDR 0x1da6 1440 #define MT6359P_RG_LDO_VUFS_HW5_OP_CFG_ADDR 0x1da6 1441 #define MT6359P_RG_LDO_VUFS_HW6_OP_CFG_ADDR 0x1da6 1442 #define MT6359P_RG_LDO_VUFS_HW7_OP_CFG_ADDR 0x1da6 1443 #define MT6359P_RG_LDO_VUFS_HW8_OP_CFG_ADDR 0x1da6 1444 #define MT6359P_RG_LDO_VUFS_HW9_OP_CFG_ADDR 0x1da6 1445 #define MT6359P_RG_LDO_VUFS_HW10_OP_CFG_ADDR 0x1da6 1446 #define MT6359P_RG_LDO_VUFS_HW11_OP_CFG_ADDR 0x1da6 1447 #define MT6359P_RG_LDO_VUFS_HW12_OP_CFG_ADDR 0x1da6 1448 #define MT6359P_RG_LDO_VUFS_HW13_OP_CFG_ADDR 0x1da6 1449 #define MT6359P_RG_LDO_VUFS_HW14_OP_CFG_ADDR 0x1da6 1450 #define MT6359P_RG_LDO_VUFS_SW_OP_CFG_ADDR 0x1da6 1451 #define MT6359P_RG_LDO_VSRAM_PROC1_OP_MODE_ADDR 0x1e8a 1452 #define MT6359P_RG_LDO_VSRAM_PROC1_OP_MODE_SHIFT 10 1453 #define MT6359P_RG_LDO_VSRAM_PROC1_VOSEL_SLEEP_ADDR 0x1e8e 1454 #define MT6359P_RG_LDO_VSRAM_PROC1_HW0_OP_EN_ADDR 0x1e96 1455 #define MT6359P_RG_LDO_VSRAM_PROC1_HW1_OP_EN_ADDR 0x1e96 1456 #define MT6359P_RG_LDO_VSRAM_PROC1_HW2_OP_EN_ADDR 0x1e96 1457 #define MT6359P_RG_LDO_VSRAM_PROC1_HW3_OP_EN_ADDR 0x1e96 1458 #define MT6359P_RG_LDO_VSRAM_PROC1_HW4_OP_EN_ADDR 0x1e96 1459 #define MT6359P_RG_LDO_VSRAM_PROC1_HW5_OP_EN_ADDR 0x1e96 1460 #define MT6359P_RG_LDO_VSRAM_PROC1_HW6_OP_EN_ADDR 0x1e96 1461 #define MT6359P_RG_LDO_VSRAM_PROC1_HW7_OP_EN_ADDR 0x1e96 1462 #define MT6359P_RG_LDO_VSRAM_PROC1_HW8_OP_EN_ADDR 0x1e96 1463 #define MT6359P_RG_LDO_VSRAM_PROC1_HW9_OP_EN_ADDR 0x1e96 1464 #define MT6359P_RG_LDO_VSRAM_PROC1_HW10_OP_EN_ADDR 0x1e96 1465 #define MT6359P_RG_LDO_VSRAM_PROC1_HW11_OP_EN_ADDR 0x1e96 1466 #define MT6359P_RG_LDO_VSRAM_PROC1_HW12_OP_EN_ADDR 0x1e96 1467 #define MT6359P_RG_LDO_VSRAM_PROC1_HW13_OP_EN_ADDR 0x1e96 1468 #define MT6359P_RG_LDO_VSRAM_PROC1_HW14_OP_EN_ADDR 0x1e96 1469 #define MT6359P_RG_LDO_VSRAM_PROC1_SW_OP_EN_ADDR 0x1e96 1470 #define MT6359P_RG_LDO_VSRAM_PROC1_HW0_OP_CFG_ADDR 0x1e9c 1471 #define MT6359P_RG_LDO_VSRAM_PROC1_HW1_OP_CFG_ADDR 0x1e9c 1472 #define MT6359P_RG_LDO_VSRAM_PROC1_HW2_OP_CFG_ADDR 0x1e9c 1473 #define MT6359P_RG_LDO_VSRAM_PROC1_HW3_OP_CFG_ADDR 0x1e9c 1474 #define MT6359P_RG_LDO_VSRAM_PROC1_HW4_OP_CFG_ADDR 0x1e9c 1475 #define MT6359P_RG_LDO_VSRAM_PROC1_HW5_OP_CFG_ADDR 0x1e9c 1476 #define MT6359P_RG_LDO_VSRAM_PROC1_HW6_OP_CFG_ADDR 0x1e9c 1477 #define MT6359P_RG_LDO_VSRAM_PROC1_HW7_OP_CFG_ADDR 0x1e9c 1478 #define MT6359P_RG_LDO_VSRAM_PROC1_HW8_OP_CFG_ADDR 0x1e9c 1479 #define MT6359P_RG_LDO_VSRAM_PROC1_HW9_OP_CFG_ADDR 0x1e9c 1480 #define MT6359P_RG_LDO_VSRAM_PROC1_HW10_OP_CFG_ADDR 0x1e9c 1481 #define MT6359P_RG_LDO_VSRAM_PROC1_HW11_OP_CFG_ADDR 0x1e9c 1482 #define MT6359P_RG_LDO_VSRAM_PROC1_HW12_OP_CFG_ADDR 0x1e9c 1483 #define MT6359P_RG_LDO_VSRAM_PROC1_HW13_OP_CFG_ADDR 0x1e9c 1484 #define MT6359P_RG_LDO_VSRAM_PROC1_HW14_OP_CFG_ADDR 0x1e9c 1485 #define MT6359P_RG_LDO_VSRAM_PROC1_SW_OP_CFG_ADDR 0x1e9c 1486 #define MT6359P_RG_LDO_VSRAM_PROC2_OP_MODE_ADDR 0x1eaa 1487 #define MT6359P_RG_LDO_VSRAM_PROC2_OP_MODE_SHIFT 10 1488 #define MT6359P_RG_LDO_VSRAM_PROC2_VOSEL_SLEEP_ADDR 0x1eae 1489 #define MT6359P_RG_LDO_VSRAM_PROC2_HW0_OP_EN_ADDR 0x1eb6 1490 #define MT6359P_RG_LDO_VSRAM_PROC2_HW1_OP_EN_ADDR 0x1eb6 1491 #define MT6359P_RG_LDO_VSRAM_PROC2_HW2_OP_EN_ADDR 0x1eb6 1492 #define MT6359P_RG_LDO_VSRAM_PROC2_HW3_OP_EN_ADDR 0x1eb6 1493 #define MT6359P_RG_LDO_VSRAM_PROC2_HW4_OP_EN_ADDR 0x1eb6 1494 #define MT6359P_RG_LDO_VSRAM_PROC2_HW5_OP_EN_ADDR 0x1eb6 1495 #define MT6359P_RG_LDO_VSRAM_PROC2_HW6_OP_EN_ADDR 0x1eb6 1496 #define MT6359P_RG_LDO_VSRAM_PROC2_HW7_OP_EN_ADDR 0x1eb6 1497 #define MT6359P_RG_LDO_VSRAM_PROC2_HW8_OP_EN_ADDR 0x1eb6 1498 #define MT6359P_RG_LDO_VSRAM_PROC2_HW9_OP_EN_ADDR 0x1eb6 1499 #define MT6359P_RG_LDO_VSRAM_PROC2_HW10_OP_EN_ADDR 0x1eb6 1500 #define MT6359P_RG_LDO_VSRAM_PROC2_HW11_OP_EN_ADDR 0x1eb6 1501 #define MT6359P_RG_LDO_VSRAM_PROC2_HW12_OP_EN_ADDR 0x1eb6 1502 #define MT6359P_RG_LDO_VSRAM_PROC2_HW13_OP_EN_ADDR 0x1eb6 1503 #define MT6359P_RG_LDO_VSRAM_PROC2_HW14_OP_EN_ADDR 0x1eb6 1504 #define MT6359P_RG_LDO_VSRAM_PROC2_SW_OP_EN_ADDR 0x1eb6 1505 #define MT6359P_RG_LDO_VSRAM_PROC2_HW0_OP_CFG_ADDR 0x1ebc 1506 #define MT6359P_RG_LDO_VSRAM_PROC2_HW1_OP_CFG_ADDR 0x1ebc 1507 #define MT6359P_RG_LDO_VSRAM_PROC2_HW2_OP_CFG_ADDR 0x1ebc 1508 #define MT6359P_RG_LDO_VSRAM_PROC2_HW3_OP_CFG_ADDR 0x1ebc 1509 #define MT6359P_RG_LDO_VSRAM_PROC2_HW4_OP_CFG_ADDR 0x1ebc 1510 #define MT6359P_RG_LDO_VSRAM_PROC2_HW5_OP_CFG_ADDR 0x1ebc 1511 #define MT6359P_RG_LDO_VSRAM_PROC2_HW6_OP_CFG_ADDR 0x1ebc 1512 #define MT6359P_RG_LDO_VSRAM_PROC2_HW7_OP_CFG_ADDR 0x1ebc 1513 #define MT6359P_RG_LDO_VSRAM_PROC2_HW8_OP_CFG_ADDR 0x1ebc 1514 #define MT6359P_RG_LDO_VSRAM_PROC2_HW9_OP_CFG_ADDR 0x1ebc 1515 #define MT6359P_RG_LDO_VSRAM_PROC2_HW10_OP_CFG_ADDR 0x1ebc 1516 #define MT6359P_RG_LDO_VSRAM_PROC2_HW11_OP_CFG_ADDR 0x1ebc 1517 #define MT6359P_RG_LDO_VSRAM_PROC2_HW12_OP_CFG_ADDR 0x1ebc 1518 #define MT6359P_RG_LDO_VSRAM_PROC2_HW13_OP_CFG_ADDR 0x1ebc 1519 #define MT6359P_RG_LDO_VSRAM_PROC2_HW14_OP_CFG_ADDR 0x1ebc 1520 #define MT6359P_RG_LDO_VSRAM_PROC2_SW_OP_CFG_ADDR 0x1ebc 1521 #define MT6359P_RG_LDO_VSRAM_OTHERS_OP_MODE_ADDR 0x1f0a 1522 #define MT6359P_RG_LDO_VSRAM_OTHERS_OP_MODE_SHIFT 10 1523 #define MT6359P_RG_LDO_VSRAM_OTHERS_VOSEL_SLEEP_ADDR 0x1f0e 1524 #define MT6359P_RG_LDO_VSRAM_OTHERS_HW0_OP_EN_ADDR 0x1f16 1525 #define MT6359P_RG_LDO_VSRAM_OTHERS_HW1_OP_EN_ADDR 0x1f16 1526 #define MT6359P_RG_LDO_VSRAM_OTHERS_HW2_OP_EN_ADDR 0x1f16 1527 #define MT6359P_RG_LDO_VSRAM_OTHERS_HW3_OP_EN_ADDR 0x1f16 1528 #define MT6359P_RG_LDO_VSRAM_OTHERS_HW4_OP_EN_ADDR 0x1f16 1529 #define MT6359P_RG_LDO_VSRAM_OTHERS_HW5_OP_EN_ADDR 0x1f16 1530 #define MT6359P_RG_LDO_VSRAM_OTHERS_HW6_OP_EN_ADDR 0x1f16 1531 #define MT6359P_RG_LDO_VSRAM_OTHERS_HW7_OP_EN_ADDR 0x1f16 1532 #define MT6359P_RG_LDO_VSRAM_OTHERS_HW8_OP_EN_ADDR 0x1f16 1533 #define MT6359P_RG_LDO_VSRAM_OTHERS_HW9_OP_EN_ADDR 0x1f16 1534 #define MT6359P_RG_LDO_VSRAM_OTHERS_HW10_OP_EN_ADDR 0x1f16 1535 #define MT6359P_RG_LDO_VSRAM_OTHERS_HW11_OP_EN_ADDR 0x1f16 1536 #define MT6359P_RG_LDO_VSRAM_OTHERS_HW12_OP_EN_ADDR 0x1f16 1537 #define MT6359P_RG_LDO_VSRAM_OTHERS_HW13_OP_EN_ADDR 0x1f16 1538 #define MT6359P_RG_LDO_VSRAM_OTHERS_HW14_OP_EN_ADDR 0x1f16 1539 #define MT6359P_RG_LDO_VSRAM_OTHERS_SW_OP_EN_ADDR 0x1f16 1540 #define MT6359P_RG_LDO_VSRAM_OTHERS_HW0_OP_CFG_ADDR 0x1f1c 1541 #define MT6359P_RG_LDO_VSRAM_OTHERS_HW1_OP_CFG_ADDR 0x1f1c 1542 #define MT6359P_RG_LDO_VSRAM_OTHERS_HW2_OP_CFG_ADDR 0x1f1c 1543 #define MT6359P_RG_LDO_VSRAM_OTHERS_HW3_OP_CFG_ADDR 0x1f1c 1544 #define MT6359P_RG_LDO_VSRAM_OTHERS_HW4_OP_CFG_ADDR 0x1f1c 1545 #define MT6359P_RG_LDO_VSRAM_OTHERS_HW5_OP_CFG_ADDR 0x1f1c 1546 #define MT6359P_RG_LDO_VSRAM_OTHERS_HW6_OP_CFG_ADDR 0x1f1c 1547 #define MT6359P_RG_LDO_VSRAM_OTHERS_HW7_OP_CFG_ADDR 0x1f1c 1548 #define MT6359P_RG_LDO_VSRAM_OTHERS_HW8_OP_CFG_ADDR 0x1f1c 1549 #define MT6359P_RG_LDO_VSRAM_OTHERS_HW9_OP_CFG_ADDR 0x1f1c 1550 #define MT6359P_RG_LDO_VSRAM_OTHERS_HW10_OP_CFG_ADDR 0x1f1c 1551 #define MT6359P_RG_LDO_VSRAM_OTHERS_HW11_OP_CFG_ADDR 0x1f1c 1552 #define MT6359P_RG_LDO_VSRAM_OTHERS_HW12_OP_CFG_ADDR 0x1f1c 1553 #define MT6359P_RG_LDO_VSRAM_OTHERS_HW13_OP_CFG_ADDR 0x1f1c 1554 #define MT6359P_RG_LDO_VSRAM_OTHERS_HW14_OP_CFG_ADDR 0x1f1c 1555 #define MT6359P_RG_LDO_VSRAM_OTHERS_SW_OP_CFG_ADDR 0x1f1c 1556 #define MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SLEEP_ADDR 0x1f28 1557 #define MT6359P_RG_LDO_VSRAM_MD_OP_MODE_ADDR 0x1f30 1558 #define MT6359P_RG_LDO_VSRAM_MD_OP_MODE_SHIFT 10 1559 #define MT6359P_RG_LDO_VSRAM_MD_VOSEL_SLEEP_ADDR 0x1f34 1560 #define MT6359P_RG_LDO_VSRAM_MD_HW0_OP_EN_ADDR 0x1f3c 1561 #define MT6359P_RG_LDO_VSRAM_MD_HW1_OP_EN_ADDR 0x1f3c 1562 #define MT6359P_RG_LDO_VSRAM_MD_HW2_OP_EN_ADDR 0x1f3c 1563 #define MT6359P_RG_LDO_VSRAM_MD_HW3_OP_EN_ADDR 0x1f3c 1564 #define MT6359P_RG_LDO_VSRAM_MD_HW4_OP_EN_ADDR 0x1f3c 1565 #define MT6359P_RG_LDO_VSRAM_MD_HW5_OP_EN_ADDR 0x1f3c 1566 #define MT6359P_RG_LDO_VSRAM_MD_HW6_OP_EN_ADDR 0x1f3c 1567 #define MT6359P_RG_LDO_VSRAM_MD_HW7_OP_EN_ADDR 0x1f3c 1568 #define MT6359P_RG_LDO_VSRAM_MD_HW8_OP_EN_ADDR 0x1f3c 1569 #define MT6359P_RG_LDO_VSRAM_MD_HW9_OP_EN_ADDR 0x1f3c 1570 #define MT6359P_RG_LDO_VSRAM_MD_HW10_OP_EN_ADDR 0x1f3c 1571 #define MT6359P_RG_LDO_VSRAM_MD_HW11_OP_EN_ADDR 0x1f3c 1572 #define MT6359P_RG_LDO_VSRAM_MD_HW12_OP_EN_ADDR 0x1f3c 1573 #define MT6359P_RG_LDO_VSRAM_MD_HW13_OP_EN_ADDR 0x1f3c 1574 #define MT6359P_RG_LDO_VSRAM_MD_HW14_OP_EN_ADDR 0x1f3c 1575 #define MT6359P_RG_LDO_VSRAM_MD_SW_OP_EN_ADDR 0x1f3c 1576 #define MT6359P_RG_LDO_VSRAM_MD_HW0_OP_CFG_ADDR 0x1f42 1577 #define MT6359P_RG_LDO_VSRAM_MD_HW1_OP_CFG_ADDR 0x1f42 1578 #define MT6359P_RG_LDO_VSRAM_MD_HW2_OP_CFG_ADDR 0x1f42 1579 #define MT6359P_RG_LDO_VSRAM_MD_HW3_OP_CFG_ADDR 0x1f42 1580 #define MT6359P_RG_LDO_VSRAM_MD_HW4_OP_CFG_ADDR 0x1f42 1581 #define MT6359P_RG_LDO_VSRAM_MD_HW5_OP_CFG_ADDR 0x1f42 1582 #define MT6359P_RG_LDO_VSRAM_MD_HW6_OP_CFG_ADDR 0x1f42 1583 #define MT6359P_RG_LDO_VSRAM_MD_HW7_OP_CFG_ADDR 0x1f42 1584 #define MT6359P_RG_LDO_VSRAM_MD_HW8_OP_CFG_ADDR 0x1f42 1585 #define MT6359P_RG_LDO_VSRAM_MD_HW9_OP_CFG_ADDR 0x1f42 1586 #define MT6359P_RG_LDO_VSRAM_MD_HW10_OP_CFG_ADDR 0x1f42 1587 #define MT6359P_RG_LDO_VSRAM_MD_HW11_OP_CFG_ADDR 0x1f42 1588 #define MT6359P_RG_LDO_VSRAM_MD_HW12_OP_CFG_ADDR 0x1f42 1589 #define MT6359P_RG_LDO_VSRAM_MD_HW13_OP_CFG_ADDR 0x1f42 1590 #define MT6359P_RG_LDO_VSRAM_MD_HW14_OP_CFG_ADDR 0x1f42 1591 #define MT6359P_RG_LDO_VSRAM_MD_SW_OP_CFG_ADDR 0x1f42 1592 1593 #endif /* MT6359P_LOWPOWER_REG_H */ 1594