13374752fSBo-Chen Chen /* 23374752fSBo-Chen Chen * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. 33374752fSBo-Chen Chen * 43374752fSBo-Chen Chen * SPDX-License-Identifier: BSD-3-Clause 53374752fSBo-Chen Chen */ 63374752fSBo-Chen Chen 73374752fSBo-Chen Chen #ifndef MT_TIMER_H 83374752fSBo-Chen Chen #define MT_TIMER_H 93374752fSBo-Chen Chen 10*a65fadfbSGavin Liu #include "platform_def.h" 11*a65fadfbSGavin Liu 12*a65fadfbSGavin Liu #ifndef SYSTIMER_BASE 133374752fSBo-Chen Chen #define SYSTIMER_BASE (0x10017000) 14*a65fadfbSGavin Liu #endif 15*a65fadfbSGavin Liu 163374752fSBo-Chen Chen #define CNTCR_REG (SYSTIMER_BASE + 0x0) 173374752fSBo-Chen Chen #define CNTSR_REG (SYSTIMER_BASE + 0x4) 183374752fSBo-Chen Chen #define CNTSYS_L_REG (SYSTIMER_BASE + 0x8) 193374752fSBo-Chen Chen #define CNTSYS_H_REG (SYSTIMER_BASE + 0xc) 203374752fSBo-Chen Chen #define CNTWACR_REG (SYSTIMER_BASE + 0x10) 213374752fSBo-Chen Chen #define CNTRACR_REG (SYSTIMER_BASE + 0x14) 223374752fSBo-Chen Chen 233374752fSBo-Chen Chen #define TIEO_EN (1 << 3) 243374752fSBo-Chen Chen #define COMP_15_EN (1 << 10) 253374752fSBo-Chen Chen #define COMP_20_EN (1 << 11) 263374752fSBo-Chen Chen #define COMP_25_EN (1 << 12) 273374752fSBo-Chen Chen 283374752fSBo-Chen Chen #define COMP_FEATURE_MASK (COMP_15_EN | COMP_20_EN | COMP_25_EN | TIEO_EN) 293374752fSBo-Chen Chen #define COMP_15_MASK (COMP_15_EN) 303374752fSBo-Chen Chen #define COMP_20_MASK (COMP_20_EN | TIEO_EN) 313374752fSBo-Chen Chen #define COMP_25_MASK (COMP_20_EN | COMP_25_EN) 323374752fSBo-Chen Chen 333374752fSBo-Chen Chen #define CNT_WRITE_ACCESS_CTL_MASK (0x3FFFFF0U) 343374752fSBo-Chen Chen #define CNT_READ_ACCESS_CTL_MASK (0x3FFFFFFU) 353374752fSBo-Chen Chen 363374752fSBo-Chen Chen void sched_clock_init(uint64_t normal_base, uint64_t atf_base); 373374752fSBo-Chen Chen uint64_t sched_clock(void); 38215869c6SRex-BC Chen int mt_systimer_init(void); 393374752fSBo-Chen Chen 403374752fSBo-Chen Chen #endif /* MT_TIMER_H */ 41