xref: /rk3399_ARM-atf/plat/mediatek/drivers/timer/mt_timer.h (revision ffb93d41f953c42bfa747964ddc23ccda391e553)
1 /*
2  * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef MT_TIMER_H
8 #define MT_TIMER_H
9 
10 #include "platform_def.h"
11 
12 #ifndef SYSTIMER_BASE
13 #define SYSTIMER_BASE       (0x10017000)
14 #endif
15 
16 #define CNTCR_REG           (SYSTIMER_BASE + 0x0)
17 #define CNTSR_REG           (SYSTIMER_BASE + 0x4)
18 #define CNTSYS_L_REG        (SYSTIMER_BASE + 0x8)
19 #define CNTSYS_H_REG        (SYSTIMER_BASE + 0xc)
20 #define CNTWACR_REG         (SYSTIMER_BASE + 0x10)
21 #define CNTRACR_REG         (SYSTIMER_BASE + 0x14)
22 
23 #define TIEO_EN             (1 << 3)
24 #define COMP_15_EN          (1 << 10)
25 #define COMP_20_EN          (1 << 11)
26 #define COMP_25_EN          (1 << 12)
27 
28 #define COMP_FEATURE_MASK (COMP_15_EN | COMP_20_EN | COMP_25_EN | TIEO_EN)
29 #define COMP_15_MASK (COMP_15_EN)
30 #define COMP_20_MASK (COMP_20_EN | TIEO_EN)
31 #define COMP_25_MASK (COMP_20_EN | COMP_25_EN)
32 
33 #define CNT_WRITE_ACCESS_CTL_MASK (0x3FFFFF0U)
34 #define CNT_READ_ACCESS_CTL_MASK  (0x3FFFFFFU)
35 
36 void sched_clock_init(uint64_t normal_base, uint64_t atf_base);
37 uint64_t sched_clock(void);
38 int mt_systimer_init(void);
39 
40 #endif /* MT_TIMER_H */
41