xref: /rk3399_ARM-atf/plat/mediatek/drivers/spmi/pmif_v1/pmif.h (revision cf2df874cd09305ac7282fadb0fef6be597dfffb)
1 /*
2  * Copyright (c) 2025, Mediatek Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef PMIF_H
8 #define PMIF_H
9 
10 #include <stdint.h>
11 
12 #include <platform_def.h>
13 
14 #include <drivers/spmi/pmif_common.h>
15 #include <drivers/spmi/spmi_common.h>
16 
17 enum pmif_regs {
18 	PMIF_INIT_DONE,
19 	PMIF_INF_EN,
20 	PMIF_ARB_EN,
21 	PMIF_IRQ_EVENT_EN_0,
22 	PMIF_IRQ_FLAG_0,
23 	PMIF_IRQ_CLR_0,
24 	PMIF_IRQ_EVENT_EN_2,
25 	PMIF_IRQ_FLAG_2,
26 	PMIF_IRQ_CLR_2,
27 	PMIF_WDT_CTRL,
28 	PMIF_WDT_EVENT_EN_1,
29 	PMIF_WDT_FLAG_1,
30 	PMIF_SWINF_2_ACC,
31 	PMIF_SWINF_2_WDATA_31_0,
32 	PMIF_SWINF_2_WDATA_63_32,
33 	PMIF_SWINF_2_RDATA_31_0,
34 	PMIF_SWINF_2_RDATA_63_32,
35 	PMIF_SWINF_2_VLD_CLR,
36 	PMIF_SWINF_2_STA,
37 	PMIF_SWINF_3_ACC,
38 	PMIF_SWINF_3_WDATA_31_0,
39 	PMIF_SWINF_3_WDATA_63_32,
40 	PMIF_SWINF_3_RDATA_31_0,
41 	PMIF_SWINF_3_RDATA_63_32,
42 	PMIF_SWINF_3_VLD_CLR,
43 	PMIF_SWINF_3_STA,
44 	/* HW MPU */
45 	PMIF_PMIC_ALL_RGN_EN_1,
46 	PMIF_PMIC_ALL_RGN_EN_2,
47 	PMIF_PMIC_ALL_RGN_0_START,
48 	PMIF_PMIC_ALL_RGN_0_END,
49 	PMIF_PMIC_ALL_RGN_1_START,
50 	PMIF_PMIC_ALL_RGN_1_END,
51 	PMIF_PMIC_ALL_RGN_2_START,
52 	PMIF_PMIC_ALL_RGN_2_END,
53 	PMIF_PMIC_ALL_RGN_3_START,
54 	PMIF_PMIC_ALL_RGN_3_END,
55 	PMIF_PMIC_ALL_RGN_31_START,
56 	PMIF_PMIC_ALL_RGN_31_END,
57 	PMIF_PMIC_ALL_INVLD_SLVID,
58 	PMIF_PMIC_ALL_RGN_0_PER0,
59 	PMIF_PMIC_ALL_RGN_0_PER1,
60 	PMIF_PMIC_ALL_RGN_1_PER0,
61 	PMIF_PMIC_ALL_RGN_2_PER0,
62 	PMIF_PMIC_ALL_RGN_3_PER0,
63 	PMIF_PMIC_ALL_RGN_31_PER0,
64 	PMIF_PMIC_ALL_RGN_31_PER1,
65 	PMIF_PMIC_ALL_RGN_OTHERS_PER0,
66 	PMIF_PMIC_ALL_RGN_OTHERS_PER1,
67 };
68 #endif
69