1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MT_SPM_VCOREFS_COMMON_H 8 #define MT_SPM_VCOREFS_COMMON_H 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************* 13 * 14 * DVFSRC Function Return Value & Other Macro Definition 15 * 16 *******************************************************************/ 17 #define VCOREFS_SUCCESS 0 18 #define VCOREFS_E_NOT_SUPPORTED -1 19 #define VCOREFS_E_SPMFW_NOT_READY 0 20 21 #define TAG "vcorefs: " 22 #define v_min(a, b) MAX(a, b) 23 #define v_max(a, b) MIN(a, b) 24 25 /******************************************************************* 26 * 27 * VCOREFS CMD 28 * 29 ********************************************************************/ 30 enum vcorefs_smc_cmd { 31 VCOREFS_SMC_VCORE_DVFS_INIT = 0, 32 VCOREFS_SMC_VCORE_DVFS_KICK = 1, 33 VCOREFS_SMC_CMD_OPP_TYPE = 2, 34 VCOREFS_SMC_CMD_FW_TYPE = 3, 35 VCOREFS_SMC_CMD_GET_UV = 4, 36 VCOREFS_SMC_CMD_GET_FREQ = 5, 37 VCOREFS_SMC_CMD_GET_NUM_V = 6, 38 VCOREFS_SMC_CMD_GET_NUM_F = 7, 39 40 /*chip specific setting */ 41 VCOREFS_SMC_CMD_GET_VCORE_INFO = 18, 42 43 /*qos specific setting */ 44 VCOREFS_SMC_CMD_QOS_MODE = 32, 45 VCOREFS_SMC_CMD_PAUSE_ENABLE = 33, 46 47 /*spm resource request */ 48 VCOREFS_SMC_RSC_MEM_REQ = 64, 49 VCOREFS_SMC_RSC_MEM_REL = 65, 50 }; 51 52 struct reg_config { 53 uint32_t offset; 54 uint32_t val; 55 }; 56 57 #endif /* MT_SPM_VCOREFS_COMMON_H */ 58