xref: /rk3399_ARM-atf/plat/mediatek/drivers/pmic_wrap/pmic_wrap_v3.h (revision 52c47c174fadb9e1398af41e9bbf290af314e8ec)
1 /*
2  * Copyright (c) 2025, MediaTek Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef PMIC_WRAP_V3_H
8 #define PMIC_WRAP_V3_H
9 
10 #include <stdint.h>
11 
12 #include <common/debug.h>
13 #include <drivers/console.h>
14 
15 #define PMIF_REG_RANGE			(0x774)
16 #define PMICSPI_MST_REG_RANGE		(0x80)
17 #define DEFAULT_CMD			0
18 #define DEFAULT_SLVID			0
19 #define DEFAULT_BYTECNT			0
20 #define PMIF_SPI_PMIFID			0
21 /* #define PWRAP_DEBUG 1 */
22 
23 #if PWRAP_DEBUG
24 #define PWRAP_LOG(fmts, args...) do {\
25 		console_init(gteearg.atf_log_port, UART_CLOCK, UART_BAUDRATE);\
26 		INFO("[%s:%d] -" fmts, __func__, __LINE__, ##args);\
27 		console_uninit();\
28 	} while (0)
29 #endif
30 
31 /**********************************************************/
32 #define DEFAULT_VALUE_READ_TEST		(0x5aa5)
33 #define PWRAP_WRITE_TEST_VALUE		(0xa55a)
34 #define PWRAP_POLL_STEP_US		(10)
35 
36 /* timeout setting */
37 enum {
38 	TIMEOUT_RESET		= 50,	/* us */
39 	TIMEOUT_READ		= 50,	/* us */
40 	TIMEOUT_WAIT_IDLE	= 50	/* us */
41 };
42 
43 #endif /* PMIC_WRAP_V3_H */
44