1 /* 2 * Copyright (c) 2025, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MT_CPU_PM_MBOX_H 8 #define MT_CPU_PM_MBOX_H 9 10 #define MCUPM_MBOX_AP_READY 0 11 #define MCUPM_MBOX_GROUP 1 12 #define MCUPM_MBOX_RESERVED_2 2 13 #define MCUPM_MBOX_RESERVED_3 3 14 #define MCUPM_MBOX_PWR_CTRL_EN 4 15 #define MCUPM_MBOX_L3_CACHE_MODE 5 16 #define MCUPM_MBOX_BUCK_MODE 6 17 #define MCUPM_MBOX_ARMPLL_MODE 7 18 19 #define MCUPM_MBOX_TASK_STA 8 20 #define MCUPM_MBOX_RESERVED_9 9 21 #define MCUPM_MBOX_RESERVED_10 10 22 #define MCUPM_MBOX_RESERVED_11 11 23 #define MCUPM_MBOX_WAKEUP_CPU 12 24 25 #define MCUPM_MCUSYS_CTRL BIT(0) 26 #define MCUPM_BUCK_CTRL BIT(1) 27 #define MCUPM_ARMPLL_CTRL BIT(2) 28 #define MCUPM_CM_CTRL BIT(3) 29 30 #define MCUPM_L3_OFF_MODE 0 31 #define MCUPM_L3_DORMANT_MODE 1 32 #define NF_MCUPM_L3_MODE 2U 33 34 #define MCUPM_BUCK_NORMAL_MODE 0 35 #define MCUPM_BUCK_LP_MODE 1 36 #define MCUPM_BUCK_OFF_MODE 2 37 #define NF_MCUPM_BUCK_MODE 3U 38 39 #define MCUPM_ARMPLL_ON 0 40 #define MCUPM_ARMPLL_GATING 1 41 #define MCUPM_ARMPLL_OFF 2 42 #define NF_MCUPM_ARMPLL_MODE 3U 43 44 #define MCUPM_TASK_UNINIT 0 45 #define MCUPM_TASK_INIT 1 46 #define MCUPM_TASK_INIT_FINISH 2 47 #define MCUPM_TASK_WAIT 3 48 #define MCUPM_TASK_RUN 4 49 #define MCUPM_TASK_PAUSE 5 50 51 void mtk_set_mcupm_pll_mode(unsigned int mode); 52 int mtk_get_mcupm_pll_mode(void); 53 54 void mtk_set_mcupm_buck_mode(unsigned int mode); 55 int mtk_get_mcupm_buck_mode(void); 56 57 void mtk_set_cpu_pm_preffered_cpu(unsigned int cpuid); 58 unsigned int mtk_get_cpu_pm_preffered_cpu(void); 59 60 void mtk_set_mcupm_group_hint(unsigned int gmask); 61 62 enum cpupm_mbox_depd_type { 63 CPUPM_MBOX_WAIT_DEV_INIT, 64 CPUPM_MBOX_WAIT_TASK_READY, 65 }; 66 67 int mtk_lp_depd_condition(enum cpupm_mbox_depd_type type); 68 69 #endif /* MT_CPU_PM_MBOX_H */ 70