1 /* 2 * Copyright (c) 2025, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MT_CPU_PM_CPC_H 8 #define MT_CPU_PM_CPC_H 9 10 #include <lib/mmio.h> 11 #include <platform_def.h> 12 #include <mcucfg.h> 13 #include <mcupm_cfg.h> 14 15 #define NEED_CPUSYS_PROT_WORKAROUND 1 16 17 /* system sram registers */ 18 #define CPUIDLE_SRAM_REG(r) (0x11B000 + (r)) 19 20 /* db dump */ 21 #define CPC_TRACE_SIZE 0x20 22 #define CPC_TRACE_ID_NUM 13 23 #define CPC_TRACE_SRAM(id) (CPUIDLE_SRAM_REG(0x10) + (id) * CPC_TRACE_SIZE) 24 25 /* backup off count */ 26 #define SYSRAM_RECENT_CPU_CNT(i) CPUIDLE_SRAM_REG(4 * (i) + 0x1B0) 27 #define SYSRAM_RECENT_CLUSTER_CNT CPUIDLE_SRAM_REG(0x1D0) 28 #define SYSRAM_RECENT_MCUSYS_CNT CPUIDLE_SRAM_REG(0x1D4) 29 #define SYSRAM_RECENT_CNT_TS_L CPUIDLE_SRAM_REG(0x1D8) 30 #define SYSRAM_RECENT_CNT_TS_H CPUIDLE_SRAM_REG(0x1DC) 31 #define SYSRAM_CPUSYS_CNT CPUIDLE_SRAM_REG(0x1E8) 32 #define SYSRAM_MCUSYS_CNT CPUIDLE_SRAM_REG(0x1EC) 33 #define SYSRAM_CLUSTER_CNT_BACKUP CPUIDLE_SRAM_REG(0x1F0) 34 #define MCUPM_TCM_MCUSYS_COUNTER \ 35 (CPU_EB_TCM_CNT_BASE + CPU_EB_MCUSYS_CNT_OFST) 36 37 /* CPC_MCUSYS_CPC_FLOW_CTRL_CFG(0x114): debug setting */ 38 #define CPC_PWR_ON_SEQ_DIS BIT(1) 39 #define CPC_PWR_ON_PRIORITY BIT(2) 40 #define CPC_AUTO_OFF_EN BIT(5) 41 #define CPC_DORMANT_WAIT_EN BIT(14) 42 #define CPC_CTRL_EN BIT(16) 43 #define CPC_OFF_PRE_EN BIT(29) 44 45 /* CPC_MCUSYS_LAST_CORE_REQ(0x118) : last core protection */ 46 #define CPUSYS_PROT_SET BIT(0) 47 #define MCUSYS_PROT_SET BIT(8) 48 /* CPC_PWR_ON_MASK(0x128) : last core protection */ 49 #define CPUSYS_PROT_CLR BIT(8) 50 #define MCUSYS_PROT_CLR BIT(9) 51 52 #define CPC_PROT_RESP_MASK (0x3) 53 /* CPC_CPUSYS_LAST_CORE_RESP(0x11C) : last core protection */ 54 #define CPUSYS_RESP_OFS (16) 55 /* CPC_MCUSYS_LAST_CORE_RESP(0x124) : last core protection */ 56 #define MCUSYS_RESP_OFS (30) 57 58 #define RETRY_CNT_MAX (1000) 59 60 #define PROT_RETRY (0) 61 #define PROT_SUCCESS (1) 62 #define PROT_GIVEUP (2) 63 64 /* CPC_MCUSYS_CPC_DBG_SETTING(0x200): debug setting */ 65 #define CPC_PROF_EN BIT(0) 66 #define CPC_DBG_EN BIT(1) 67 #define CPC_FREEZE BIT(2) 68 #define CPC_CALC_EN BIT(3) 69 70 enum mcusys_cpc_lastcore_prot_status { 71 CPC_SUCCESS = 0, 72 CPC_ERR_FAIL, 73 CPC_ERR_TIMEOUT, 74 NF_CPC_ERR 75 }; 76 77 enum mcusys_cpc_smc_events { 78 CPC_SMC_EVENT_DUMP_TRACE_DATA, 79 CPC_SMC_EVENT_GIC_DPG_SET, 80 CPC_SMC_EVENT_CPC_CONFIG, 81 CPC_SMC_EVENT_READ_CONFIG, 82 CPC_SMC_EVENT_PROF_LATENCY, 83 NF_CPC_SMC_EVENT 84 }; 85 86 enum mcusys_cpc_smc_config { 87 CPC_SMC_CONFIG_PROF, 88 CPC_SMC_CONFIG_CNT_CLR, 89 CPC_SMC_CONFIG_TIME_SYNC, 90 91 NF_CPC_SMC_CONFIG, 92 }; 93 94 enum dev_type { 95 DEV_TYPE_CPU_0 = 0, 96 DEV_TYPE_CPUSYS = PLATFORM_CORE_COUNT, 97 DEV_TYPE_MCUSYS, 98 DEV_TYPE_NUM 99 }; 100 101 enum { 102 CPC_PROF_ENABLE, 103 CPC_PROF_ENABLED, 104 CPC_PROF_DEV_NUM, 105 CPC_PROF_DEV_NAME, 106 CPC_PROF_OFF_CNT, 107 CPC_PROF_OFF_AVG, 108 CPC_PROF_OFF_MAX, 109 CPC_PROF_OFF_MIN, 110 CPC_PROF_ON_CNT, 111 CPC_PROF_ON_AVG, 112 CPC_PROF_ON_MAX, 113 CPC_PROF_ON_MIN, 114 115 CPC_PROF_NUM 116 }; 117 118 #define MTK_CPC_AUTO_DORMANT_THR_US (8000) 119 #define US_TO_TICKS(us) ((us) * 26) 120 #define TICKS_TO_US(tick) ((tick) / 26) 121 122 int mtk_cpu_pm_cluster_prot_aquire(int cluster); 123 void mtk_cpu_pm_cluster_prot_release(int cluster); 124 125 void mtk_cpc_mcusys_off_reflect(void); 126 int mtk_cpc_mcusys_off_prepare(void); 127 128 void mtk_cpc_core_on_hint_set(int cpu); 129 void mtk_cpc_core_on_hint_clr(int cpu); 130 void mtk_cpc_time_sync(void); 131 132 uint64_t mtk_cpc_handler(uint64_t act, uint64_t arg1, uint64_t arg2); 133 uint64_t mtk_cpc_trace_dump(uint64_t act, uint64_t arg1, uint64_t arg2); 134 void mtk_cpu_pm_counter_enable(bool enable); 135 bool mtk_cpu_pm_counter_enabled(void); 136 void mtk_cpu_pm_counter_update(unsigned int cpu); 137 void mtk_cpc_prof_enable(bool enable); 138 bool mtk_cpc_prof_is_enabled(void); 139 void mtk_cpu_pm_save_cpc_latency(enum dev_type dev_type); 140 void mtk_cpc_init(void); 141 142 #endif /* MT_CPU_PM_CPC_H */ 143