1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #include <common/debug.h> 9 #include <drivers/marvell/mci.h> 10 #include <drivers/marvell/mochi/ap_setup.h> 11 #include <drivers/marvell/mochi/cp110_setup.h> 12 #include <lib/mmio.h> 13 14 #include <armada_common.h> 15 #include <marvell_plat_priv.h> 16 #include <marvell_pm.h> 17 #include <mc_trustzone/mc_trustzone.h> 18 #include <plat_marvell.h> 19 #if MSS_SUPPORT 20 #include <mss_ipc_drv.h> 21 #include <mss_mem.h> 22 #include <mss_defs.h> 23 #endif 24 25 /* In Armada-8k family AP806/AP807, CP0 connected to PIDI 26 * and CP1 connected to IHB via MCI #0 27 */ 28 #define MVEBU_MCI0 0 29 30 static _Bool pm_fw_running; 31 32 /* Set a weak stub for platforms that don't need to configure GPIO */ 33 #pragma weak marvell_gpio_config 34 int marvell_gpio_config(void) 35 { 36 return 0; 37 } 38 39 static void marvell_bl31_mpp_init(int cp) 40 { 41 uint32_t reg; 42 43 /* need to do for CP#0 only */ 44 if (cp) 45 return; 46 47 48 /* 49 * Enable CP0 I2C MPPs (MPP: 37-38) 50 * U-Boot rely on proper MPP settings for I2C EEPROM usage 51 * (only for CP0) 52 */ 53 reg = mmio_read_32(MVEBU_CP_MPP_REGS(0, 4)); 54 mmio_write_32(MVEBU_CP_MPP_REGS(0, 4), reg | 0x2200000); 55 } 56 57 #if MSS_SUPPORT 58 void marvell_bl31_mss_init(void) 59 { 60 struct mss_pm_ctrl_block *mss_pm_crtl = 61 (struct mss_pm_ctrl_block *)MSS_SRAM_PM_CONTROL_BASE; 62 63 /* Check that the image was loaded successfully */ 64 if (mss_pm_crtl->handshake != HOST_ACKNOWLEDGMENT) { 65 NOTICE("MSS PM is not supported in this build\n"); 66 return; 67 } 68 69 /* If we got here it means that the PM firmware is running */ 70 pm_fw_running = 1; 71 72 INFO("MSS IPC init\n"); 73 74 if (mss_pm_crtl->ipc_state == IPC_INITIALIZED) 75 mv_pm_ipc_init(mss_pm_crtl->ipc_base_address | MVEBU_REGS_BASE); 76 } 77 #endif 78 79 _Bool is_pm_fw_running(void) 80 { 81 return pm_fw_running; 82 } 83 84 /* For TrusTzone we treat the "target" field of addr_map_win 85 * struct as attribute 86 */ 87 static const struct addr_map_win tz_map[] = { 88 {PLAT_MARVELL_ATF_BASE, 0x200000, TZ_PERM_ABORT} 89 }; 90 91 /* Configure MC TrustZone regions */ 92 static void marvell_bl31_security_setup(void) 93 { 94 int tz_nr, win_id; 95 96 tz_nr = ARRAY_SIZE(tz_map); 97 98 for (win_id = 0; win_id < tz_nr; win_id++) 99 tz_enable_win(MVEBU_AP0, tz_map, win_id); 100 } 101 102 /* This function overruns the same function in marvell_bl31_setup.c */ 103 void bl31_plat_arch_setup(void) 104 { 105 int cp; 106 uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE; 107 108 /* initialize the timer for mdelay/udelay functionality */ 109 plat_delay_timer_init(); 110 111 /* configure apn806 */ 112 ap_init(); 113 114 /* In marvell_bl31_plat_arch_setup, el3 mmu is configured. 115 * el3 mmu configuration MUST be called after apn806_init, if not, 116 * this will cause an hang in init_io_win 117 * (after setting the IO windows GCR values). 118 */ 119 if (mailbox[MBOX_IDX_MAGIC] != MVEBU_MAILBOX_MAGIC_NUM || 120 mailbox[MBOX_IDX_SUSPEND_MAGIC] != MVEBU_MAILBOX_SUSPEND_STATE) 121 marvell_bl31_plat_arch_setup(); 122 123 for (cp = 0; cp < CP_COUNT; cp++) { 124 cp110_init(MVEBU_CP_REGS_BASE(cp), 125 STREAM_ID_BASE + (cp * MAX_STREAM_ID_PER_CP)); 126 127 marvell_bl31_mpp_init(cp); 128 129 #if MSS_SUPPORT 130 /* Release CP MSS CPU from reset once the CP init is done */ 131 mss_start_cp_cm3(cp); 132 #endif 133 } 134 135 for (cp = 1; cp < CP_COUNT; cp++) 136 mci_link_tune(cp - 1); 137 138 #if MSS_SUPPORT 139 /* initialize IPC between MSS and ATF */ 140 if (mailbox[MBOX_IDX_MAGIC] != MVEBU_MAILBOX_MAGIC_NUM || 141 mailbox[MBOX_IDX_SUSPEND_MAGIC] != MVEBU_MAILBOX_SUSPEND_STATE) 142 marvell_bl31_mss_init(); 143 #endif 144 /* Configure GPIO */ 145 marvell_gpio_config(); 146 147 marvell_bl31_security_setup(); 148 } 149