1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #include <arch_helpers.h> 9 #include <common/debug.h> 10 11 #include <mv_ddr_if.h> 12 #include <plat_marvell.h> 13 14 /* 15 * This function may modify the default DRAM parameters 16 * based on information received from SPD or bootloader 17 * configuration located on non volatile storage 18 */ 19 void plat_marvell_dram_update_topology(void) 20 { 21 } 22 23 /* 24 * This struct provides the DRAM training code with 25 * the appropriate board DRAM configuration 26 */ 27 static struct mv_ddr_topology_map board_topology_map = { 28 /* FIXME: MISL board 2CS 4Gb x8 devices of micron - 2133P */ 29 DEBUG_LEVEL_ERROR, 30 0x1, /* active interfaces */ 31 /* cs_mask, mirror, dqs_swap, ck_swap X subphys */ 32 { { { {0x3, 0x2, 0, 0}, 33 {0x3, 0x2, 0, 0}, 34 {0x3, 0x2, 0, 0}, 35 {0x3, 0x2, 0, 0}, 36 {0x3, 0x2, 0, 0}, 37 {0x3, 0x2, 0, 0}, 38 {0x3, 0x2, 0, 0}, 39 {0x3, 0x2, 0, 0}, 40 {0x3, 0x2, 0, 0} }, 41 SPEED_BIN_DDR_2133P, /* speed_bin */ 42 MV_DDR_DEV_WIDTH_8BIT, /* sdram device width */ 43 MV_DDR_DIE_CAP_4GBIT, /* die capacity */ 44 MV_DDR_FREQ_SAR, /* frequency */ 45 0, 0, /* cas_l, cas_wl */ 46 MV_DDR_TEMP_LOW} }, /* temperature */ 47 MV_DDR_32BIT_ECC_PUP8_BUS_MASK, /* subphys mask */ 48 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ 49 { {0} }, /* raw spd data */ 50 {0}, /* timing parameters */ 51 { /* electrical configuration */ 52 { /* memory electrical configuration */ 53 MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ 54 { 55 MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ 56 MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ 57 }, 58 { 59 MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ 60 MV_DDR_RTT_WR_RZQ_DIV2 /* rtt_wr 2cs */ 61 }, 62 MV_DDR_DIC_RZQ_DIV7 /* dic */ 63 }, 64 { /* phy electrical configuration */ 65 MV_DDR_OHM_30, /* data_drv_p */ 66 MV_DDR_OHM_30, /* data_drv_n */ 67 MV_DDR_OHM_30, /* ctrl_drv_p */ 68 MV_DDR_OHM_30, /* ctrl_drv_n */ 69 { 70 MV_DDR_OHM_60, /* odt_p 1cs */ 71 MV_DDR_OHM_120 /* odt_p 2cs */ 72 }, 73 { 74 MV_DDR_OHM_60, /* odt_n 1cs */ 75 MV_DDR_OHM_120 /* odt_n 2cs */ 76 }, 77 }, 78 { /* mac electrical configuration */ 79 MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ 80 MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ 81 MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ 82 }, 83 } 84 }; 85 86 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) 87 { 88 /* Return the board topology as defined in the board code */ 89 return &board_topology_map; 90 } 91