1 /* 2 * Copyright (c) 2019, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #define S10_FIREWALL_SOC2FPGA 0xffd21200 8 #define S10_FIREWALL_LWSOC2FPGA 0xffd21300 9 10 /* L3 Interconnect Register Map */ 11 #define S10_NOC_FW_L4_PER_SCR_NAND_REGISTER 0xffd21000 12 #define S10_NOC_FW_L4_PER_SCR_NAND_DATA 0xffd21004 13 #define S10_NOC_FW_L4_PER_SCR_USB0_REGISTER 0xffd2100c 14 #define S10_NOC_FW_L4_PER_SCR_USB1_REGISTER 0xffd21010 15 #define S10_NOC_FW_L4_PER_SCR_SPI_MASTER0 0xffd2101c 16 #define S10_NOC_FW_L4_PER_SCR_SPI_MASTER1 0xffd21020 17 #define S10_NOC_FW_L4_PER_SCR_SPI_SLAVE0 0xffd21024 18 #define S10_NOC_FW_L4_PER_SCR_SPI_SLAVE1 0xffd21028 19 #define S10_NOC_FW_L4_PER_SCR_EMAC0 0xffd2102c 20 #define S10_NOC_FW_L4_PER_SCR_EMAC1 0xffd21030 21 #define S10_NOC_FW_L4_PER_SCR_EMAC2 0xffd21034 22 #define S10_NOC_FW_L4_PER_SCR_SDMMC 0xffd21040 23 #define S10_NOC_FW_L4_PER_SCR_GPIO0 0xffd21044 24 #define S10_NOC_FW_L4_PER_SCR_GPIO1 0xffd21048 25 #define S10_NOC_FW_L4_PER_SCR_I2C0 0xffd21050 26 #define S10_NOC_FW_L4_PER_SCR_I2C1 0xffd21054 27 #define S10_NOC_FW_L4_PER_SCR_I2C2 0xffd21058 28 #define S10_NOC_FW_L4_PER_SCR_I2C3 0xffd2105c 29 #define S10_NOC_FW_L4_PER_SCR_I2C4 0xffd21060 30 #define S10_NOC_FW_L4_PER_SCR_SP_TIMER0 0xffd21064 31 #define S10_NOC_FW_L4_PER_SCR_SP_TIMER1 0xffd21068 32 #define S10_NOC_FW_L4_PER_SCR_UART0 0xffd2106c 33 #define S10_NOC_FW_L4_PER_SCR_UART1 0xffd21070 34 35 #define S10_NOC_FW_L4_SYS_SCR_DMA_ECC 0xffd21108 36 #define S10_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC 0xffd2110c 37 #define S10_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC 0xffd21110 38 #define S10_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC 0xffd21114 39 #define S10_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC 0xffd21118 40 #define S10_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC 0xffd2111c 41 #define S10_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC 0xffd21120 42 #define S10_NOC_FW_L4_SYS_SCR_NAND_ECC 0xffd2112c 43 #define S10_NOC_FW_L4_SYS_SCR_NAND_READ_ECC 0xffd21130 44 #define S10_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC 0xffd21134 45 #define S10_NOC_FW_L4_SYS_SCR_OCRAM_ECC 0xffd21138 46 #define S10_NOC_FW_L4_SYS_SCR_SDMMC_ECC 0xffd21140 47 #define S10_NOC_FW_L4_SYS_SCR_USB0_ECC 0xffd21144 48 #define S10_NOC_FW_L4_SYS_SCR_USB1_ECC 0xffd21148 49 #define S10_NOC_FW_L4_SYS_SCR_CLK_MGR 0xffd2114c 50 #define S10_NOC_FW_L4_SYS_SCR_IO_MGR 0xffd21154 51 #define S10_NOC_FW_L4_SYS_SCR_RST_MGR 0xffd21158 52 #define S10_NOC_FW_L4_SYS_SCR_SYS_MGR 0xffd2115c 53 #define S10_NOC_FW_L4_SYS_SCR_OSC0_TIMER 0xffd21160 54 #define S10_NOC_FW_L4_SYS_SCR_OSC1_TIMER 0xffd21164 55 #define S10_NOC_FW_L4_SYS_SCR_WATCHDOG0 0xffd21168 56 #define S10_NOC_FW_L4_SYS_SCR_WATCHDOG1 0xffd2116c 57 #define S10_NOC_FW_L4_SYS_SCR_WATCHDOG2 0xffd21170 58 #define S10_NOC_FW_L4_SYS_SCR_WATCHDOG3 0xffd21174 59 #define S10_NOC_FW_L4_SYS_SCR_DAP 0xffd21178 60 #define S10_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES 0xffd21190 61 #define S10_NOC_FW_L4_SYS_SCR_L4_NOC_QOS 0xffd21194 62 63 #define S10_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688 64 #define S10_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628 65 66 /* System Manager Register Map */ 67 #define S10_SYSMGR_CORE(x) (0xffd12000 + (x)) 68 69 #define SYSMGR_MMC 0x28 70 #define SYSMGR_MMC_DRVSEL(x) (((x) & 0x7) << 0) 71 72 #define SYSMGR_NOC_TIMEOUT 0xc0 73 #define SYSMGR_NOC_IDLEREQ_SET 0xc4 74 #define SYSMGR_NOC_IDLEREQ_CLR 0xc8 75 #define SYSMGR_NOC_IDLEREQ_VAL 0xcc 76 #define SYSMGR_NOC_IDLEACK 0xd0 77 #define SYSMGR_NOC_IDLESTATUS 0xd4 78 79 #define IDLE_DATA_LWSOC2FPGA BIT(0) 80 #define IDLE_DATA_SOC2FPGA BIT(4) 81 #define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA) 82 83 #define SYSMGR_BOOT_SCRATCH_COLD_0 0x200 84 #define SYSMGR_BOOT_SCRATCH_COLD_1 0x204 85 #define SYSMGR_BOOT_SCRATCH_COLD_2 0x208 86 87 #define DISABLE_BRIDGE_FIREWALL 0x0ffe0101 88 #define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24)) 89 90 void enable_nonsecure_access(void); 91 void enable_ns_peripheral_access(void); 92 void enable_ns_bridge_access(void); 93