1 /* 2 * Copyright (c) 2019, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __S10_MEMORYCONTROLLER_H__ 8 #define __S10_MEMORYCONTROLLER_H__ 9 10 #define S10_MPFE_IOHMC_REG_DRAMADDRW 0xf80100a8 11 #define S10_MPFE_IOHMC_CTRLCFG0 0xf8010028 12 #define S10_MPFE_IOHMC_CTRLCFG1 0xf801002c 13 #define S10_MPFE_IOHMC_DRAMADDRW 0xf80100a8 14 #define S10_MPFE_IOHMC_DRAMTIMING0 0xf8010050 15 #define S10_MPFE_IOHMC_CALTIMING0 0xf801007c 16 #define S10_MPFE_IOHMC_CALTIMING1 0xf8010080 17 #define S10_MPFE_IOHMC_CALTIMING2 0xf8010084 18 #define S10_MPFE_IOHMC_CALTIMING3 0xf8010088 19 #define S10_MPFE_IOHMC_CALTIMING4 0xf801008c 20 #define S10_MPFE_IOHMC_CALTIMING9 0xf80100a0 21 #define S10_MPFE_IOHMC_CALTIMING9_ACT_TO_ACT(x) (((x) & 0x000000ff) >> 0) 22 #define S10_MPFE_IOHMC_CTRLCFG1_CFG_ADDR_ORDER(value) \ 23 (((value) & 0x00000060) >> 5) 24 25 #define S10_RSTMGR_BRGMODRST 0xffd1102c 26 #define S10_RSTMGR_BRGMODRST_DDRSCH 0x00000040 27 28 #define S10_MPFE_HMC_ADP_ECCCTRL1 0xf8011100 29 #define S10_MPFE_HMC_ADP_ECCCTRL2 0xf8011104 30 #define S10_MPFE_HMC_ADP_RSTHANDSHAKESTAT 0xf8011218 31 #define S10_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE 0x000000ff 32 #define S10_MPFE_HMC_ADP_RSTHANDSHAKECTRL 0xf8011214 33 34 35 #define S10_MPFE_IOHMC_REG_CTRLCFG1 0xf801002c 36 37 #define S10_MPFE_IOHMC_REG_NIOSRESERVE0_OFST 0xf8010110 38 39 #define IOHMC_DRAMADDRW_COL_ADDR_WIDTH(x) (((x) & 0x0000001f) >> 0) 40 #define IOHMC_DRAMADDRW_ROW_ADDR_WIDTH(x) (((x) & 0x000003e0) >> 5) 41 #define IOHMC_DRAMADDRW_CS_ADDR_WIDTH(x) (((x) & 0x00070000) >> 16) 42 #define IOHMC_DRAMADDRW_BANK_GRP_ADDR_WIDTH(x) (((x) & 0x0000c000) >> 14) 43 #define IOHMC_DRAMADDRW_BANK_ADDR_WIDTH(x) (((x) & 0x00003c00) >> 10) 44 45 #define S10_MPFE_DDR(x) (0xf8000000 + x) 46 #define S10_MPFE_HMC_ADP_DDRCALSTAT 0xf801100c 47 #define S10_MPFE_DDR_MAIN_SCHED 0xf8000400 48 #define S10_MPFE_DDR_MAIN_SCHED_DDRCONF 0xf8000408 49 #define S10_MPFE_DDR_MAIN_SCHED_DDRTIMING 0xf800040c 50 #define S10_MPFE_DDR_MAIN_SCHED_DDRCONF_SET_MSK 0x0000001f 51 #define S10_MPFE_DDR_MAIN_SCHED_DDRMODE 0xf8000410 52 #define S10_MPFE_DDR_MAIN_SCHED_DEVTODEV 0xf800043c 53 #define S10_MPFE_DDR_MAIN_SCHED_READLATENCY 0xf8000414 54 #define S10_MPFE_DDR_MAIN_SCHED_ACTIVATE 0xf8000438 55 #define S10_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAWBANK_OFST 10 56 #define S10_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAW_OFST 4 57 #define S10_MPFE_DDR_MAIN_SCHED_ACTIVATE_RRD_OFST 0 58 #define S10_MPFE_DDR_MAIN_SCHED_DDRCONF_SET(x) (((x) << 0) & 0x0000001f) 59 #define S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTORD_OFST 0 60 #define S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTORD_MSK (BIT(0) | BIT(1)) 61 #define S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTOWR_OFST 2 62 #define S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTOWR_MSK (BIT(2) | BIT(3)) 63 #define S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSWRTORD_OFST 4 64 #define S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSWRTORD_MSK (BIT(4) | BIT(5)) 65 66 #define S10_MPFE_HMC_ADP(x) (0xf8011000 + (x)) 67 #define S10_MPFE_HMC_ADP_HPSINTFCSEL 0xf8011210 68 #define S10_MPFE_HMC_ADP_DDRIOCTRL 0xf8011008 69 #define HMC_ADP_DDRIOCTRL 0x8 70 #define HMC_ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x00000003) >> 0) 71 #define HMC_ADP_DDRIOCTRL_CTRL_BURST_LENGTH(x) (((x) & 0x00003e00) >> 9) 72 #define ADP_DRAMADDRWIDTH 0xe0 73 74 #define ACT_TO_ACT_DIFF_BANK(value) (((value) & 0x00fc0000) >> 18) 75 #define ACT_TO_ACT(value) (((value) & 0x0003f000) >> 12) 76 #define ACT_TO_RDWR(value) (((value) & 0x0000003f) >> 0) 77 #define ACT_TO_ACT(value) (((value) & 0x0003f000) >> 12) 78 79 /* timing 2 */ 80 #define RD_TO_RD_DIFF_CHIP(value) (((value) & 0x00000fc0) >> 6) 81 #define RD_TO_WR_DIFF_CHIP(value) (((value) & 0x3f000000) >> 24) 82 #define RD_TO_WR(value) (((value) & 0x00fc0000) >> 18) 83 #define RD_TO_PCH(value) (((value) & 0x00000fc0) >> 6) 84 85 /* timing 3 */ 86 #define CALTIMING3_WR_TO_RD_DIFF_CHIP(value) (((value) & 0x0003f000) >> 12) 87 #define CALTIMING3_WR_TO_RD(value) (((value) & 0x00000fc0) >> 6) 88 89 /* timing 4 */ 90 #define PCH_TO_VALID(value) (((value) & 0x00000fc0) >> 6) 91 92 #define DDRTIMING_BWRATIO_OFST 31 93 #define DDRTIMING_WRTORD_OFST 26 94 #define DDRTIMING_RDTOWR_OFST 21 95 #define DDRTIMING_BURSTLEN_OFST 18 96 #define DDRTIMING_WRTOMISS_OFST 12 97 #define DDRTIMING_RDTOMISS_OFST 6 98 #define DDRTIMING_ACTTOACT_OFST 0 99 100 #define ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x00000003) >> 0) 101 102 #define DDRMODE_AUTOPRECHARGE_OFST 1 103 #define DDRMODE_BWRATIOEXTENDED_OFST 0 104 105 106 #define S10_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL(x) (((x) & 0x0000007f) >> 0) 107 #define S10_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE(x) (((x) & 0x0000000f) >> 0) 108 109 #define S10_CCU_CPU0_MPRT_DDR 0xf7004400 110 #define S10_CCU_CPU0_MPRT_MEM0 0xf70045c0 111 #define S10_CCU_CPU0_MPRT_MEM1A 0xf70045e0 112 #define S10_CCU_CPU0_MPRT_MEM1B 0xf7004600 113 #define S10_CCU_CPU0_MPRT_MEM1C 0xf7004620 114 #define S10_CCU_CPU0_MPRT_MEM1D 0xf7004640 115 #define S10_CCU_CPU0_MPRT_MEM1E 0xf7004660 116 #define S10_CCU_IOM_MPRT_MEM0 0xf7018560 117 #define S10_CCU_IOM_MPRT_MEM1A 0xf7018580 118 #define S10_CCU_IOM_MPRT_MEM1B 0xf70185a0 119 #define S10_CCU_IOM_MPRT_MEM1C 0xf70185c0 120 #define S10_CCU_IOM_MPRT_MEM1D 0xf70185e0 121 #define S10_CCU_IOM_MPRT_MEM1E 0xf7018600 122 123 #define S10_NOC_FW_DDR_SCR 0xf8020100 124 #define S10_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT 0xf802011c 125 #define S10_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT 0xf8020118 126 #define S10_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0xf802019c 127 #define S10_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0xf8020198 128 129 #define S10_SOC_NOC_FW_DDR_SCR_ENABLE 0xf8020100 130 #define S10_CCU_NOC_DI_SET_MSK 0x10 131 132 #define S10_SYSMGR_CORE_HMC_CLK 0xffd120b4 133 #define S10_SYSMGR_CORE_HMC_CLK_STATUS 0x00000001 134 135 #define S10_MPFE_IOHMC_NIOSRESERVE0_NIOS_RESERVE0(x) (((x) & 0x0000ffff) >> 0) 136 #define S10_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_MSK 0x00000003 137 #define S10_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_OFST 0 138 #define S10_MPFE_HMC_ADP_HPSINTFCSEL_ENABLE 0x001f1f1f 139 #define S10_IOHMC_CTRLCFG1_ENABLE_ECC_OFST 7 140 141 #define S10_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_SET_MSK 0x00010000 142 #define S10_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_SET_MSK 0x00000100 143 #define S10_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_SET_MSK 0x00000001 144 145 #define S10_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_SET_MSK 0x00000001 146 #define S10_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_SET_MSK 0x00010000 147 #define S10_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_SET_MSK 0x00000100 148 #define S10_MPFE_HMC_ADP_DDRCALSTAT_CAL(value) (((value) & 0x00000001) >> 0) 149 150 151 #define S10_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x00000003) >> 0) 152 #define IOHMC_DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) (((x) & 0x00003c00) >> 10) 153 #define IOHMC_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH(x) (((x) & 0x0000c000) >> 14) 154 #define IOHMC_DRAMADDRW_CFG_COL_ADDR_WIDTH(x) (((x) & 0x0000001f) >> 0) 155 #define IOHMC_DRAMADDRW_CFG_CS_ADDR_WIDTH(x) (((x) & 0x00070000) >> 16) 156 #define IOHMC_DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) (((x) & 0x000003e0) >> 5) 157 158 #define S10_SDRAM_0_LB_ADDR 0x0 159 160 int init_hard_memory_controller(void); 161 162 #endif 163