1 /* 2 * Copyright (c) 2020-2022, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <arch.h> 9 #include <arch_helpers.h> 10 #include <common/bl_common.h> 11 #include <drivers/arm/gicv2.h> 12 #include <drivers/ti/uart/uart_16550.h> 13 #include <lib/mmio.h> 14 #include <lib/xlat_tables/xlat_tables.h> 15 16 #include "ccu/ncore_ccu.h" 17 #include "socfpga_mailbox.h" 18 #include "socfpga_private.h" 19 20 static entry_point_info_t bl32_image_ep_info; 21 static entry_point_info_t bl33_image_ep_info; 22 23 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 24 { 25 entry_point_info_t *next_image_info; 26 27 next_image_info = (type == NON_SECURE) ? 28 &bl33_image_ep_info : &bl32_image_ep_info; 29 30 /* None of the images on this platform can have 0x0 as the entrypoint */ 31 if (next_image_info->pc) { 32 return next_image_info; 33 } else { 34 return NULL; 35 } 36 } 37 38 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 39 u_register_t arg2, u_register_t arg3) 40 { 41 static console_t console; 42 43 mmio_write_64(PLAT_SEC_ENTRY, 0); 44 45 console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK, 46 PLAT_BAUDRATE, &console); 47 /* 48 * Check params passed from BL31 should not be NULL, 49 */ 50 void *from_bl2 = (void *) arg0; 51 52 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 53 54 assert(params_from_bl2 != NULL); 55 56 /* 57 * Copy BL32 (if populated by BL31) and BL33 entry point information. 58 * They are stored in Secure RAM, in BL31's address space. 59 */ 60 61 if (params_from_bl2->h.type == PARAM_BL_PARAMS && 62 params_from_bl2->h.version >= VERSION_2) { 63 64 bl_params_node_t *bl_params = params_from_bl2->head; 65 66 while (bl_params != NULL) { 67 if (bl_params->image_id == BL33_IMAGE_ID) 68 bl33_image_ep_info = *bl_params->ep_info; 69 70 bl_params = bl_params->next_params_info; 71 } 72 } else { 73 struct socfpga_bl31_params *arg_from_bl2 = 74 (struct socfpga_bl31_params *) from_bl2; 75 76 assert(arg_from_bl2->h.type == PARAM_BL31); 77 assert(arg_from_bl2->h.version >= VERSION_1); 78 79 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info; 80 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info; 81 } 82 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 83 } 84 85 static const interrupt_prop_t s10_interrupt_props[] = { 86 PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), 87 PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0) 88 }; 89 90 static unsigned int target_mask_array[PLATFORM_CORE_COUNT]; 91 92 static const gicv2_driver_data_t plat_gicv2_gic_data = { 93 .gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE, 94 .gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE, 95 .interrupt_props = s10_interrupt_props, 96 .interrupt_props_num = ARRAY_SIZE(s10_interrupt_props), 97 .target_masks = target_mask_array, 98 .target_masks_num = ARRAY_SIZE(target_mask_array), 99 }; 100 101 /******************************************************************************* 102 * Perform any BL3-1 platform setup code 103 ******************************************************************************/ 104 void bl31_platform_setup(void) 105 { 106 socfpga_delay_timer_init(); 107 108 /* Initialize the gic cpu and distributor interfaces */ 109 gicv2_driver_init(&plat_gicv2_gic_data); 110 gicv2_distif_init(); 111 gicv2_pcpu_distif_init(); 112 gicv2_cpuif_enable(); 113 114 /* Signal secondary CPUs to jump to BL31 (BL2 = U-boot SPL) */ 115 mmio_write_64(PLAT_CPU_RELEASE_ADDR, 116 (uint64_t)plat_secondary_cpus_bl31_entry); 117 118 mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL); 119 120 ncore_enable_ocram_firewall(); 121 } 122 123 const mmap_region_t plat_dm_mmap[] = { 124 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, 125 MT_MEMORY | MT_RW | MT_NS), 126 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, 127 MT_DEVICE | MT_RW | MT_NS), 128 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, 129 MT_DEVICE | MT_RW | MT_SECURE), 130 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, 131 MT_NON_CACHEABLE | MT_RW | MT_SECURE), 132 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE, 133 MT_DEVICE | MT_RW | MT_SECURE), 134 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, 135 MT_DEVICE | MT_RW | MT_NS), 136 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, 137 MT_DEVICE | MT_RW | MT_NS), 138 {0} 139 }; 140 141 /******************************************************************************* 142 * Perform the very early platform specific architectural setup here. At the 143 * moment this is only initializes the mmu in a quick and dirty way. 144 ******************************************************************************/ 145 void bl31_plat_arch_setup(void) 146 { 147 const mmap_region_t bl_regions[] = { 148 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 149 MT_MEMORY | MT_RW | MT_SECURE), 150 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 151 MT_CODE | MT_SECURE), 152 MAP_REGION_FLAT(BL_RO_DATA_BASE, 153 BL_RO_DATA_END - BL_RO_DATA_BASE, 154 MT_RO_DATA | MT_SECURE), 155 #if USE_COHERENT_MEM 156 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 157 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 158 MT_DEVICE | MT_RW | MT_SECURE), 159 #endif 160 {0} 161 }; 162 163 setup_page_tables(bl_regions, plat_dm_mmap); 164 enable_mmu_el3(0); 165 } 166