1d8820789SHadi Asyrafi /* 2d8820789SHadi Asyrafi * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3d8820789SHadi Asyrafi * 4d8820789SHadi Asyrafi * SPDX-License-Identifier: BSD-3-Clause 5d8820789SHadi Asyrafi */ 6d8820789SHadi Asyrafi 7d8820789SHadi Asyrafi #include <assert.h> 8d8820789SHadi Asyrafi #include <arch_helpers.h> 9d8820789SHadi Asyrafi #include <drivers/delay_timer.h> 10d8820789SHadi Asyrafi #include <lib/mmio.h> 11d8820789SHadi Asyrafi 12d8820789SHadi Asyrafi #define SOCFPGA_GLOBAL_TIMER 0xffd01000 13d8820789SHadi Asyrafi #define SOCFPGA_GLOBAL_TIMER_EN 0x3 14d8820789SHadi Asyrafi 15d8820789SHadi Asyrafi /******************************************************************** 16d8820789SHadi Asyrafi * The timer delay function 17d8820789SHadi Asyrafi ********************************************************************/ 18d8820789SHadi Asyrafi static uint32_t socfpga_get_timer_value(void) 19d8820789SHadi Asyrafi { 20d8820789SHadi Asyrafi /* 21d8820789SHadi Asyrafi * Generic delay timer implementation expects the timer to be a down 22d8820789SHadi Asyrafi * counter. We apply bitwise NOT operator to the tick values returned 23d8820789SHadi Asyrafi * by read_cntpct_el0() to simulate the down counter. The value is 24d8820789SHadi Asyrafi * clipped from 64 to 32 bits. 25d8820789SHadi Asyrafi */ 26d8820789SHadi Asyrafi return (uint32_t)(~read_cntpct_el0()); 27d8820789SHadi Asyrafi } 28d8820789SHadi Asyrafi 29d8820789SHadi Asyrafi static const timer_ops_t plat_timer_ops = { 30d8820789SHadi Asyrafi .get_timer_value = socfpga_get_timer_value, 31d8820789SHadi Asyrafi .clk_mult = 1, 32d8820789SHadi Asyrafi .clk_div = PLAT_SYS_COUNTER_FREQ_IN_MHZ, 33d8820789SHadi Asyrafi }; 34d8820789SHadi Asyrafi 35d8820789SHadi Asyrafi void socfpga_delay_timer_init(void) 36d8820789SHadi Asyrafi { 37d8820789SHadi Asyrafi timer_init(&plat_timer_ops); 38d8820789SHadi Asyrafi mmio_write_32(SOCFPGA_GLOBAL_TIMER, SOCFPGA_GLOBAL_TIMER_EN); 39*811af8b7STien Hock Loh 40*811af8b7STien Hock Loh asm volatile("msr cntp_ctl_el0, %0" : : "r" (SOCFPGA_GLOBAL_TIMER_EN)); 41*811af8b7STien Hock Loh asm volatile("msr cntp_tval_el0, %0" : : "r" (~0)); 42*811af8b7STien Hock Loh 43d8820789SHadi Asyrafi } 44