1 /* 2 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SOCFPGA_PRIVATE_H 8 #define SOCFPGA_PRIVATE_H 9 10 11 #define EMMC_DESC_SIZE (1<<20) 12 13 #define EMMC_INIT_PARAMS(base, clk) \ 14 { .bus_width = MMC_BUS_WIDTH_4, \ 15 .clk_rate = (clk), \ 16 .desc_base = (base), \ 17 .desc_size = EMMC_DESC_SIZE, \ 18 .flags = 0, \ 19 .reg_base = SOCFPGA_MMC_REG_BASE \ 20 } 21 22 typedef enum { 23 BOOT_SOURCE_FPGA = 0, 24 BOOT_SOURCE_SDMMC, 25 BOOT_SOURCE_NAND, 26 BOOT_SOURCE_RSVD, 27 BOOT_SOURCE_QSPI 28 } boot_source_type; 29 30 /******************************************************************************* 31 * Function and variable prototypes 32 ******************************************************************************/ 33 34 void enable_nonsecure_access(void); 35 36 void socfpga_io_setup(int boot_source, unsigned long offset); 37 38 void socfgpa_configure_mmu_el3(unsigned long total_base, 39 unsigned long total_size, 40 unsigned long ro_start, 41 unsigned long ro_limit, 42 unsigned long coh_start, 43 unsigned long coh_limit); 44 45 46 void socfpga_configure_mmu_el1(unsigned long total_base, 47 unsigned long total_size, 48 unsigned long ro_start, 49 unsigned long ro_limit, 50 unsigned long coh_start, 51 unsigned long coh_limit); 52 53 void socfpga_delay_timer_init(void); 54 55 void socfpga_gic_driver_init(void); 56 57 void socfpga_delay_timer_init_args(void); 58 59 uint32_t socfpga_get_spsr_for_bl32_entry(void); 60 61 uint32_t socfpga_get_spsr_for_bl33_entry(void); 62 63 unsigned long socfpga_get_ns_image_entrypoint(void); 64 65 void plat_secondary_cpus_bl31_entry(void); 66 67 #endif /* SOCFPGA_PRIVATE_H */ 68