13f7b1490SHadi Asyrafi /* 2*f65bdf3aSBenjaminLimJL * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. 33f7b1490SHadi Asyrafi * 43f7b1490SHadi Asyrafi * SPDX-License-Identifier: BSD-3-Clause 53f7b1490SHadi Asyrafi */ 63f7b1490SHadi Asyrafi 7e9b5e360SHadi Asyrafi #ifndef SOCFPGA_PRIVATE_H 8e9b5e360SHadi Asyrafi #define SOCFPGA_PRIVATE_H 9e9b5e360SHadi Asyrafi 10e9b5e360SHadi Asyrafi #include "socfpga_plat_def.h" 11e9b5e360SHadi Asyrafi 12e9b5e360SHadi Asyrafi #define EMMC_DESC_SIZE (1<<20) 13e9b5e360SHadi Asyrafi 14e9b5e360SHadi Asyrafi #define EMMC_INIT_PARAMS(base, clk) \ 15e9b5e360SHadi Asyrafi { .bus_width = MMC_BUS_WIDTH_4, \ 16e9b5e360SHadi Asyrafi .clk_rate = (clk), \ 17e9b5e360SHadi Asyrafi .desc_base = (base), \ 18e9b5e360SHadi Asyrafi .desc_size = EMMC_DESC_SIZE, \ 19e9b5e360SHadi Asyrafi .flags = 0, \ 20e9b5e360SHadi Asyrafi .reg_base = SOCFPGA_MMC_REG_BASE \ 21e9b5e360SHadi Asyrafi } 22e9b5e360SHadi Asyrafi 23e9b5e360SHadi Asyrafi typedef enum { 24e9b5e360SHadi Asyrafi BOOT_SOURCE_FPGA = 0, 25e9b5e360SHadi Asyrafi BOOT_SOURCE_SDMMC, 26e9b5e360SHadi Asyrafi BOOT_SOURCE_NAND, 27e9b5e360SHadi Asyrafi BOOT_SOURCE_RSVD, 28e9b5e360SHadi Asyrafi BOOT_SOURCE_QSPI 29e9b5e360SHadi Asyrafi } boot_source_type; 303f7b1490SHadi Asyrafi 313f7b1490SHadi Asyrafi /******************************************************************************* 323f7b1490SHadi Asyrafi * Function and variable prototypes 333f7b1490SHadi Asyrafi ******************************************************************************/ 34e9b5e360SHadi Asyrafi 35e9b5e360SHadi Asyrafi void enable_nonsecure_access(void); 36e9b5e360SHadi Asyrafi 37e9b5e360SHadi Asyrafi void socfpga_io_setup(int boot_source); 38e9b5e360SHadi Asyrafi 393f7b1490SHadi Asyrafi void socfgpa_configure_mmu_el3(unsigned long total_base, 403f7b1490SHadi Asyrafi unsigned long total_size, 413f7b1490SHadi Asyrafi unsigned long ro_start, 423f7b1490SHadi Asyrafi unsigned long ro_limit, 433f7b1490SHadi Asyrafi unsigned long coh_start, 443f7b1490SHadi Asyrafi unsigned long coh_limit); 453f7b1490SHadi Asyrafi 463f7b1490SHadi Asyrafi 473f7b1490SHadi Asyrafi void socfpga_configure_mmu_el1(unsigned long total_base, 483f7b1490SHadi Asyrafi unsigned long total_size, 493f7b1490SHadi Asyrafi unsigned long ro_start, 503f7b1490SHadi Asyrafi unsigned long ro_limit, 513f7b1490SHadi Asyrafi unsigned long coh_start, 523f7b1490SHadi Asyrafi unsigned long coh_limit); 533f7b1490SHadi Asyrafi 543f7b1490SHadi Asyrafi void socfpga_delay_timer_init(void); 553f7b1490SHadi Asyrafi 563f7b1490SHadi Asyrafi void socfpga_gic_driver_init(void); 573f7b1490SHadi Asyrafi 58*f65bdf3aSBenjaminLimJL void socfpga_delay_timer_init_args(void); 59*f65bdf3aSBenjaminLimJL 603f7b1490SHadi Asyrafi uint32_t socfpga_get_spsr_for_bl32_entry(void); 613f7b1490SHadi Asyrafi 623f7b1490SHadi Asyrafi uint32_t socfpga_get_spsr_for_bl33_entry(void); 633f7b1490SHadi Asyrafi 643f7b1490SHadi Asyrafi unsigned long socfpga_get_ns_image_entrypoint(void); 653f7b1490SHadi Asyrafi 662db1e766SHadi Asyrafi void plat_secondary_cpus_bl31_entry(void); 673f7b1490SHadi Asyrafi 68e9b5e360SHadi Asyrafi #endif /* SOCFPGA_PRIVATE_H */ 69