13f7b1490SHadi Asyrafi /* 23f7b1490SHadi Asyrafi * Copyright (c) 2019, Intel Corporation. All rights reserved. 33f7b1490SHadi Asyrafi * 43f7b1490SHadi Asyrafi * SPDX-License-Identifier: BSD-3-Clause 53f7b1490SHadi Asyrafi */ 63f7b1490SHadi Asyrafi 7*e9b5e360SHadi Asyrafi #ifndef SOCFPGA_PRIVATE_H 8*e9b5e360SHadi Asyrafi #define SOCFPGA_PRIVATE_H 9*e9b5e360SHadi Asyrafi 10*e9b5e360SHadi Asyrafi #include "socfpga_plat_def.h" 11*e9b5e360SHadi Asyrafi 12*e9b5e360SHadi Asyrafi #define EMMC_DESC_SIZE (1<<20) 13*e9b5e360SHadi Asyrafi 14*e9b5e360SHadi Asyrafi #define EMMC_INIT_PARAMS(base, clk) \ 15*e9b5e360SHadi Asyrafi { .bus_width = MMC_BUS_WIDTH_4, \ 16*e9b5e360SHadi Asyrafi .clk_rate = (clk), \ 17*e9b5e360SHadi Asyrafi .desc_base = (base), \ 18*e9b5e360SHadi Asyrafi .desc_size = EMMC_DESC_SIZE, \ 19*e9b5e360SHadi Asyrafi .flags = 0, \ 20*e9b5e360SHadi Asyrafi .reg_base = SOCFPGA_MMC_REG_BASE \ 21*e9b5e360SHadi Asyrafi } 22*e9b5e360SHadi Asyrafi 23*e9b5e360SHadi Asyrafi typedef enum { 24*e9b5e360SHadi Asyrafi BOOT_SOURCE_FPGA = 0, 25*e9b5e360SHadi Asyrafi BOOT_SOURCE_SDMMC, 26*e9b5e360SHadi Asyrafi BOOT_SOURCE_NAND, 27*e9b5e360SHadi Asyrafi BOOT_SOURCE_RSVD, 28*e9b5e360SHadi Asyrafi BOOT_SOURCE_QSPI 29*e9b5e360SHadi Asyrafi } boot_source_type; 303f7b1490SHadi Asyrafi 313f7b1490SHadi Asyrafi /******************************************************************************* 323f7b1490SHadi Asyrafi * Function and variable prototypes 333f7b1490SHadi Asyrafi ******************************************************************************/ 34*e9b5e360SHadi Asyrafi 35*e9b5e360SHadi Asyrafi void enable_nonsecure_access(void); 36*e9b5e360SHadi Asyrafi 37*e9b5e360SHadi Asyrafi void socfpga_io_setup(int boot_source); 38*e9b5e360SHadi Asyrafi 393f7b1490SHadi Asyrafi void socfgpa_configure_mmu_el3(unsigned long total_base, 403f7b1490SHadi Asyrafi unsigned long total_size, 413f7b1490SHadi Asyrafi unsigned long ro_start, 423f7b1490SHadi Asyrafi unsigned long ro_limit, 433f7b1490SHadi Asyrafi unsigned long coh_start, 443f7b1490SHadi Asyrafi unsigned long coh_limit); 453f7b1490SHadi Asyrafi 463f7b1490SHadi Asyrafi 473f7b1490SHadi Asyrafi void socfpga_configure_mmu_el1(unsigned long total_base, 483f7b1490SHadi Asyrafi unsigned long total_size, 493f7b1490SHadi Asyrafi unsigned long ro_start, 503f7b1490SHadi Asyrafi unsigned long ro_limit, 513f7b1490SHadi Asyrafi unsigned long coh_start, 523f7b1490SHadi Asyrafi unsigned long coh_limit); 533f7b1490SHadi Asyrafi 543f7b1490SHadi Asyrafi void socfpga_delay_timer_init(void); 553f7b1490SHadi Asyrafi 563f7b1490SHadi Asyrafi void socfpga_gic_driver_init(void); 573f7b1490SHadi Asyrafi 583f7b1490SHadi Asyrafi uint32_t socfpga_get_spsr_for_bl32_entry(void); 593f7b1490SHadi Asyrafi 603f7b1490SHadi Asyrafi uint32_t socfpga_get_spsr_for_bl33_entry(void); 613f7b1490SHadi Asyrafi 623f7b1490SHadi Asyrafi unsigned long socfpga_get_ns_image_entrypoint(void); 633f7b1490SHadi Asyrafi 643f7b1490SHadi Asyrafi 65*e9b5e360SHadi Asyrafi #endif /* SOCFPGA_PRIVATE_H */ 66