xref: /rk3399_ARM-atf/plat/intel/soc/common/include/socfpga_private.h (revision 8f7575efcb3df7eeb21e92677c3a7be3fe3c36df)
13f7b1490SHadi Asyrafi /*
27ac7dadbSSieu Mun Tang  * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
3*8f7575efSBoon Khai Ng  * Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
43f7b1490SHadi Asyrafi  *
53f7b1490SHadi Asyrafi  * SPDX-License-Identifier: BSD-3-Clause
63f7b1490SHadi Asyrafi  */
73f7b1490SHadi Asyrafi 
8e9b5e360SHadi Asyrafi #ifndef SOCFPGA_PRIVATE_H
9e9b5e360SHadi Asyrafi #define SOCFPGA_PRIVATE_H
10e9b5e360SHadi Asyrafi 
11*8f7575efSBoon Khai Ng #include <errno.h>
12e9b5e360SHadi Asyrafi 
13e9b5e360SHadi Asyrafi #define EMMC_DESC_SIZE		(1<<20)
14e9b5e360SHadi Asyrafi 
15e9b5e360SHadi Asyrafi #define EMMC_INIT_PARAMS(base, clk)			\
16e9b5e360SHadi Asyrafi 	{	.bus_width = MMC_BUS_WIDTH_4,		\
17e9b5e360SHadi Asyrafi 		.clk_rate = (clk),			\
18e9b5e360SHadi Asyrafi 		.desc_base = (base),			\
19e9b5e360SHadi Asyrafi 		.desc_size = EMMC_DESC_SIZE,		\
20e9b5e360SHadi Asyrafi 		.flags = 0,				\
21e9b5e360SHadi Asyrafi 		.reg_base = SOCFPGA_MMC_REG_BASE	\
22e9b5e360SHadi Asyrafi 	}
23e9b5e360SHadi Asyrafi 
24e9b5e360SHadi Asyrafi typedef enum {
25e9b5e360SHadi Asyrafi 	BOOT_SOURCE_FPGA = 0,
26e9b5e360SHadi Asyrafi 	BOOT_SOURCE_SDMMC,
27e9b5e360SHadi Asyrafi 	BOOT_SOURCE_NAND,
28ef8b05f5SSieu Mun Tang 	BOOT_SOURCE_QSPI,
29ef8b05f5SSieu Mun Tang 	BOOT_SOURCE_RSVD
30e9b5e360SHadi Asyrafi } boot_source_type;
313f7b1490SHadi Asyrafi 
323f7b1490SHadi Asyrafi /*******************************************************************************
333f7b1490SHadi Asyrafi  * Function and variable prototypes
343f7b1490SHadi Asyrafi  ******************************************************************************/
35e9b5e360SHadi Asyrafi 
36e9b5e360SHadi Asyrafi void enable_nonsecure_access(void);
37e9b5e360SHadi Asyrafi 
386cbe2c5dSMahesh Rao void socfpga_io_setup(int boot_source, unsigned long offset);
39e9b5e360SHadi Asyrafi 
403f7b1490SHadi Asyrafi void socfgpa_configure_mmu_el3(unsigned long total_base,
413f7b1490SHadi Asyrafi 			unsigned long total_size,
423f7b1490SHadi Asyrafi 			unsigned long ro_start,
433f7b1490SHadi Asyrafi 			unsigned long ro_limit,
443f7b1490SHadi Asyrafi 			unsigned long coh_start,
453f7b1490SHadi Asyrafi 			unsigned long coh_limit);
463f7b1490SHadi Asyrafi 
473f7b1490SHadi Asyrafi 
483f7b1490SHadi Asyrafi void socfpga_configure_mmu_el1(unsigned long total_base,
493f7b1490SHadi Asyrafi 			unsigned long total_size,
503f7b1490SHadi Asyrafi 			unsigned long ro_start,
513f7b1490SHadi Asyrafi 			unsigned long ro_limit,
523f7b1490SHadi Asyrafi 			unsigned long coh_start,
533f7b1490SHadi Asyrafi 			unsigned long coh_limit);
543f7b1490SHadi Asyrafi 
553f7b1490SHadi Asyrafi void socfpga_delay_timer_init(void);
563f7b1490SHadi Asyrafi 
573f7b1490SHadi Asyrafi void socfpga_gic_driver_init(void);
583f7b1490SHadi Asyrafi 
59f65bdf3aSBenjaminLimJL void socfpga_delay_timer_init_args(void);
60f65bdf3aSBenjaminLimJL 
613f7b1490SHadi Asyrafi uint32_t socfpga_get_spsr_for_bl32_entry(void);
623f7b1490SHadi Asyrafi 
633f7b1490SHadi Asyrafi uint32_t socfpga_get_spsr_for_bl33_entry(void);
643f7b1490SHadi Asyrafi 
653f7b1490SHadi Asyrafi unsigned long socfpga_get_ns_image_entrypoint(void);
663f7b1490SHadi Asyrafi 
672db1e766SHadi Asyrafi void plat_secondary_cpus_bl31_entry(void);
683f7b1490SHadi Asyrafi 
69bb9e34f9SJit Loon Lim void setup_clusterectlr_el1(void);
70bb9e34f9SJit Loon Lim 
71*8f7575efSBoon Khai Ng /******************************************************************************
72*8f7575efSBoon Khai Ng  * Macro for generic poling function
73*8f7575efSBoon Khai Ng  *****************************************************************************/
74*8f7575efSBoon Khai Ng 
75*8f7575efSBoon Khai Ng #define SOCFPGA_POLL(cond, max_count, delay, delay_fn, status)	\
76*8f7575efSBoon Khai Ng 	do {							\
77*8f7575efSBoon Khai Ng 		int __count = (max_count);			\
78*8f7575efSBoon Khai Ng 		(status) = -ETIMEDOUT;				\
79*8f7575efSBoon Khai Ng 		while ((!(cond)) && (__count-- > 0)) {		\
80*8f7575efSBoon Khai Ng 			delay_fn(delay);			\
81*8f7575efSBoon Khai Ng 		}						\
82*8f7575efSBoon Khai Ng 								\
83*8f7575efSBoon Khai Ng 		if ((cond)) {					\
84*8f7575efSBoon Khai Ng 			(status) = 0;				\
85*8f7575efSBoon Khai Ng 		}						\
86*8f7575efSBoon Khai Ng 	} while (0)
87*8f7575efSBoon Khai Ng 
88e9b5e360SHadi Asyrafi #endif /* SOCFPGA_PRIVATE_H */
89