1 /* 2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef PLATFORM_DEF_H 10 #define PLATFORM_DEF_H 11 12 #include <arch.h> 13 #include <common/interrupt_props.h> 14 #include <common/tbbr/tbbr_img_def.h> 15 #include <plat/common/common_def.h> 16 #include "socfpga_plat_def.h" 17 18 /* Platform Type */ 19 #define PLAT_SOCFPGA_STRATIX10 1 20 #define PLAT_SOCFPGA_AGILEX 2 21 #define PLAT_SOCFPGA_N5X 3 22 #define PLAT_SOCFPGA_AGILEX5 4 23 #define SIMICS_RUN 1 24 #define MAX_IO_MTD_DEVICES U(1) 25 26 /* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */ 27 #define PLAT_CPU_RELEASE_ADDR 0xffd12210 28 29 /* Magic word to indicate L2 reset is completed */ 30 #define L2_RESET_DONE_STATUS 0x1228E5E7 31 32 /* Define next boot image name and offset */ 33 /* Get non-secure image entrypoint for BL33. Zephyr and Linux */ 34 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 35 #ifndef PRELOADED_BL33_BASE 36 #define PLAT_NS_IMAGE_OFFSET 0x80200000 37 #else 38 #define PLAT_NS_IMAGE_OFFSET PRELOADED_BL33_BASE 39 #endif 40 #define PLAT_HANDOFF_OFFSET 0x0003F000 41 42 #else 43 /* Legacy Products. Please refactor with Agilex5 */ 44 #ifndef PRELOADED_BL33_BASE 45 #define PLAT_NS_IMAGE_OFFSET 0x10000000 46 #else 47 #define PLAT_NS_IMAGE_OFFSET PRELOADED_BL33_BASE 48 #endif 49 #define PLAT_HANDOFF_OFFSET 0xFFE3F000 50 #endif 51 52 #define PLAT_QSPI_DATA_BASE (0x3C00000) 53 #define PLAT_NAND_DATA_BASE (0x0200000) 54 #define PLAT_SDMMC_DATA_BASE (0x0) 55 56 57 /******************************************************************************* 58 * Platform binary types for linking 59 ******************************************************************************/ 60 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 61 #define PLATFORM_LINKER_ARCH aarch64 62 63 /* SoCFPGA supports up to 124GB RAM */ 64 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39) 65 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39) 66 67 68 /******************************************************************************* 69 * Generic platform constants 70 ******************************************************************************/ 71 #define PLAT_SECONDARY_ENTRY_BASE 0x01f78bf0 72 73 /* Size of cacheable stacks */ 74 #define PLATFORM_STACK_SIZE 0x2000 75 76 /* PSCI related constant */ 77 #define PLAT_NUM_POWER_DOMAINS 5 78 #define PLAT_MAX_PWR_LVL 1 79 #define PLAT_MAX_RET_STATE 1 80 #define PLAT_MAX_OFF_STATE 2 81 #define PLATFORM_SYSTEM_COUNT U(1) 82 #define PLATFORM_CLUSTER_COUNT U(1) 83 #define PLATFORM_CLUSTER0_CORE_COUNT U(4) 84 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 85 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 86 PLATFORM_CLUSTER0_CORE_COUNT) 87 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 88 89 /* Interrupt related constant */ 90 91 #define INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 29 92 93 #define INTEL_SOCFPGA_IRQ_SEC_SGI_0 8 94 #define INTEL_SOCFPGA_IRQ_SEC_SGI_1 9 95 #define INTEL_SOCFPGA_IRQ_SEC_SGI_2 10 96 #define INTEL_SOCFPGA_IRQ_SEC_SGI_3 11 97 #define INTEL_SOCFPGA_IRQ_SEC_SGI_4 12 98 #define INTEL_SOCFPGA_IRQ_SEC_SGI_5 13 99 #define INTEL_SOCFPGA_IRQ_SEC_SGI_6 14 100 #define INTEL_SOCFPGA_IRQ_SEC_SGI_7 15 101 102 #define TSP_IRQ_SEC_PHY_TIMER INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 103 #define TSP_SEC_MEM_BASE BL32_BASE 104 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) 105 106 107 /******************************************************************************* 108 * BL31 specific defines. 109 ******************************************************************************/ 110 /* 111 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 112 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 113 * little space for growth. 114 */ 115 116 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 117 118 #define BL1_RO_BASE (0xffe00000) 119 #define BL1_RO_LIMIT (0xffe0f000) 120 #define BL1_RW_BASE (0xffe10000) 121 #define BL1_RW_LIMIT (0xffe1ffff) 122 #define BL1_RW_SIZE (0x14000) 123 124 #define BL_DATA_LIMIT PLAT_HANDOFF_OFFSET 125 126 #define PLAT_CPUID_RELEASE (BL_DATA_LIMIT - 16) 127 #define PLAT_SEC_ENTRY (BL_DATA_LIMIT - 8) 128 129 #define CMP_ENTRY 0xFFE3EFF8 130 131 #define PLAT_SEC_WARM_ENTRY 0 132 133 /******************************************************************************* 134 * Platform specific page table and MMU setup constants 135 ******************************************************************************/ 136 #define MAX_XLAT_TABLES 8 137 #define MAX_MMAP_REGIONS 16 138 139 /******************************************************************************* 140 * Declarations and constants to access the mailboxes safely. Each mailbox is 141 * aligned on the biggest cache line size in the platform. This is known only 142 * to the platform as it might have a combination of integrated and external 143 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 144 * line at any cache level. They could belong to different cpus/clusters & 145 * get written while being protected by different locks causing corruption of 146 * a valid mailbox address. 147 ******************************************************************************/ 148 #define CACHE_WRITEBACK_SHIFT 6 149 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 150 151 /******************************************************************************* 152 * UART related constants 153 ******************************************************************************/ 154 #define CRASH_CONSOLE_BASE PLAT_UART0_BASE 155 #define PLAT_INTEL_UART_BASE PLAT_UART0_BASE 156 157 #define PLAT_BAUDRATE (115200) 158 #define PLAT_UART_CLOCK (100000000) 159 160 /******************************************************************************* 161 * PHY related constants 162 ******************************************************************************/ 163 164 #define EMAC0_PHY_MODE PHY_INTERFACE_MODE_RGMII 165 #define EMAC1_PHY_MODE PHY_INTERFACE_MODE_RGMII 166 #define EMAC2_PHY_MODE PHY_INTERFACE_MODE_RGMII 167 168 /******************************************************************************* 169 * GIC related constants 170 ******************************************************************************/ 171 #define PLAT_INTEL_SOCFPGA_GICD_BASE PLAT_GICD_BASE 172 #define PLAT_INTEL_SOCFPGA_GICC_BASE PLAT_GICC_BASE 173 174 /******************************************************************************* 175 * System counter frequency related constants 176 ******************************************************************************/ 177 178 /* 179 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 180 * terminology. On a GICv2 system or mode, the lists will be merged and treated 181 * as Group 0 interrupts. 182 */ 183 #define PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(grp) \ 184 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER, \ 185 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 186 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_0, \ 187 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 188 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_1, \ 189 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 190 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_2, \ 191 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 192 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_3, \ 193 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 194 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_4, \ 195 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 196 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_5, \ 197 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 198 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_6, \ 199 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 200 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_7, \ 201 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE) 202 203 #define PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(grp) 204 205 #define MAX_IO_HANDLES 4 206 #define MAX_IO_DEVICES 4 207 #define MAX_IO_BLOCK_DEVICES 2 208 209 #ifndef __ASSEMBLER__ 210 struct socfpga_bl31_params { 211 param_header_t h; 212 image_info_t *bl31_image_info; 213 entry_point_info_t *bl32_ep_info; 214 image_info_t *bl32_image_info; 215 entry_point_info_t *bl33_ep_info; 216 image_info_t *bl33_image_info; 217 }; 218 #endif 219 220 #endif /* PLATFORM_DEF_H */ 221