1 /* 2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef PLATFORM_DEF_H 10 #define PLATFORM_DEF_H 11 12 #include <arch.h> 13 #include <common/interrupt_props.h> 14 #include <common/tbbr/tbbr_img_def.h> 15 #include <plat/common/common_def.h> 16 #include "socfpga_plat_def.h" 17 18 /* Platform Type */ 19 #define PLAT_SOCFPGA_STRATIX10 1 20 #define PLAT_SOCFPGA_AGILEX 2 21 #define PLAT_SOCFPGA_N5X 3 22 #define PLAT_SOCFPGA_AGILEX5 4 23 #define SIMICS_RUN 1 24 #define MAX_IO_MTD_DEVICES U(1) 25 /* Boot Source configuration 26 * TODO: Shall consider "assert_numeric" in the future 27 */ 28 #if SOCFPGA_BOOT_SOURCE_NAND 29 #define BOOT_SOURCE BOOT_SOURCE_NAND 30 #elif SOCFPGA_BOOT_SOURCE_SDMMC 31 #define BOOT_SOURCE BOOT_SOURCE_SDMMC 32 #elif SOCFPGA_BOOT_SOURCE_QSPI 33 #define BOOT_SOURCE BOOT_SOURCE_QSPI 34 #else 35 #define BOOT_SOURCE BOOT_SOURCE_SDMMC 36 #endif 37 38 /* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */ 39 #define PLAT_CPU_RELEASE_ADDR 0xffd12210 40 41 /* Define next boot image name and offset */ 42 /* Get non-secure image entrypoint for BL33. Zephyr and Linux */ 43 #ifdef PRELOADED_BL33_BASE 44 #define PLAT_NS_IMAGE_OFFSET PRELOADED_BL33_BASE 45 #else 46 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 47 #define PLAT_NS_IMAGE_OFFSET 0x80200000 48 #else 49 #define PLAT_NS_IMAGE_OFFSET 0x10000000 50 #endif 51 #endif /* #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 */ 52 53 #define PLAT_QSPI_DATA_BASE (0x3C00000) 54 #define PLAT_NAND_DATA_BASE (0x0200000) 55 #define PLAT_SDMMC_DATA_BASE (0x0) 56 57 58 /******************************************************************************* 59 * Platform binary types for linking 60 ******************************************************************************/ 61 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 62 #define PLATFORM_LINKER_ARCH aarch64 63 64 /* SoCFPGA supports up to 124GB RAM */ 65 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39) 66 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39) 67 68 69 /******************************************************************************* 70 * Generic platform constants 71 ******************************************************************************/ 72 #define PLAT_SECONDARY_ENTRY_BASE 0x01f78bf0 73 74 /* Size of cacheable stacks */ 75 #define PLATFORM_STACK_SIZE 0x2000 76 77 /* PSCI related constant */ 78 #define PLAT_NUM_POWER_DOMAINS 5 79 #define PLAT_MAX_PWR_LVL 1 80 #define PLAT_MAX_RET_STATE 1 81 #define PLAT_MAX_OFF_STATE 2 82 #define PLATFORM_SYSTEM_COUNT U(1) 83 #define PLATFORM_CLUSTER_COUNT U(1) 84 #define PLATFORM_CLUSTER0_CORE_COUNT U(4) 85 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 86 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 87 PLATFORM_CLUSTER0_CORE_COUNT) 88 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 89 90 /* Interrupt related constant */ 91 92 #define INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 29 93 94 #define INTEL_SOCFPGA_IRQ_SEC_SGI_0 8 95 #define INTEL_SOCFPGA_IRQ_SEC_SGI_1 9 96 #define INTEL_SOCFPGA_IRQ_SEC_SGI_2 10 97 #define INTEL_SOCFPGA_IRQ_SEC_SGI_3 11 98 #define INTEL_SOCFPGA_IRQ_SEC_SGI_4 12 99 #define INTEL_SOCFPGA_IRQ_SEC_SGI_5 13 100 #define INTEL_SOCFPGA_IRQ_SEC_SGI_6 14 101 #define INTEL_SOCFPGA_IRQ_SEC_SGI_7 15 102 103 #define TSP_IRQ_SEC_PHY_TIMER INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 104 #define TSP_SEC_MEM_BASE BL32_BASE 105 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) 106 107 108 /******************************************************************************* 109 * BL31 specific defines. 110 ******************************************************************************/ 111 /* 112 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 113 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 114 * little space for growth. 115 */ 116 117 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 118 119 #define BL1_RO_BASE (0xffe00000) 120 #define BL1_RO_LIMIT (0xffe0f000) 121 #define BL1_RW_BASE (0xffe10000) 122 #define BL1_RW_LIMIT (0xffe1ffff) 123 #define BL1_RW_SIZE (0x14000) 124 125 #define BL_DATA_LIMIT PLAT_HANDOFF_OFFSET 126 127 #define PLAT_CPUID_RELEASE (BL_DATA_LIMIT - 16) 128 #define PLAT_SEC_ENTRY (BL_DATA_LIMIT - 8) 129 130 #define CMP_ENTRY 0xFFE3EFF8 131 132 #define PLAT_SEC_WARM_ENTRY 0 133 134 /******************************************************************************* 135 * Platform specific page table and MMU setup constants 136 ******************************************************************************/ 137 #define MAX_XLAT_TABLES 8 138 #define MAX_MMAP_REGIONS 16 139 140 /******************************************************************************* 141 * Declarations and constants to access the mailboxes safely. Each mailbox is 142 * aligned on the biggest cache line size in the platform. This is known only 143 * to the platform as it might have a combination of integrated and external 144 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 145 * line at any cache level. They could belong to different cpus/clusters & 146 * get written while being protected by different locks causing corruption of 147 * a valid mailbox address. 148 ******************************************************************************/ 149 #define CACHE_WRITEBACK_SHIFT 6 150 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 151 152 /******************************************************************************* 153 * UART related constants 154 ******************************************************************************/ 155 #define CRASH_CONSOLE_BASE PLAT_UART0_BASE 156 #define PLAT_INTEL_UART_BASE PLAT_UART0_BASE 157 158 #define PLAT_BAUDRATE (115200) 159 #define PLAT_UART_CLOCK (100000000) 160 161 /******************************************************************************* 162 * PHY related constants 163 ******************************************************************************/ 164 165 #define EMAC0_PHY_MODE PHY_INTERFACE_MODE_RGMII 166 #define EMAC1_PHY_MODE PHY_INTERFACE_MODE_RGMII 167 #define EMAC2_PHY_MODE PHY_INTERFACE_MODE_RGMII 168 169 /******************************************************************************* 170 * GIC related constants 171 ******************************************************************************/ 172 #define PLAT_INTEL_SOCFPGA_GICD_BASE PLAT_GICD_BASE 173 #define PLAT_INTEL_SOCFPGA_GICC_BASE PLAT_GICC_BASE 174 175 /******************************************************************************* 176 * System counter frequency related constants 177 ******************************************************************************/ 178 179 /* 180 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 181 * terminology. On a GICv2 system or mode, the lists will be merged and treated 182 * as Group 0 interrupts. 183 */ 184 #define PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(grp) \ 185 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER, \ 186 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 187 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_0, \ 188 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 189 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_1, \ 190 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 191 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_2, \ 192 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 193 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_3, \ 194 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 195 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_4, \ 196 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 197 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_5, \ 198 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 199 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_6, \ 200 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 201 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_7, \ 202 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE) 203 204 #define PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(grp) 205 206 #define MAX_IO_HANDLES 4 207 #define MAX_IO_DEVICES 4 208 #define MAX_IO_BLOCK_DEVICES 2 209 210 #ifndef __ASSEMBLER__ 211 struct socfpga_bl31_params { 212 param_header_t h; 213 image_info_t *bl31_image_info; 214 entry_point_info_t *bl32_ep_info; 215 image_info_t *bl32_image_info; 216 entry_point_info_t *bl33_ep_info; 217 image_info_t *bl33_image_info; 218 }; 219 #endif 220 221 #endif /* PLATFORM_DEF_H */ 222