1 /* 2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef PLATFORM_DEF_H 9 #define PLATFORM_DEF_H 10 11 #include <arch.h> 12 #include <common/interrupt_props.h> 13 #include <common/tbbr/tbbr_img_def.h> 14 #include <plat/common/common_def.h> 15 #include "socfpga_plat_def.h" 16 17 /* Platform Type */ 18 #define PLAT_SOCFPGA_STRATIX10 1 19 #define PLAT_SOCFPGA_AGILEX 2 20 #define PLAT_SOCFPGA_N5X 3 21 #define PLAT_SOCFPGA_AGILEX5 4 22 #define SIMICS_RUN 1 23 #define MAX_IO_MTD_DEVICES U(1) 24 25 /* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */ 26 #define PLAT_CPU_RELEASE_ADDR 0xffd12210 27 28 /* 29 * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset 30 * is done and HPS should trigger warm reset via RMR_EL3. 31 */ 32 #define L2_RESET_DONE_REG 0xFFD12218 33 34 /* Magic word to indicate L2 reset is completed */ 35 #define L2_RESET_DONE_STATUS 0x1228E5E7 36 37 /* Define next boot image name and offset */ 38 /* Get non-secure image entrypoint for BL33. Zephyr and Linux */ 39 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 40 41 #ifndef PRELOADED_BL33_BASE 42 #define PLAT_NS_IMAGE_OFFSET 0x80200000 43 #else 44 #define PLAT_NS_IMAGE_OFFSET PRELOADED_BL33_BASE 45 #endif 46 #define PLAT_HANDOFF_OFFSET 0x0003F000 47 48 #else 49 #define PLAT_NS_IMAGE_OFFSET 0x10000000 50 #define PLAT_HANDOFF_OFFSET 0xFFE3F000 51 #endif 52 53 /******************************************************************************* 54 * Platform binary types for linking 55 ******************************************************************************/ 56 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 57 #define PLATFORM_LINKER_ARCH aarch64 58 59 /* SoCFPGA supports up to 124GB RAM */ 60 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39) 61 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39) 62 63 64 /******************************************************************************* 65 * Generic platform constants 66 ******************************************************************************/ 67 #define PLAT_SECONDARY_ENTRY_BASE 0x01f78bf0 68 69 /* Size of cacheable stacks */ 70 #define PLATFORM_STACK_SIZE 0x2000 71 72 /* PSCI related constant */ 73 #define PLAT_NUM_POWER_DOMAINS 5 74 #define PLAT_MAX_PWR_LVL 1 75 #define PLAT_MAX_RET_STATE 1 76 #define PLAT_MAX_OFF_STATE 2 77 #define PLATFORM_SYSTEM_COUNT U(1) 78 #define PLATFORM_CLUSTER_COUNT U(1) 79 #define PLATFORM_CLUSTER0_CORE_COUNT U(4) 80 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 81 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 82 PLATFORM_CLUSTER0_CORE_COUNT) 83 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 84 85 /* Interrupt related constant */ 86 87 #define INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 29 88 89 #define INTEL_SOCFPGA_IRQ_SEC_SGI_0 8 90 #define INTEL_SOCFPGA_IRQ_SEC_SGI_1 9 91 #define INTEL_SOCFPGA_IRQ_SEC_SGI_2 10 92 #define INTEL_SOCFPGA_IRQ_SEC_SGI_3 11 93 #define INTEL_SOCFPGA_IRQ_SEC_SGI_4 12 94 #define INTEL_SOCFPGA_IRQ_SEC_SGI_5 13 95 #define INTEL_SOCFPGA_IRQ_SEC_SGI_6 14 96 #define INTEL_SOCFPGA_IRQ_SEC_SGI_7 15 97 98 #define TSP_IRQ_SEC_PHY_TIMER INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 99 #define TSP_SEC_MEM_BASE BL32_BASE 100 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) 101 102 103 /******************************************************************************* 104 * BL31 specific defines. 105 ******************************************************************************/ 106 /* 107 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 108 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 109 * little space for growth. 110 */ 111 112 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 113 114 #define BL1_RO_BASE (0xffe00000) 115 #define BL1_RO_LIMIT (0xffe0f000) 116 #define BL1_RW_BASE (0xffe10000) 117 #define BL1_RW_LIMIT (0xffe1ffff) 118 #define BL1_RW_SIZE (0x14000) 119 120 #define BL_DATA_LIMIT PLAT_HANDOFF_OFFSET 121 122 #define PLAT_CPUID_RELEASE (BL_DATA_LIMIT - 16) 123 #define PLAT_SEC_ENTRY (BL_DATA_LIMIT - 8) 124 125 #define CMP_ENTRY 0xFFE3EFF8 126 127 #define PLAT_SEC_WARM_ENTRY 0 128 129 /******************************************************************************* 130 * Platform specific page table and MMU setup constants 131 ******************************************************************************/ 132 #define MAX_XLAT_TABLES 8 133 #define MAX_MMAP_REGIONS 16 134 135 /******************************************************************************* 136 * Declarations and constants to access the mailboxes safely. Each mailbox is 137 * aligned on the biggest cache line size in the platform. This is known only 138 * to the platform as it might have a combination of integrated and external 139 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 140 * line at any cache level. They could belong to different cpus/clusters & 141 * get written while being protected by different locks causing corruption of 142 * a valid mailbox address. 143 ******************************************************************************/ 144 #define CACHE_WRITEBACK_SHIFT 6 145 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 146 147 /******************************************************************************* 148 * UART related constants 149 ******************************************************************************/ 150 #define CRASH_CONSOLE_BASE PLAT_UART0_BASE 151 #define PLAT_INTEL_UART_BASE PLAT_UART0_BASE 152 153 #define PLAT_BAUDRATE (115200) 154 #define PLAT_UART_CLOCK (100000000) 155 156 /******************************************************************************* 157 * PHY related constants 158 ******************************************************************************/ 159 160 #define EMAC0_PHY_MODE PHY_INTERFACE_MODE_RGMII 161 #define EMAC1_PHY_MODE PHY_INTERFACE_MODE_RGMII 162 #define EMAC2_PHY_MODE PHY_INTERFACE_MODE_RGMII 163 164 /******************************************************************************* 165 * GIC related constants 166 ******************************************************************************/ 167 #define PLAT_INTEL_SOCFPGA_GICD_BASE PLAT_GICD_BASE 168 #define PLAT_INTEL_SOCFPGA_GICC_BASE PLAT_GICC_BASE 169 170 /******************************************************************************* 171 * System counter frequency related constants 172 ******************************************************************************/ 173 174 /* 175 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 176 * terminology. On a GICv2 system or mode, the lists will be merged and treated 177 * as Group 0 interrupts. 178 */ 179 #define PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(grp) \ 180 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER, \ 181 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 182 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_0, \ 183 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 184 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_1, \ 185 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 186 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_2, \ 187 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 188 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_3, \ 189 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 190 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_4, \ 191 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 192 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_5, \ 193 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 194 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_6, \ 195 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 196 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_7, \ 197 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE) 198 199 #define PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(grp) 200 201 #define MAX_IO_HANDLES 4 202 #define MAX_IO_DEVICES 4 203 #define MAX_IO_BLOCK_DEVICES 2 204 205 #ifndef __ASSEMBLER__ 206 struct socfpga_bl31_params { 207 param_header_t h; 208 image_info_t *bl31_image_info; 209 entry_point_info_t *bl32_ep_info; 210 image_info_t *bl32_image_info; 211 entry_point_info_t *bl33_ep_info; 212 image_info_t *bl33_image_info; 213 }; 214 #endif 215 216 #endif /* PLATFORM_DEF_H */ 217