1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <platform_def.h> 10 #include <plat/common/platform.h> 11 #include <socfpga_private.h> 12 13 14 unsigned int plat_get_syscnt_freq2(void) 15 { 16 return PLAT_SYS_COUNTER_FREQ_IN_TICKS; 17 } 18 19 unsigned long socfpga_get_ns_image_entrypoint(void) 20 { 21 return PLAT_NS_IMAGE_OFFSET; 22 } 23 24 /****************************************************************************** 25 * Gets SPSR for BL32 entry 26 *****************************************************************************/ 27 uint32_t socfpga_get_spsr_for_bl32_entry(void) 28 { 29 /* 30 * The Secure Payload Dispatcher service is responsible for 31 * setting the SPSR prior to entry into the BL32 image. 32 */ 33 return 0; 34 } 35 36 /****************************************************************************** 37 * Gets SPSR for BL33 entry 38 *****************************************************************************/ 39 uint32_t socfpga_get_spsr_for_bl33_entry(void) 40 { 41 unsigned long el_status; 42 unsigned int mode; 43 uint32_t spsr; 44 45 /* Figure out what mode we enter the non-secure world in */ 46 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 47 el_status &= ID_AA64PFR0_ELX_MASK; 48 49 mode = (el_status) ? MODE_EL2 : MODE_EL1; 50 51 /* 52 * TODO: Consider the possibility of specifying the SPSR in 53 * the FIP ToC and allowing the platform to have a say as 54 * well. 55 */ 56 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 57 return spsr; 58 } 59 60