1 /* 2 * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <common/desc_image_load.h> 14 #include <drivers/cadence/cdns_sdmmc.h> 15 #include <drivers/generic_delay_timer.h> 16 #include <drivers/synopsys/dw_mmc.h> 17 #include <drivers/ti/uart/uart_16550.h> 18 #include <lib/mmio.h> 19 #include <lib/xlat_tables/xlat_tables_v2.h> 20 21 #include "agilex5_clock_manager.h" 22 #include "agilex5_memory_controller.h" 23 #include "agilex5_mmc.h" 24 #include "agilex5_pinmux.h" 25 #include "agilex5_system_manager.h" 26 #include "ccu/ncore_ccu.h" 27 #include "combophy/combophy.h" 28 #include "nand/nand.h" 29 #include "qspi/cadence_qspi.h" 30 #include "sdmmc/sdmmc.h" 31 #include "socfpga_emac.h" 32 #include "socfpga_f2sdram_manager.h" 33 #include "socfpga_handoff.h" 34 #include "socfpga_mailbox.h" 35 #include "socfpga_private.h" 36 #include "socfpga_reset_manager.h" 37 #include "wdt/watchdog.h" 38 39 40 /* Declare mmc_info */ 41 static struct mmc_device_info mmc_info; 42 43 /* Declare cadence idmac descriptor */ 44 extern struct cdns_idmac_desc cdns_desc[8] __aligned(32); 45 46 const mmap_region_t agilex_plat_mmap[] = { 47 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, 48 MT_MEMORY | MT_RW | MT_NS), 49 MAP_REGION_FLAT(PSS_BASE, PSS_SIZE, 50 MT_DEVICE | MT_RW | MT_NS), 51 MAP_REGION_FLAT(MPFE_BASE, MPFE_SIZE, 52 MT_DEVICE | MT_RW | MT_SECURE), 53 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, 54 MT_NON_CACHEABLE | MT_RW | MT_SECURE), 55 MAP_REGION_FLAT(CCU_BASE, CCU_SIZE, 56 MT_DEVICE | MT_RW | MT_SECURE), 57 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, 58 MT_DEVICE | MT_RW | MT_NS), 59 MAP_REGION_FLAT(GIC_BASE, GIC_SIZE, 60 MT_DEVICE | MT_RW | MT_SECURE), 61 {0}, 62 }; 63 64 boot_source_type boot_source = BOOT_SOURCE; 65 66 void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, 67 u_register_t x2, u_register_t x4) 68 { 69 static console_t console; 70 71 handoff reverse_handoff_ptr = { 0 }; 72 73 generic_delay_timer_init(); 74 config_clkmgr_handoff(&reverse_handoff_ptr); 75 mailbox_init(); 76 enable_nonsecure_access(); 77 78 deassert_peripheral_reset(); 79 if (combo_phy_init(&reverse_handoff_ptr) != 0) { 80 ERROR("Combo Phy initialization failed\n"); 81 } 82 83 console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK, 84 PLAT_BAUDRATE, &console); 85 86 /* Store magic number */ 87 // TODO: Temp workaround to ungate testing 88 // mmio_write_32(L2_RESET_DONE_REG, PLAT_L2_RESET_REQ); 89 } 90 91 void bl2_el3_plat_arch_setup(void) 92 { 93 handoff reverse_handoff_ptr; 94 95 struct cdns_sdmmc_params params = EMMC_INIT_PARAMS((uintptr_t) &cdns_desc, get_mmc_clk()); 96 97 mmc_info.mmc_dev_type = MMC_DEVICE_TYPE; 98 mmc_info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3; 99 100 /* Request ownership and direct access to QSPI */ 101 mailbox_hps_qspi_enable(); 102 103 switch (boot_source) { 104 case BOOT_SOURCE_SDMMC: 105 NOTICE("SDMMC boot\n"); 106 sdmmc_init(&reverse_handoff_ptr, ¶ms, &mmc_info); 107 socfpga_io_setup(boot_source); 108 break; 109 110 case BOOT_SOURCE_QSPI: 111 NOTICE("QSPI boot\n"); 112 cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL, 113 QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS, 114 QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0); 115 socfpga_io_setup(boot_source); 116 break; 117 118 case BOOT_SOURCE_NAND: 119 NOTICE("NAND boot\n"); 120 nand_init(&reverse_handoff_ptr); 121 socfpga_io_setup(boot_source); 122 break; 123 124 default: 125 ERROR("Unsupported boot source\n"); 126 panic(); 127 break; 128 } 129 } 130 131 uint32_t get_spsr_for_bl33_entry(void) 132 { 133 unsigned long el_status; 134 unsigned int mode; 135 uint32_t spsr; 136 137 /* Figure out what mode we enter the non-secure world in */ 138 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 139 el_status &= ID_AA64PFR0_ELX_MASK; 140 141 mode = (el_status) ? MODE_EL2 : MODE_EL1; 142 143 /* 144 * TODO: Consider the possibility of specifying the SPSR in 145 * the FIP ToC and allowing the platform to have a say as 146 * well. 147 */ 148 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 149 return spsr; 150 } 151 152 int bl2_plat_handle_post_image_load(unsigned int image_id) 153 { 154 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 155 156 assert(bl_mem_params); 157 158 switch (image_id) { 159 case BL33_IMAGE_ID: 160 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 161 bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry(); 162 break; 163 default: 164 break; 165 } 166 167 return 0; 168 } 169 170 /******************************************************************************* 171 * Perform any BL3-1 platform setup code 172 ******************************************************************************/ 173 void bl2_platform_setup(void) 174 { 175 } 176