1 /* 2 * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024-2025, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <common/desc_image_load.h> 15 #include <drivers/cadence/cdns_sdmmc.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <drivers/synopsys/dw_mmc.h> 18 #include <drivers/ti/uart/uart_16550.h> 19 #include <lib/mmio.h> 20 #include <lib/xlat_tables/xlat_tables_v2.h> 21 22 #include "agilex5_clock_manager.h" 23 #include "agilex5_ddr.h" 24 #include "agilex5_memory_controller.h" 25 #include "agilex5_mmc.h" 26 #include "agilex5_pinmux.h" 27 #include "agilex5_power_manager.h" 28 #include "agilex5_system_manager.h" 29 #include "ccu/ncore_ccu.h" 30 #include "combophy/combophy.h" 31 #include "nand/nand.h" 32 #include "qspi/cadence_qspi.h" 33 #include "sdmmc/sdmmc.h" 34 /* TODO: DTB not available */ 35 // #include "socfpga_dt.h" 36 #include "socfpga_emac.h" 37 #include "socfpga_f2sdram_manager.h" 38 #include "socfpga_handoff.h" 39 #include "socfpga_mailbox.h" 40 #include "socfpga_private.h" 41 #include "socfpga_reset_manager.h" 42 #include "socfpga_ros.h" 43 #include "socfpga_vab.h" 44 #include "wdt/watchdog.h" 45 46 47 /* Declare mmc_info */ 48 static struct mmc_device_info mmc_info; 49 50 /* Declare cadence idmac descriptor */ 51 extern struct cdns_idmac_desc cdns_desc[8] __aligned(32); 52 53 const mmap_region_t agilex_plat_mmap[] = { 54 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, 55 MT_MEMORY | MT_RW | MT_NS), 56 MAP_REGION_FLAT(PSS_BASE, PSS_SIZE, 57 MT_DEVICE | MT_RW | MT_NS), 58 MAP_REGION_FLAT(MPFE_BASE, MPFE_SIZE, 59 MT_DEVICE | MT_RW | MT_SECURE), 60 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, 61 MT_NON_CACHEABLE | MT_RW | MT_SECURE), 62 MAP_REGION_FLAT(CCU_BASE, CCU_SIZE, 63 MT_DEVICE | MT_RW | MT_SECURE), 64 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, 65 MT_DEVICE | MT_RW | MT_NS), 66 MAP_REGION_FLAT(GIC_BASE, GIC_SIZE, 67 MT_DEVICE | MT_RW | MT_SECURE), 68 {0}, 69 }; 70 71 boot_source_type boot_source = BOOT_SOURCE; 72 73 void bl2_el3_early_platform_setup(u_register_t x0 __unused, 74 u_register_t x1 __unused, 75 u_register_t x2 __unused, 76 u_register_t x3 __unused) 77 { 78 static console_t console; 79 handoff reverse_handoff_ptr; 80 81 /* Enable nonsecure access for peripherals and other misc components */ 82 enable_nonsecure_access(); 83 84 /* Bring all the required peripherals out of reset */ 85 deassert_peripheral_reset(); 86 87 /* 88 * Initialize the UART console early in BL2 EL3 boot flow to get 89 * the error/notice messages wherever required. 90 */ 91 console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK, 92 PLAT_BAUDRATE, &console); 93 94 /* Generic delay timer init */ 95 generic_delay_timer_init(); 96 97 socfpga_delay_timer_init(); 98 99 /* Get the handoff data */ 100 if ((socfpga_get_handoff(&reverse_handoff_ptr)) != 0) { 101 ERROR("SOCFPGA: Failed to get the correct handoff data\n"); 102 panic(); 103 } 104 105 /* Configure the pinmux */ 106 config_pinmux(&reverse_handoff_ptr); 107 108 /* Configure OCRAM to NON SECURE ACCESS */ 109 mmio_write_32(OCRAM_REGION_0_REG_BASE, OCRAM_NON_SECURE_ENABLE); 110 mmio_write_32(SOCFPGA_L4_PER_SCR_REG_BASE + SOCFPGA_SDMMC_SECU_BIT, 111 SOCFPGA_SDMMC_SECU_BIT_ENABLE); 112 mmio_write_32(SOCFPGA_L4_SYS_SCR_REG_BASE + SOCFPGA_SDMMC_SECU_BIT, 113 SOCFPGA_SDMMC_SECU_BIT_ENABLE); 114 mmio_write_32(SOCFPGA_LWSOC2FPGA_SCR_REG_BASE, 115 SOCFPGA_LWSOC2FPGA_ENABLE); 116 117 /* Configure the clock manager */ 118 if ((config_clkmgr_handoff(&reverse_handoff_ptr)) != 0) { 119 ERROR("SOCFPGA: Failed to initialize the clock manager\n"); 120 panic(); 121 } 122 123 /* Configure power manager PSS SRAM power gate */ 124 config_pwrmgr_handoff(&reverse_handoff_ptr); 125 126 /* Initialize the mailbox to enable communication between HPS and SDM */ 127 mailbox_init(); 128 129 /* Perform a handshake with certain peripherals before issuing a reset */ 130 config_hps_hs_before_warm_reset(); 131 132 /* TODO: watchdog init */ 133 //watchdog_init(clkmgr_get_rate(CLKMGR_WDT_CLK_ID)); 134 135 /* Initialize the CCU module for hardware cache coherency */ 136 init_ncore_ccu(); 137 138 socfpga_emac_init(); 139 140 /* DDR and IOSSM driver init */ 141 agilex5_ddr_init(&reverse_handoff_ptr); 142 143 /* TODO: DTB not available */ 144 // if (socfpga_dt_open_and_check(SOCFPGA_DTB_BASE, DT_COMPATIBLE_STR) < 0) { 145 // ERROR("SOCFPGA: Failed to open device tree\n"); 146 // panic(); 147 // } 148 149 if (combo_phy_init(&reverse_handoff_ptr) != 0) { 150 ERROR("SOCFPGA: Combo Phy initialization failed\n"); 151 } 152 153 /* Enable FPGA bridges as required */ 154 if (!intel_mailbox_is_fpga_not_ready()) { 155 socfpga_bridges_enable(SOC2FPGA_MASK | LWHPS2FPGA_MASK | 156 FPGA2SOC_MASK | F2SDRAM0_MASK); 157 } 158 } 159 160 void bl2_el3_plat_arch_setup(void) 161 { 162 handoff reverse_handoff_ptr; 163 unsigned long offset = 0; 164 165 struct cdns_sdmmc_params params = EMMC_INIT_PARAMS((uintptr_t) &cdns_desc, 166 clkmgr_get_rate(CLKMGR_SDMMC_CLK_ID)); 167 168 mmc_info.mmc_dev_type = MMC_DEVICE_TYPE; 169 mmc_info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3; 170 171 /* Request ownership and direct access to QSPI */ 172 mailbox_hps_qspi_enable(); 173 174 switch (boot_source) { 175 case BOOT_SOURCE_SDMMC: 176 NOTICE("SOCFPGA: SDMMC boot\n"); 177 cdns_mmc_init(¶ms, &mmc_info); 178 socfpga_io_setup(boot_source, PLAT_SDMMC_DATA_BASE); 179 break; 180 181 case BOOT_SOURCE_QSPI: 182 NOTICE("SOCFPGA: QSPI boot\n"); 183 cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL, 184 QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS, 185 QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0); 186 if (ros_qspi_get_ssbl_offset(&offset) != ROS_RET_OK) { 187 offset = PLAT_QSPI_DATA_BASE; 188 } 189 socfpga_io_setup(boot_source, offset); 190 break; 191 192 case BOOT_SOURCE_NAND: 193 NOTICE("SOCFPGA: SOCFPGA: NAND boot\n"); 194 nand_init(&reverse_handoff_ptr); 195 socfpga_io_setup(boot_source, PLAT_NAND_DATA_BASE); 196 break; 197 198 default: 199 ERROR("SOCFPGA: Unsupported boot source\n"); 200 panic(); 201 break; 202 } 203 } 204 205 uint32_t get_spsr_for_bl33_entry(void) 206 { 207 unsigned long el_status; 208 unsigned int mode; 209 uint32_t spsr; 210 211 /* Figure out what mode we enter the non-secure world in */ 212 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 213 el_status &= ID_AA64PFR0_ELX_MASK; 214 215 mode = (el_status) ? MODE_EL2 : MODE_EL1; 216 217 /* 218 * TODO: Consider the possibility of specifying the SPSR in 219 * the FIP ToC and allowing the platform to have a say as 220 * well. 221 */ 222 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 223 return spsr; 224 } 225 226 int bl2_plat_handle_post_image_load(unsigned int image_id) 227 { 228 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 229 230 assert(bl_mem_params); 231 232 #if SOCFPGA_SECURE_VAB_AUTH 233 /* 234 * VAB Authentication start here. 235 * If failed to authenticate, shall not proceed to process BL31 and hang. 236 */ 237 int ret = 0; 238 239 ret = socfpga_vab_init(image_id); 240 if (ret < 0) { 241 ERROR("SOCFPGA: VAB Authentication failed\n"); 242 wfi(); 243 } 244 #endif 245 246 switch (image_id) { 247 case BL33_IMAGE_ID: 248 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 249 bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry(); 250 break; 251 default: 252 break; 253 } 254 255 return 0; 256 } 257 258 /******************************************************************************* 259 * Perform any BL3-1 platform setup code 260 ******************************************************************************/ 261 void bl2_platform_setup(void) 262 { 263 } 264