1# 2# Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved. 3# Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4# Copyright (c) 2024, Altera Corporation. All rights reserved. 5# 6# SPDX-License-Identifier: BSD-3-Clause 7# 8 9PLAT_INCLUDES := \ 10 -Iplat/intel/soc/agilex/include/ \ 11 -Iplat/intel/soc/common/drivers/ \ 12 -Iplat/intel/soc/common/include/ 13 14# Include GICv2 driver files 15include drivers/arm/gic/v2/gicv2.mk 16AGX_GICv2_SOURCES := \ 17 ${GICV2_SOURCES} \ 18 plat/common/plat_gicv2.c 19 20 21PLAT_BL_COMMON_SOURCES := \ 22 ${AGX_GICv2_SOURCES} \ 23 drivers/delay_timer/delay_timer.c \ 24 drivers/delay_timer/generic_delay_timer.c \ 25 drivers/ti/uart/aarch64/16550_console.S \ 26 lib/xlat_tables/aarch64/xlat_tables.c \ 27 lib/xlat_tables/xlat_tables_common.c \ 28 plat/intel/soc/common/aarch64/platform_common.c \ 29 plat/intel/soc/common/aarch64/plat_helpers.S \ 30 plat/intel/soc/common/drivers/ccu/ncore_ccu.c \ 31 plat/intel/soc/common/lib/sha/sha.c \ 32 plat/intel/soc/common/socfpga_delay_timer.c 33 34BL2_SOURCES += \ 35 common/desc_image_load.c \ 36 drivers/mmc/mmc.c \ 37 drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \ 38 drivers/io/io_storage.c \ 39 drivers/io/io_block.c \ 40 drivers/io/io_fip.c \ 41 drivers/partition/partition.c \ 42 drivers/partition/gpt.c \ 43 drivers/synopsys/emmc/dw_mmc.c \ 44 lib/cpus/aarch64/cortex_a53.S \ 45 plat/intel/soc/agilex/bl2_plat_setup.c \ 46 plat/intel/soc/agilex/soc/agilex_clock_manager.c \ 47 plat/intel/soc/agilex/soc/agilex_memory_controller.c \ 48 plat/intel/soc/agilex/soc/agilex_mmc.c \ 49 plat/intel/soc/agilex/soc/agilex_pinmux.c \ 50 plat/intel/soc/common/bl2_plat_mem_params_desc.c \ 51 plat/intel/soc/common/socfpga_image_load.c \ 52 plat/intel/soc/common/socfpga_ros.c \ 53 plat/intel/soc/common/socfpga_storage.c \ 54 plat/intel/soc/common/socfpga_vab.c \ 55 plat/intel/soc/common/soc/socfpga_emac.c \ 56 plat/intel/soc/common/soc/socfpga_firewall.c \ 57 plat/intel/soc/common/soc/socfpga_handoff.c \ 58 plat/intel/soc/common/soc/socfpga_mailbox.c \ 59 plat/intel/soc/common/soc/socfpga_reset_manager.c \ 60 plat/intel/soc/common/drivers/ddr/ddr.c \ 61 plat/intel/soc/common/drivers/qspi/cadence_qspi.c \ 62 plat/intel/soc/common/drivers/wdt/watchdog.c 63 64include lib/zlib/zlib.mk 65PLAT_INCLUDES += -Ilib/zlib 66BL2_SOURCES += $(ZLIB_SOURCES) 67 68BL31_SOURCES += \ 69 drivers/arm/cci/cci.c \ 70 lib/cpus/aarch64/aem_generic.S \ 71 lib/cpus/aarch64/cortex_a53.S \ 72 plat/common/plat_psci_common.c \ 73 plat/intel/soc/agilex/bl31_plat_setup.c \ 74 plat/intel/soc/agilex/soc/agilex_clock_manager.c \ 75 plat/intel/soc/common/socfpga_psci.c \ 76 plat/intel/soc/common/socfpga_sip_svc.c \ 77 plat/intel/soc/common/socfpga_sip_svc_v2.c \ 78 plat/intel/soc/common/socfpga_topology.c \ 79 plat/intel/soc/common/sip/socfpga_sip_ecc.c \ 80 plat/intel/soc/common/sip/socfpga_sip_fcs.c \ 81 plat/intel/soc/common/soc/socfpga_mailbox.c \ 82 plat/intel/soc/common/soc/socfpga_reset_manager.c 83 84# Don't have the Linux kernel as a BL33 image by default 85ARM_LINUX_KERNEL_AS_BL33 := 0 86$(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33)) 87$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33)) 88$(eval $(call add_define,ARM_PRELOADED_DTB_BASE)) 89 90# Configs for VAB Authentication 91SOCFPGA_SECURE_VAB_AUTH := 0 92$(eval $(call assert_boolean,SOCFPGA_SECURE_VAB_AUTH)) 93$(eval $(call add_define,SOCFPGA_SECURE_VAB_AUTH)) 94 95PROGRAMMABLE_RESET_ADDRESS := 0 96RESET_TO_BL2 := 1 97BL2_INV_DCACHE := 0 98USE_COHERENT_MEM := 1 99 100HANDLE_EA_EL3_FIRST_NS := 1