xref: /rk3399_ARM-atf/plat/intel/soc/agilex/include/agilex_system_manager.h (revision 222519a0ea5cf3dbbb64de6e69de83d43c06a795)
1 /*
2  * Copyright (c) 2019, Intel Corporation. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef AGX_SYSTEMMANAGER_H
8 #define AGX_SYSTEMMANAGER_H
9 
10 #define AGX_FIREWALL_SOC2FPGA			0xffd21200
11 #define AGX_FIREWALL_LWSOC2FPGA			0xffd21300
12 
13 #define AGX_NOC_FW_L4_PER_SCR_NAND_REGISTER	0xffd21000
14 #define AGX_NOC_FW_L4_PER_SCR_NAND_DATA		0xffd21004
15 #define AGX_NOC_FW_L4_PER_SCR_USB0_REGISTER	0xffd2100c
16 #define AGX_NOC_FW_L4_PER_SCR_USB1_REGISTER	0xffd21010
17 #define AGX_NOC_FW_L4_PER_SCR_SPI_MASTER0	0xffd2101c
18 #define AGX_NOC_FW_L4_PER_SCR_SPI_MASTER1	0xffd21020
19 #define AGX_NOC_FW_L4_PER_SCR_SPI_SLAVE0	0xffd21024
20 #define AGX_NOC_FW_L4_PER_SCR_SPI_SLAVE1	0xffd21028
21 #define AGX_NOC_FW_L4_PER_SCR_EMAC0		0xffd2102c
22 #define AGX_NOC_FW_L4_PER_SCR_EMAC1		0xffd21030
23 #define AGX_NOC_FW_L4_PER_SCR_EMAC2		0xffd21034
24 #define AGX_NOC_FW_L4_PER_SCR_SDMMC		0xffd21040
25 #define AGX_NOC_FW_L4_PER_SCR_GPIO0		0xffd21044
26 #define AGX_NOC_FW_L4_PER_SCR_GPIO1		0xffd21048
27 #define AGX_NOC_FW_L4_PER_SCR_I2C0		0xffd21050
28 #define AGX_NOC_FW_L4_PER_SCR_I2C1		0xffd21054
29 #define AGX_NOC_FW_L4_PER_SCR_I2C2		0xffd21058
30 #define AGX_NOC_FW_L4_PER_SCR_I2C3		0xffd2105c
31 #define AGX_NOC_FW_L4_PER_SCR_I2C4		0xffd21060
32 #define AGX_NOC_FW_L4_PER_SCR_SP_TIMER0		0xffd21064
33 #define AGX_NOC_FW_L4_PER_SCR_SP_TIMER1		0xffd21068
34 #define AGX_NOC_FW_L4_PER_SCR_UART0		0xffd2106c
35 #define AGX_NOC_FW_L4_PER_SCR_UART1		0xffd21070
36 
37 #define AGX_NOC_FW_L4_SYS_SCR_DMA_ECC		0xffd21108
38 #define AGX_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC	0xffd2110c
39 #define AGX_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC	0xffd21110
40 #define AGX_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC	0xffd21114
41 #define AGX_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC	0xffd21118
42 #define AGX_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC	0xffd2111c
43 #define AGX_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC	0xffd21120
44 #define AGX_NOC_FW_L4_SYS_SCR_NAND_ECC		0xffd2112c
45 #define AGX_NOC_FW_L4_SYS_SCR_NAND_READ_ECC	0xffd21130
46 #define AGX_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC	0xffd21134
47 #define AGX_NOC_FW_L4_SYS_SCR_OCRAM_ECC		0xffd21138
48 #define AGX_NOC_FW_L4_SYS_SCR_SDMMC_ECC		0xffd21140
49 #define AGX_NOC_FW_L4_SYS_SCR_USB0_ECC		0xffd21144
50 #define AGX_NOC_FW_L4_SYS_SCR_USB1_ECC		0xffd21148
51 #define AGX_NOC_FW_L4_SYS_SCR_CLK_MGR		0xffd2114c
52 #define AGX_NOC_FW_L4_SYS_SCR_IO_MGR		0xffd21154
53 #define AGX_NOC_FW_L4_SYS_SCR_RST_MGR		0xffd21158
54 #define AGX_NOC_FW_L4_SYS_SCR_SYS_MGR		0xffd2115c
55 #define AGX_NOC_FW_L4_SYS_SCR_OSC0_TIMER	0xffd21160
56 #define AGX_NOC_FW_L4_SYS_SCR_OSC1_TIMER	0xffd21164
57 #define AGX_NOC_FW_L4_SYS_SCR_WATCHDOG0		0xffd21168
58 #define AGX_NOC_FW_L4_SYS_SCR_WATCHDOG1		0xffd2116c
59 #define AGX_NOC_FW_L4_SYS_SCR_WATCHDOG2		0xffd21170
60 #define AGX_NOC_FW_L4_SYS_SCR_WATCHDOG3		0xffd21174
61 #define AGX_NOC_FW_L4_SYS_SCR_DAP		0xffd21178
62 #define AGX_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES	0xffd21190
63 #define AGX_NOC_FW_L4_SYS_SCR_L4_NOC_QOS	0xffd21194
64 
65 #define AGX_CCU_NOC_CPU0_RAMSPACE0_0		0xf7004688
66 #define AGX_CCU_NOC_IOM_RAMSPACE0_0		0xf7018628
67 
68 #define AGX_SYSMGR_CORE(x)                      (0xffd12000 + (x))
69 
70 #define SYSMGR_BOOT_SCRATCH_COLD_0		0x200
71 #define SYSMGR_BOOT_SCRATCH_COLD_1		0x204
72 #define SYSMGR_BOOT_SCRATCH_COLD_2		0x208
73 
74 #define DISABLE_BRIDGE_FIREWALL			0x0ffe0101
75 #define DISABLE_L4_FIREWALL	(BIT(0) | BIT(16) | BIT(24))
76 
77 void enable_nonsecure_access(void);
78 void enable_ns_peripheral_access(void);
79 void enable_ns_bridge_access(void);
80 
81 #endif
82