1 /* 2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <arch.h> 9 #include <arch_helpers.h> 10 #include <assert.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <common/desc_image_load.h> 14 #include <drivers/generic_delay_timer.h> 15 #include <drivers/synopsys/dw_mmc.h> 16 #include <drivers/ti/uart/uart_16550.h> 17 #include <lib/xlat_tables/xlat_tables.h> 18 19 #include "agilex_mmc.h" 20 #include "agilex_clock_manager.h" 21 #include "agilex_memory_controller.h" 22 #include "agilex_pinmux.h" 23 #include "ccu/ncore_ccu.h" 24 #include "qspi/cadence_qspi.h" 25 #include "socfpga_emac.h" 26 #include "socfpga_f2sdram_manager.h" 27 #include "socfpga_handoff.h" 28 #include "socfpga_mailbox.h" 29 #include "socfpga_private.h" 30 #include "socfpga_reset_manager.h" 31 #include "socfpga_ros.h" 32 #include "socfpga_system_manager.h" 33 #include "wdt/watchdog.h" 34 35 static struct mmc_device_info mmc_info; 36 37 const mmap_region_t agilex_plat_mmap[] = { 38 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, 39 MT_MEMORY | MT_RW | MT_NS), 40 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, 41 MT_DEVICE | MT_RW | MT_NS), 42 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, 43 MT_DEVICE | MT_RW | MT_SECURE), 44 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, 45 MT_NON_CACHEABLE | MT_RW | MT_SECURE), 46 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE, 47 MT_DEVICE | MT_RW | MT_SECURE), 48 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, 49 MT_DEVICE | MT_RW | MT_NS), 50 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, 51 MT_DEVICE | MT_RW | MT_NS), 52 {0}, 53 }; 54 55 boot_source_type boot_source = BOOT_SOURCE; 56 57 void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, 58 u_register_t x2, u_register_t x4) 59 { 60 static console_t console; 61 handoff reverse_handoff_ptr; 62 63 generic_delay_timer_init(); 64 65 if (socfpga_get_handoff(&reverse_handoff_ptr)) 66 return; 67 config_pinmux(&reverse_handoff_ptr); 68 config_clkmgr_handoff(&reverse_handoff_ptr); 69 70 enable_nonsecure_access(); 71 deassert_peripheral_reset(); 72 config_hps_hs_before_warm_reset(); 73 74 watchdog_init(get_wdt_clk()); 75 76 console_16550_register(PLAT_INTEL_UART_BASE, get_uart_clk(), 77 PLAT_BAUDRATE, &console); 78 79 socfpga_delay_timer_init(); 80 init_ncore_ccu(); 81 socfpga_emac_init(); 82 init_hard_memory_controller(); 83 mailbox_init(); 84 agx_mmc_init(); 85 86 if (!intel_mailbox_is_fpga_not_ready()) { 87 socfpga_bridges_enable(SOC2FPGA_MASK | LWHPS2FPGA_MASK | 88 FPGA2SOC_MASK); 89 } 90 } 91 92 93 void bl2_el3_plat_arch_setup(void) 94 { 95 96 unsigned long offset = 0; 97 const mmap_region_t bl_regions[] = { 98 MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE, 99 MT_MEMORY | MT_RW | MT_SECURE), 100 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 101 MT_CODE | MT_SECURE), 102 MAP_REGION_FLAT(BL_RO_DATA_BASE, 103 BL_RO_DATA_END - BL_RO_DATA_BASE, 104 MT_RO_DATA | MT_SECURE), 105 #if USE_COHERENT_MEM_BAR 106 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 107 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 108 MT_DEVICE | MT_RW | MT_SECURE), 109 #endif 110 {0}, 111 }; 112 113 setup_page_tables(bl_regions, agilex_plat_mmap); 114 115 enable_mmu_el3(0); 116 117 dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000, get_mmc_clk()); 118 119 mmc_info.mmc_dev_type = MMC_IS_SD; 120 mmc_info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3; 121 122 /* Request ownership and direct access to QSPI */ 123 mailbox_hps_qspi_enable(); 124 125 switch (boot_source) { 126 case BOOT_SOURCE_SDMMC: 127 dw_mmc_init(¶ms, &mmc_info); 128 socfpga_io_setup(boot_source, PLAT_SDMMC_DATA_BASE); 129 break; 130 131 case BOOT_SOURCE_QSPI: 132 cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL, 133 QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS, 134 QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0); 135 if (ros_qspi_get_ssbl_offset(&offset) != ROS_RET_OK) { 136 offset = PLAT_QSPI_DATA_BASE; 137 } 138 socfpga_io_setup(boot_source, offset); 139 break; 140 141 default: 142 ERROR("Unsupported boot source\n"); 143 panic(); 144 break; 145 } 146 } 147 148 uint32_t get_spsr_for_bl33_entry(void) 149 { 150 unsigned long el_status; 151 unsigned int mode; 152 uint32_t spsr; 153 154 /* Figure out what mode we enter the non-secure world in */ 155 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 156 el_status &= ID_AA64PFR0_ELX_MASK; 157 158 mode = (el_status) ? MODE_EL2 : MODE_EL1; 159 160 /* 161 * TODO: Consider the possibility of specifying the SPSR in 162 * the FIP ToC and allowing the platform to have a say as 163 * well. 164 */ 165 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 166 return spsr; 167 } 168 169 170 int bl2_plat_handle_post_image_load(unsigned int image_id) 171 { 172 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 173 174 assert(bl_mem_params); 175 176 switch (image_id) { 177 case BL33_IMAGE_ID: 178 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 179 bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry(); 180 break; 181 default: 182 break; 183 } 184 185 return 0; 186 } 187 188 /******************************************************************************* 189 * Perform any BL3-1 platform setup code 190 ******************************************************************************/ 191 void bl2_platform_setup(void) 192 { 193 } 194 195