1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019, Intel Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <arch.h> 9 #include <arch_helpers.h> 10 #include <common/bl_common.h> 11 #include <common/debug.h> 12 #include <common/desc_image_load.h> 13 #include <drivers/generic_delay_timer.h> 14 #include <drivers/synopsys/dw_mmc.h> 15 #include <drivers/ti/uart/uart_16550.h> 16 #include <lib/xlat_tables/xlat_tables.h> 17 #include <platform_def.h> 18 #include <socfpga_private.h> 19 20 #include "agilex_clock_manager.h" 21 #include "agilex_handoff.h" 22 #include "agilex_mailbox.h" 23 #include "agilex_memory_controller.h" 24 #include "agilex_pinmux.h" 25 #include "agilex_private.h" 26 #include "agilex_reset_manager.h" 27 #include "agilex_system_manager.h" 28 29 #include "ccu/ncore_ccu.h" 30 #include "qspi/cadence_qspi.h" 31 #include "wdt/watchdog.h" 32 33 34 const mmap_region_t agilex_plat_mmap[] = { 35 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, 36 MT_MEMORY | MT_RW | MT_NS), 37 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, 38 MT_DEVICE | MT_RW | MT_NS), 39 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, 40 MT_DEVICE | MT_RW | MT_SECURE), 41 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, 42 MT_NON_CACHEABLE | MT_RW | MT_SECURE), 43 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE, 44 MT_DEVICE | MT_RW | MT_SECURE), 45 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, 46 MT_DEVICE | MT_RW | MT_NS), 47 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, 48 MT_DEVICE | MT_RW | MT_NS), 49 {0}, 50 }; 51 52 boot_source_type boot_source; 53 54 void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, 55 u_register_t x2, u_register_t x4) 56 { 57 static console_16550_t console; 58 handoff reverse_handoff_ptr; 59 60 generic_delay_timer_init(); 61 62 if (agilex_get_handoff(&reverse_handoff_ptr)) 63 return; 64 config_pinmux(&reverse_handoff_ptr); 65 boot_source = reverse_handoff_ptr.boot_source; 66 config_clkmgr_handoff(&reverse_handoff_ptr); 67 68 enable_nonsecure_access(); 69 deassert_peripheral_reset(); 70 config_hps_hs_before_warm_reset(); 71 72 watchdog_init(get_wdt_clk()); 73 74 console_16550_register(PLAT_UART0_BASE, get_uart_clk(), PLAT_BAUDRATE, 75 &console); 76 77 socfpga_delay_timer_init(); 78 init_ncore_ccu(); 79 init_hard_memory_controller(); 80 enable_ns_bridge_access(); 81 } 82 83 84 void bl2_el3_plat_arch_setup(void) 85 { 86 87 struct mmc_device_info info; 88 const mmap_region_t bl_regions[] = { 89 MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE, 90 MT_MEMORY | MT_RW | MT_SECURE), 91 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 92 MT_CODE | MT_SECURE), 93 MAP_REGION_FLAT(BL_RO_DATA_BASE, 94 BL_RO_DATA_END - BL_RO_DATA_BASE, 95 MT_RO_DATA | MT_SECURE), 96 #if USE_COHERENT_MEM_BAR 97 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 98 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 99 MT_DEVICE | MT_RW | MT_SECURE), 100 #endif 101 {0}, 102 }; 103 104 setup_page_tables(bl_regions, agilex_plat_mmap); 105 106 enable_mmu_el3(0); 107 108 dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000, get_mmc_clk()); 109 110 info.mmc_dev_type = MMC_IS_SD; 111 info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3; 112 113 mailbox_init(); 114 115 switch (boot_source) { 116 case BOOT_SOURCE_SDMMC: 117 dw_mmc_init(¶ms, &info); 118 socfpga_io_setup(boot_source); 119 break; 120 121 case BOOT_SOURCE_QSPI: 122 mailbox_set_qspi_open(); 123 mailbox_set_qspi_direct(); 124 cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL, 125 QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS, 126 QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0); 127 socfpga_io_setup(boot_source); 128 break; 129 130 default: 131 ERROR("Unsupported boot source\n"); 132 panic(); 133 break; 134 } 135 } 136 137 uint32_t get_spsr_for_bl33_entry(void) 138 { 139 unsigned long el_status; 140 unsigned int mode; 141 uint32_t spsr; 142 143 /* Figure out what mode we enter the non-secure world in */ 144 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 145 el_status &= ID_AA64PFR0_ELX_MASK; 146 147 mode = (el_status) ? MODE_EL2 : MODE_EL1; 148 149 /* 150 * TODO: Consider the possibility of specifying the SPSR in 151 * the FIP ToC and allowing the platform to have a say as 152 * well. 153 */ 154 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 155 return spsr; 156 } 157 158 159 int bl2_plat_handle_post_image_load(unsigned int image_id) 160 { 161 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 162 163 switch (image_id) { 164 case BL33_IMAGE_ID: 165 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 166 bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry(); 167 break; 168 default: 169 break; 170 } 171 172 return 0; 173 } 174 175 /******************************************************************************* 176 * Perform any BL3-1 platform setup code 177 ******************************************************************************/ 178 void bl2_platform_setup(void) 179 { 180 } 181 182