1 /* 2 * Copyright 2024-2025 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef IMX95_SCMI_DEF_H 8 #define IMX95_SCMI_DEF_H 9 10 #define IMR_NUM U(12) 11 #define IMX95_A55P_IDX 6U 12 13 #define IMX9_SCMI_CPU_A55C0 2U 14 #define IMX9_SCMI_CPU_A55C1 3U 15 #define IMX9_SCMI_CPU_A55C2 4U 16 #define IMX9_SCMI_CPU_A55C3 5U 17 #define IMX9_SCMI_CPU_A55C4 6U 18 #define IMX9_SCMI_CPU_A55C5 7U 19 #define IMX9_SCMI_CPU_A55P 8U 20 21 #define SCMI_PWR_MIX_SLICE_IDX_ANA 0U 22 #define SCMI_PWR_MIX_SLICE_IDX_AON 1U 23 #define SCMI_PWR_MIX_SLICE_IDX_BBSM 2U 24 #define SCMI_PWR_MIX_SLICE_IDX_CAMERA 3U 25 #define SCMI_PWR_MIX_SLICE_IDX_CCMSRCGPC 4U 26 #define SCMI_PWR_MIX_SLICE_IDX_A55C0 5U 27 #define SCMI_PWR_MIX_SLICE_IDX_A55C1 6U 28 #define SCMI_PWR_MIX_SLICE_IDX_A55C2 7U 29 #define SCMI_PWR_MIX_SLICE_IDX_A55C3 8U 30 #define SCMI_PWR_MIX_SLICE_IDX_A55C4 9U 31 #define SCMI_PWR_MIX_SLICE_IDX_A55C5 10U 32 #define SCMI_PWR_MIX_SLICE_IDX_A55P 11U 33 #define SCMI_PWR_MIX_SLICE_IDX_DDR 12U 34 #define SCMI_PWR_MIX_SLICE_IDX_DISPLAY 13U 35 #define SCMI_PWR_MIX_SLICE_IDX_GPU 14U 36 #define SCMI_PWR_MIX_SLICE_IDX_HSIO_TOP 15U 37 #define SCMI_PWR_MIX_SLICE_IDX_HSIO_WAON 16U 38 #define SCMI_PWR_MIX_SLICE_IDX_M7 17U 39 #define SCMI_PWR_MIX_SLICE_IDX_NETC 18U 40 #define SCMI_PWR_MIX_SLICE_IDX_NOC 19U 41 #define SCMI_PWR_MIX_SLICE_IDX_NPU 20U 42 #define SCMI_PWR_MIX_SLICE_IDX_VPU 21U 43 #define SCMI_PWR_MIX_SLICE_IDX_WAKEUP 22U 44 45 #define SCMI_PWR_MEM_SLICE_IDX_AON 0U 46 #define SCMI_PWR_MEM_SLICE_IDX_CAMERA 1U 47 #define SCMI_PWR_MEM_SLICE_IDX_A55C0 2U 48 #define SCMI_PWR_MEM_SLICE_IDX_A55C1 3U 49 #define SCMI_PWR_MEM_SLICE_IDX_A55C2 4U 50 #define SCMI_PWR_MEM_SLICE_IDX_A55C3 5U 51 #define SCMI_PWR_MEM_SLICE_IDX_A55C4 6U 52 #define SCMI_PWR_MEM_SLICE_IDX_A55C5 7U 53 #define SCMI_PWR_MEM_SLICE_IDX_A55P 8U 54 #define SCMI_PWR_MEM_SLICE_IDX_A55L3 9U 55 #define SCMI_PWR_MEM_SLICE_IDX_DDR 10U 56 #define SCMI_PWR_MEM_SLICE_IDX_DISPLAY 11U 57 #define SCMI_PWR_MEM_SLICE_IDX_GPU 12U 58 #define SCMI_PWR_MEM_SLICE_IDX_HSIO 13U 59 #define SCMI_PWR_MEM_SLICE_IDX_M7 14U 60 #define SCMI_PWR_MEM_SLICE_IDX_NETC 15U 61 #define SCMI_PWR_MEM_SLICE_IDX_NOC_OCRAM 16U 62 #define SCMI_PWR_MEM_SLICE_IDX_NOC2 17U 63 #define SCMI_PWR_MEM_SLICE_IDX_NPU 18U 64 #define SCMI_PWR_MEM_SLICE_IDX_VPU 19U 65 #define SCMI_PWR_MEM_SLICE_IDX_WAKEUP 20U 66 67 /* Peripheral LPI index */ 68 #define CPU_PER_LPI_IDX_GPIO1 0U 69 #define CPU_PER_LPI_IDX_GPIO2 1U 70 #define CPU_PER_LPI_IDX_GPIO3 2U 71 #define CPU_PER_LPI_IDX_GPIO4 3U 72 #define CPU_PER_LPI_IDX_GPIO5 4U 73 #define CPU_PER_LPI_IDX_CAN1 5U 74 #define CPU_PER_LPI_IDX_CAN2 6U 75 #define CPU_PER_LPI_IDX_CAN3 7U 76 #define CPU_PER_LPI_IDX_CAN4 8U 77 #define CPU_PER_LPI_IDX_CAN5 9U 78 #define CPU_PER_LPI_IDX_LPUART1 10U 79 #define CPU_PER_LPI_IDX_LPUART2 11U 80 #define CPU_PER_LPI_IDX_LPUART3 12U 81 #define CPU_PER_LPI_IDX_LPUART4 13U 82 #define CPU_PER_LPI_IDX_LPUART5 14U 83 #define CPU_PER_LPI_IDX_LPUART6 15U 84 #define CPU_PER_LPI_IDX_LPUART7 16U 85 #define CPU_PER_LPI_IDX_LPUART8 17U 86 #define CPU_PER_LPI_IDX_WDOG3 18U 87 #define CPU_PER_LPI_IDX_WDOG4 19U 88 #define CPU_PER_LPI_IDX_WDOG5 20U 89 90 91 #define DEBUG_WAKEUP_MASK BIT(1) 92 #define EVENT_WAKEUP_MASK BIT(0) 93 94 #endif /* IMX95_SCMI_DEF_H */ 95