1*4249a4fbSJacky Bai /* 2*4249a4fbSJacky Bai * Copyright 2025 NXP 3*4249a4fbSJacky Bai * 4*4249a4fbSJacky Bai * SPDX-License-Identifier: BSD-3-Clause 5*4249a4fbSJacky Bai */ 6*4249a4fbSJacky Bai 7*4249a4fbSJacky Bai #ifndef IMX94_SCMI_DEF_H 8*4249a4fbSJacky Bai #define IMX94_SCMI_DEF_H 9*4249a4fbSJacky Bai 10*4249a4fbSJacky Bai #define SCMI_PWR_MIX_SLICE_IDX_ANA 0U 11*4249a4fbSJacky Bai #define SCMI_PWR_MIX_SLICE_IDX_AON 1U 12*4249a4fbSJacky Bai #define SCMI_PWR_MIX_SLICE_IDX_BBSM 2U 13*4249a4fbSJacky Bai #define SCMI_PWR_MIX_SLICE_IDX_M7_1 3U 14*4249a4fbSJacky Bai #define SCMI_PWR_MIX_SLICE_IDX_CCMSRCGPC 4U 15*4249a4fbSJacky Bai #define SCMI_PWR_MIX_SLICE_IDX_A55C0 5U 16*4249a4fbSJacky Bai #define SCMI_PWR_MIX_SLICE_IDX_A55C1 6U 17*4249a4fbSJacky Bai #define SCMI_PWR_MIX_SLICE_IDX_A55C2 7U 18*4249a4fbSJacky Bai #define SCMI_PWR_MIX_SLICE_IDX_A55C3 8U 19*4249a4fbSJacky Bai #define SCMI_PWR_MIX_SLICE_IDX_A55P 9U 20*4249a4fbSJacky Bai #define SCMI_PWR_MIX_SLICE_IDX_DDR 10U 21*4249a4fbSJacky Bai #define SCMI_PWR_MIX_SLICE_IDX_DISPLAY 11U 22*4249a4fbSJacky Bai #define SCMI_PWR_MIX_SLICE_IDX_M7_0 12U 23*4249a4fbSJacky Bai #define SCMI_PWR_MIX_SLICE_IDX_HSIO_TOP 13U 24*4249a4fbSJacky Bai #define SCMI_PWR_MIX_SLICE_IDX_HSIO_WAON 14U 25*4249a4fbSJacky Bai #define SCMI_PWR_MIX_SLICE_IDX_NETC 15U 26*4249a4fbSJacky Bai #define SCMI_PWR_MIX_SLICE_IDX_NOC 16U 27*4249a4fbSJacky Bai #define SCMI_PWR_MIX_SLICE_IDX_NPU 17U 28*4249a4fbSJacky Bai #define SCMI_PWR_MIX_SLICE_IDX_WAKEUP 18U 29*4249a4fbSJacky Bai 30*4249a4fbSJacky Bai #define SCMI_PWR_MEM_SLICE_IDX_AON 0U 31*4249a4fbSJacky Bai #define SCMI_PWR_MEM_SLICE_IDX_M7_1 1U 32*4249a4fbSJacky Bai #define SCMI_PWR_MEM_SLICE_IDX_A55C0 2U 33*4249a4fbSJacky Bai #define SCMI_PWR_MEM_SLICE_IDX_A55C1 3U 34*4249a4fbSJacky Bai #define SCMI_PWR_MEM_SLICE_IDX_A55C2 4U 35*4249a4fbSJacky Bai #define SCMI_PWR_MEM_SLICE_IDX_A55C3 5U 36*4249a4fbSJacky Bai #define SCMI_PWR_MEM_SLICE_IDX_A55P 6U 37*4249a4fbSJacky Bai #define SCMI_PWR_MEM_SLICE_IDX_A55L3 7U 38*4249a4fbSJacky Bai #define SCMI_PWR_MEM_SLICE_IDX_DDR 8U 39*4249a4fbSJacky Bai #define SCMI_PWR_MEM_SLICE_IDX_DISPLAY 9U 40*4249a4fbSJacky Bai #define SCMI_PWR_MEM_SLICE_IDX_M7_0 10U 41*4249a4fbSJacky Bai #define SCMI_PWR_MEM_SLICE_IDX_HSIO 11U 42*4249a4fbSJacky Bai #define SCMI_PWR_MEM_SLICE_IDX_NETC 12U 43*4249a4fbSJacky Bai #define SCMI_PWR_MEM_SLICE_IDX_NOC_OCRAM 13U 44*4249a4fbSJacky Bai #define SCMI_PWR_MEM_SLICE_IDX_NOC2 14U 45*4249a4fbSJacky Bai #define SCMI_PWR_MEM_SLICE_IDX_NPU 15U 46*4249a4fbSJacky Bai #define SCMI_PWR_MEM_SLICE_IDX_WAKEUP 16U 47*4249a4fbSJacky Bai 48*4249a4fbSJacky Bai #define CPU_PER_LPI_IDX_GPIO1 0U 49*4249a4fbSJacky Bai #define CPU_PER_LPI_IDX_GPIO2 1U 50*4249a4fbSJacky Bai #define CPU_PER_LPI_IDX_GPIO3 2U 51*4249a4fbSJacky Bai #define CPU_PER_LPI_IDX_GPIO4 3U 52*4249a4fbSJacky Bai #define CPU_PER_LPI_IDX_GPIO5 4U 53*4249a4fbSJacky Bai #define CPU_PER_LPI_IDX_GPIO6 5U 54*4249a4fbSJacky Bai #define CPU_PER_LPI_IDX_GPIO7 6U 55*4249a4fbSJacky Bai #define CPU_PER_LPI_IDX_CAN1 7U 56*4249a4fbSJacky Bai #define CPU_PER_LPI_IDX_CAN2 8U 57*4249a4fbSJacky Bai #define CPU_PER_LPI_IDX_CAN3 9U 58*4249a4fbSJacky Bai #define CPU_PER_LPI_IDX_CAN4 10U 59*4249a4fbSJacky Bai #define CPU_PER_LPI_IDX_CAN5 11U 60*4249a4fbSJacky Bai #define CPU_PER_LPI_IDX_LPUART1 12U 61*4249a4fbSJacky Bai #define CPU_PER_LPI_IDX_LPUART2 13U 62*4249a4fbSJacky Bai #define CPU_PER_LPI_IDX_LPUART3 14U 63*4249a4fbSJacky Bai #define CPU_PER_LPI_IDX_LPUART4 15U 64*4249a4fbSJacky Bai #define CPU_PER_LPI_IDX_LPUART5 16U 65*4249a4fbSJacky Bai #define CPU_PER_LPI_IDX_LPUART6 17U 66*4249a4fbSJacky Bai #define CPU_PER_LPI_IDX_LPUART7 18U 67*4249a4fbSJacky Bai #define CPU_PER_LPI_IDX_LPUART8 19U 68*4249a4fbSJacky Bai #define CPU_PER_LPI_IDX_LPUART9 20U 69*4249a4fbSJacky Bai #define CPU_PER_LPI_IDX_LPUART10 21U 70*4249a4fbSJacky Bai #define CPU_PER_LPI_IDX_LPUART11 22U 71*4249a4fbSJacky Bai #define CPU_PER_LPI_IDX_LPUART12 23U 72*4249a4fbSJacky Bai #define CPU_PER_LPI_IDX_WDOG3 24U 73*4249a4fbSJacky Bai #define CPU_PER_LPI_IDX_WDOG4 25U 74*4249a4fbSJacky Bai #define CPU_PER_LPI_IDX_WDOG5 26U 75*4249a4fbSJacky Bai #define CPU_PER_LPI_IDX_WDOG6 27U 76*4249a4fbSJacky Bai #define CPU_PER_LPI_IDX_WDOG7 28U 77*4249a4fbSJacky Bai #define CPU_PER_LPI_IDX_WDOG8 29U 78*4249a4fbSJacky Bai 79*4249a4fbSJacky Bai #define IMX9_A55P_IDX 4U 80*4249a4fbSJacky Bai 81*4249a4fbSJacky Bai #define IMX9_SCMI_CPU_A55C0 2U 82*4249a4fbSJacky Bai #define IMX9_SCMI_CPU_A55C1 3U 83*4249a4fbSJacky Bai #define IMX9_SCMI_CPU_A55C2 4U 84*4249a4fbSJacky Bai #define IMX9_SCMI_CPU_A55C3 5U 85*4249a4fbSJacky Bai #define IMX9_SCMI_CPU_A55P 6U 86*4249a4fbSJacky Bai 87*4249a4fbSJacky Bai #define DEBUG_WAKEUP_MASK BIT(1) 88*4249a4fbSJacky Bai #define EVENT_WAKEUP_MASK BIT(0) 89*4249a4fbSJacky Bai 90*4249a4fbSJacky Bai #endif /* IMX94_SCMI_DEF_H */ 91