1 /* 2 * Copyright 2025 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef IMX94_SCMI_DEF_H 8 #define IMX94_SCMI_DEF_H 9 10 #define SCMI_PWR_MIX_SLICE_IDX_ANA 0U 11 #define SCMI_PWR_MIX_SLICE_IDX_AON 1U 12 #define SCMI_PWR_MIX_SLICE_IDX_BBSM 2U 13 #define SCMI_PWR_MIX_SLICE_IDX_M7_1 3U 14 #define SCMI_PWR_MIX_SLICE_IDX_CCMSRCGPC 4U 15 #define SCMI_PWR_MIX_SLICE_IDX_A55C0 5U 16 #define SCMI_PWR_MIX_SLICE_IDX_A55C1 6U 17 #define SCMI_PWR_MIX_SLICE_IDX_A55C2 7U 18 #define SCMI_PWR_MIX_SLICE_IDX_A55C3 8U 19 #define SCMI_PWR_MIX_SLICE_IDX_A55P 9U 20 #define SCMI_PWR_MIX_SLICE_IDX_DDR 10U 21 #define SCMI_PWR_MIX_SLICE_IDX_DISPLAY 11U 22 #define SCMI_PWR_MIX_SLICE_IDX_M7_0 12U 23 #define SCMI_PWR_MIX_SLICE_IDX_HSIO_TOP 13U 24 #define SCMI_PWR_MIX_SLICE_IDX_HSIO_WAON 14U 25 #define SCMI_PWR_MIX_SLICE_IDX_NETC 15U 26 #define SCMI_PWR_MIX_SLICE_IDX_NOC 16U 27 #define SCMI_PWR_MIX_SLICE_IDX_NPU 17U 28 #define SCMI_PWR_MIX_SLICE_IDX_WAKEUP 18U 29 30 #define SCMI_PWR_MEM_SLICE_IDX_AON 0U 31 #define SCMI_PWR_MEM_SLICE_IDX_M7_1 1U 32 #define SCMI_PWR_MEM_SLICE_IDX_A55C0 2U 33 #define SCMI_PWR_MEM_SLICE_IDX_A55C1 3U 34 #define SCMI_PWR_MEM_SLICE_IDX_A55C2 4U 35 #define SCMI_PWR_MEM_SLICE_IDX_A55C3 5U 36 #define SCMI_PWR_MEM_SLICE_IDX_A55P 6U 37 #define SCMI_PWR_MEM_SLICE_IDX_A55L3 7U 38 #define SCMI_PWR_MEM_SLICE_IDX_DDR 8U 39 #define SCMI_PWR_MEM_SLICE_IDX_DISPLAY 9U 40 #define SCMI_PWR_MEM_SLICE_IDX_M7_0 10U 41 #define SCMI_PWR_MEM_SLICE_IDX_HSIO 11U 42 #define SCMI_PWR_MEM_SLICE_IDX_NETC 12U 43 #define SCMI_PWR_MEM_SLICE_IDX_NOC_OCRAM 13U 44 #define SCMI_PWR_MEM_SLICE_IDX_NOC2 14U 45 #define SCMI_PWR_MEM_SLICE_IDX_NPU 15U 46 #define SCMI_PWR_MEM_SLICE_IDX_WAKEUP 16U 47 48 #define CPU_PER_LPI_IDX_GPIO1 0U 49 #define CPU_PER_LPI_IDX_GPIO2 1U 50 #define CPU_PER_LPI_IDX_GPIO3 2U 51 #define CPU_PER_LPI_IDX_GPIO4 3U 52 #define CPU_PER_LPI_IDX_GPIO5 4U 53 #define CPU_PER_LPI_IDX_GPIO6 5U 54 #define CPU_PER_LPI_IDX_GPIO7 6U 55 #define CPU_PER_LPI_IDX_CAN1 7U 56 #define CPU_PER_LPI_IDX_CAN2 8U 57 #define CPU_PER_LPI_IDX_CAN3 9U 58 #define CPU_PER_LPI_IDX_CAN4 10U 59 #define CPU_PER_LPI_IDX_CAN5 11U 60 #define CPU_PER_LPI_IDX_LPUART1 12U 61 #define CPU_PER_LPI_IDX_LPUART2 13U 62 #define CPU_PER_LPI_IDX_LPUART3 14U 63 #define CPU_PER_LPI_IDX_LPUART4 15U 64 #define CPU_PER_LPI_IDX_LPUART5 16U 65 #define CPU_PER_LPI_IDX_LPUART6 17U 66 #define CPU_PER_LPI_IDX_LPUART7 18U 67 #define CPU_PER_LPI_IDX_LPUART8 19U 68 #define CPU_PER_LPI_IDX_LPUART9 20U 69 #define CPU_PER_LPI_IDX_LPUART10 21U 70 #define CPU_PER_LPI_IDX_LPUART11 22U 71 #define CPU_PER_LPI_IDX_LPUART12 23U 72 #define CPU_PER_LPI_IDX_WDOG3 24U 73 #define CPU_PER_LPI_IDX_WDOG4 25U 74 #define CPU_PER_LPI_IDX_WDOG5 26U 75 #define CPU_PER_LPI_IDX_WDOG6 27U 76 #define CPU_PER_LPI_IDX_WDOG7 28U 77 #define CPU_PER_LPI_IDX_WDOG8 29U 78 79 #define IMX9_A55P_IDX 4U 80 81 #define IMX9_SCMI_CPU_A55C0 2U 82 #define IMX9_SCMI_CPU_A55C1 3U 83 #define IMX9_SCMI_CPU_A55C2 4U 84 #define IMX9_SCMI_CPU_A55C3 5U 85 #define IMX9_SCMI_CPU_A55P 6U 86 87 #define DEBUG_WAKEUP_MASK BIT(1) 88 #define EVENT_WAKEUP_MASK BIT(0) 89 90 #endif /* IMX94_SCMI_DEF_H */ 91