1c71793c6SJacky Bai /* 25277c096SJacky Bai * Copyright 2019-2023 NXP 3c71793c6SJacky Bai * 4c71793c6SJacky Bai * SPDX-License-Identifier: BSD-3-Clause 5c71793c6SJacky Bai */ 6c71793c6SJacky Bai 7c71793c6SJacky Bai #ifndef DRAM_H 8c71793c6SJacky Bai #define DRAM_H 9c71793c6SJacky Bai 10c71793c6SJacky Bai #include <assert.h> 11c71793c6SJacky Bai 12c71793c6SJacky Bai #include <arch_helpers.h> 13c71793c6SJacky Bai #include <lib/utils_def.h> 14c71793c6SJacky Bai 15c71793c6SJacky Bai #include <ddrc.h> 16c71793c6SJacky Bai #include <platform_def.h> 17c71793c6SJacky Bai 18c71793c6SJacky Bai #define DDRC_LPDDR4 BIT(5) 19c71793c6SJacky Bai #define DDRC_DDR4 BIT(4) 20c71793c6SJacky Bai #define DDRC_DDR3L BIT(0) 21c71793c6SJacky Bai #define DDR_TYPE_MASK U(0x3f) 22c71793c6SJacky Bai #define ACTIVE_RANK_MASK U(0x3) 235277c096SJacky Bai #define DDRC_ACTIVE_ONE_RANK U(0x1) 245277c096SJacky Bai #define DDRC_ACTIVE_TWO_RANK U(0x2) 25c71793c6SJacky Bai 26*a2655f48SJacky Bai #define MR12 U(12) 27*a2655f48SJacky Bai #define MR14 U(14) 28*a2655f48SJacky Bai 290331b1c6SJacky Bai #define MAX_FSP_NUM U(3) 300331b1c6SJacky Bai 31c71793c6SJacky Bai /* reg & config param */ 32c71793c6SJacky Bai struct dram_cfg_param { 33c71793c6SJacky Bai unsigned int reg; 34c71793c6SJacky Bai unsigned int val; 35c71793c6SJacky Bai }; 36c71793c6SJacky Bai 37c71793c6SJacky Bai struct dram_timing_info { 38c71793c6SJacky Bai /* umctl2 config */ 39c71793c6SJacky Bai struct dram_cfg_param *ddrc_cfg; 40c71793c6SJacky Bai unsigned int ddrc_cfg_num; 41c71793c6SJacky Bai /* ddrphy config */ 42c71793c6SJacky Bai struct dram_cfg_param *ddrphy_cfg; 43c71793c6SJacky Bai unsigned int ddrphy_cfg_num; 44c71793c6SJacky Bai /* ddr fsp train info */ 45c71793c6SJacky Bai struct dram_fsp_msg *fsp_msg; 46c71793c6SJacky Bai unsigned int fsp_msg_num; 47c71793c6SJacky Bai /* ddr phy trained CSR */ 48c71793c6SJacky Bai struct dram_cfg_param *ddrphy_trained_csr; 49c71793c6SJacky Bai unsigned int ddrphy_trained_csr_num; 50c71793c6SJacky Bai /* ddr phy PIE */ 51c71793c6SJacky Bai struct dram_cfg_param *ddrphy_pie; 52c71793c6SJacky Bai unsigned int ddrphy_pie_num; 53c71793c6SJacky Bai /* initialized fsp table */ 54c71793c6SJacky Bai unsigned int fsp_table[4]; 55c71793c6SJacky Bai }; 56c71793c6SJacky Bai 57c71793c6SJacky Bai struct dram_info { 58c71793c6SJacky Bai int dram_type; 59c71793c6SJacky Bai unsigned int num_rank; 609c336f61SJacky Bai uint32_t num_fsp; 61c71793c6SJacky Bai int current_fsp; 62c71793c6SJacky Bai int boot_fsp; 639c336f61SJacky Bai bool bypass_mode; 64c71793c6SJacky Bai struct dram_timing_info *timing_info; 659c336f61SJacky Bai /* mr, emr, emr2, emr3, mr11, mr12, mr22, mr14 */ 669c336f61SJacky Bai uint32_t mr_table[3][8]; 6733300849SJacky Bai /* used for workaround for rank to rank issue */ 6833300849SJacky Bai uint32_t rank_setting[3][3]; 69c71793c6SJacky Bai }; 70c71793c6SJacky Bai 71c71793c6SJacky Bai extern struct dram_info dram_info; 72c71793c6SJacky Bai 73c71793c6SJacky Bai void dram_info_init(unsigned long dram_timing_base); 74c71793c6SJacky Bai void dram_umctl2_init(struct dram_timing_info *timing); 75c71793c6SJacky Bai void dram_phy_init(struct dram_timing_info *timing); 76c71793c6SJacky Bai 77c71793c6SJacky Bai /* dram retention */ 78c71793c6SJacky Bai void dram_enter_retention(void); 79c71793c6SJacky Bai void dram_exit_retention(void); 80c71793c6SJacky Bai 819c336f61SJacky Bai void dram_clock_switch(unsigned int target_drate, bool bypass_mode); 829c336f61SJacky Bai 839c336f61SJacky Bai /* dram frequency change */ 849c336f61SJacky Bai void lpddr4_swffc(struct dram_info *info, unsigned int init_fsp, unsigned int fsp_index); 859c336f61SJacky Bai void ddr4_swffc(struct dram_info *dram_info, unsigned int pstate); 869c336f61SJacky Bai 87c71793c6SJacky Bai #endif /* DRAM_H */ 88