1 /* 2 * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <plat/common/common_def.h> 8 9 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 10 #define PLATFORM_LINKER_ARCH aarch64 11 12 #define PLATFORM_STACK_SIZE 0x800 13 #define CACHE_WRITEBACK_GRANULE 64 14 15 #define PLAT_PRIMARY_CPU U(0x0) 16 #define PLATFORM_MAX_CPU_PER_CLUSTER U(4) 17 #define PLATFORM_CLUSTER_COUNT U(1) 18 #define PLATFORM_CLUSTER0_CORE_COUNT U(4) 19 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 20 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 21 22 #define IMX_PWR_LVL0 MPIDR_AFFLVL0 23 #define IMX_PWR_LVL1 MPIDR_AFFLVL1 24 #define IMX_PWR_LVL2 MPIDR_AFFLVL2 25 26 #define PWR_DOMAIN_AT_MAX_LVL U(1) 27 #define PLAT_MAX_PWR_LVL U(2) 28 #define PLAT_MAX_OFF_STATE U(4) 29 #define PLAT_MAX_RET_STATE U(1) 30 31 #define PLAT_WAIT_RET_STATE PLAT_MAX_RET_STATE 32 #define PLAT_WAIT_OFF_STATE U(2) 33 #define PLAT_STOP_OFF_STATE U(3) 34 35 #define BL31_BASE U(0x910000) 36 #define BL31_SIZE SZ_64K 37 #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 38 39 /* non-secure uboot base */ 40 #define PLAT_NS_IMAGE_OFFSET U(0x40200000) 41 #define BL32_FDT_OVERLAY_ADDR (PLAT_NS_IMAGE_OFFSET + 0x3000000) 42 43 /* GICv3 base address */ 44 #define PLAT_GICD_BASE U(0x38800000) 45 #define PLAT_GICR_BASE U(0x38880000) 46 47 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 48 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 49 50 #ifdef SPD_trusty 51 #define MAX_XLAT_TABLES 5 52 #define MAX_MMAP_REGIONS 15 53 #else 54 #define MAX_XLAT_TABLES 4 55 #define MAX_MMAP_REGIONS 14 56 #endif 57 58 #define HAB_RVT_BASE U(0x00000880) /* HAB_RVT for i.MX8MQ */ 59 60 #define IMX_BOOT_UART_CLK_IN_HZ 25000000 /* Select 25Mhz oscillator */ 61 #define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE 62 #define PLAT_CRASH_UART_CLK_IN_HZ 25000000 63 #define IMX_CONSOLE_BAUDRATE 115200 64 65 #define IMX_AIPS_BASE U(0x30200000) 66 #define IMX_AIPS_SIZE U(0xC00000) 67 #define IMX_AIPS1_BASE U(0x30200000) 68 #define IMX_AIPS3_ARB_BASE U(0x30800000) 69 #define IMX_OCOTP_BASE U(0x30350000) 70 #define IMX_ANAMIX_BASE U(0x30360000) 71 #define IMX_CCM_BASE U(0x30380000) 72 #define IMX_SRC_BASE U(0x30390000) 73 #define IMX_GPC_BASE U(0x303a0000) 74 #define IMX_RDC_BASE U(0x303d0000) 75 #define IMX_CSU_BASE U(0x303e0000) 76 #define IMX_WDOG_BASE U(0x30280000) 77 #define IMX_SNVS_BASE U(0x30370000) 78 #define IMX_NOC_BASE U(0x32700000) 79 #define IMX_TZASC_BASE U(0x32F80000) 80 #define IMX_CAAM_BASE U(0x30900000) 81 #define IMX_IOMUX_GPR_BASE U(0x30340000) 82 #define IMX_DDRC_BASE U(0x3d400000) 83 #define IMX_DDRPHY_BASE U(0x3c000000) 84 #define IMX_DDR_IPS_BASE U(0x3d000000) 85 86 #define IMX_ROM_BASE U(0x00000000) 87 #define IMX_ROM_SIZE U(0x20000) 88 89 #define AIPSTZ1_BASE U(0x301f0000) 90 #define AIPSTZ2_BASE U(0x305f0000) 91 #define AIPSTZ3_BASE U(0x309f0000) 92 #define AIPSTZ4_BASE U(0x32df0000) 93 94 #define GPV_BASE U(0x32000000) 95 #define GPV_SIZE U(0x800000) 96 #define IMX_GIC_BASE PLAT_GICD_BASE 97 #define IMX_GIC_SIZE U(0x200000) 98 99 #define WDOG_WSR U(0x2) 100 #define WDOG_WCR_WDZST BIT(0) 101 #define WDOG_WCR_WDBG BIT(1) 102 #define WDOG_WCR_WDE BIT(2) 103 #define WDOG_WCR_WDT BIT(3) 104 #define WDOG_WCR_SRS BIT(4) 105 #define WDOG_WCR_WDA BIT(5) 106 #define WDOG_WCR_SRE BIT(6) 107 #define WDOG_WCR_WDW BIT(7) 108 109 #define SRC_A53RCR0 U(0x4) 110 #define SRC_A53RCR1 U(0x8) 111 #define SRC_OTG1PHY_SCR U(0x20) 112 #define SRC_OTG2PHY_SCR U(0x24) 113 #define SRC_GPR1_OFFSET U(0x74) 114 #define SRC_GPR10_OFFSET U(0x98) 115 #define SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30) 116 117 #define SNVS_LPCR U(0x38) 118 #define SNVS_LPCR_SRTC_ENV BIT(0) 119 #define SNVS_LPCR_DP_EN BIT(5) 120 #define SNVS_LPCR_TOP BIT(6) 121 122 123 #define IOMUXC_GPR10 U(0x28) 124 #define GPR_TZASC_EN BIT(0) 125 #define GPR_TZASC_EN_LOCK BIT(16) 126 127 #define OCRAM_S_BASE U(0x00180000) 128 #define OCRAM_S_SIZE U(0x8000) 129 #define OCRAM_S_LIMIT (OCRAM_S_BASE + OCRAM_S_SIZE) 130 131 #define COUNTER_FREQUENCY 8333333 /* 25MHz / 3 */ 132 133 #define IMX_WDOG_B_RESET 134