1 /* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <drivers/arm/tzc380.h> 17 #include <drivers/console.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/mmio.h> 21 #include <lib/xlat_tables/xlat_tables.h> 22 #include <plat/common/platform.h> 23 24 #include <gpc.h> 25 #include <imx_aipstz.h> 26 #include <imx_uart.h> 27 #include <plat_imx8.h> 28 29 static const mmap_region_t imx_mmap[] = { 30 MAP_REGION_FLAT(GPV_BASE, GPV_SIZE, MT_DEVICE | MT_RW), /* GPV map */ 31 MAP_REGION_FLAT(IMX_ROM_BASE, IMX_ROM_SIZE, MT_MEMORY | MT_RO), /* ROM map */ 32 MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */ 33 MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), /* GIC map */ 34 {0}, 35 }; 36 37 static const struct aipstz_cfg aipstz[] = { 38 {AIPSTZ1_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 39 {AIPSTZ2_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 40 {AIPSTZ3_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 41 {AIPSTZ4_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 42 {0}, 43 }; 44 45 static entry_point_info_t bl32_image_ep_info; 46 static entry_point_info_t bl33_image_ep_info; 47 48 static uint32_t imx_soc_revision; 49 50 int imx_soc_info_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, 51 u_register_t x3) 52 { 53 return imx_soc_revision; 54 } 55 56 #define ANAMIX_DIGPROG 0x6c 57 #define ROM_SOC_INFO_A0 0x800 58 #define ROM_SOC_INFO_B0 0x83C 59 #define OCOTP_SOC_INFO_B1 0x40 60 61 static void imx8mq_soc_info_init(void) 62 { 63 uint32_t rom_version; 64 uint32_t ocotp_val; 65 66 imx_soc_revision = mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_DIGPROG); 67 rom_version = mmio_read_8(IMX_ROM_BASE + ROM_SOC_INFO_A0); 68 if (rom_version == 0x10) 69 return; 70 71 rom_version = mmio_read_8(IMX_ROM_BASE + ROM_SOC_INFO_B0); 72 if (rom_version == 0x20) { 73 imx_soc_revision &= ~0xff; 74 imx_soc_revision |= rom_version; 75 return; 76 } 77 78 /* 0xff0055aa is magic number for B1 */ 79 ocotp_val = mmio_read_32(IMX_OCOTP_BASE + OCOTP_SOC_INFO_B1); 80 if (ocotp_val == 0xff0055aa) { 81 imx_soc_revision &= ~0xff; 82 imx_soc_revision |= 0x21; 83 return; 84 } 85 } 86 87 /* get SPSR for BL33 entry */ 88 static uint32_t get_spsr_for_bl33_entry(void) 89 { 90 unsigned long el_status; 91 unsigned long mode; 92 uint32_t spsr; 93 94 /* figure out what mode we enter the non-secure world */ 95 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 96 el_status &= ID_AA64PFR0_ELX_MASK; 97 98 mode = (el_status) ? MODE_EL2 : MODE_EL1; 99 100 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 101 return spsr; 102 } 103 104 static void bl31_tz380_setup(void) 105 { 106 unsigned int val; 107 108 val = mmio_read_32(IMX_IOMUX_GPR_BASE + IOMUXC_GPR10); 109 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 110 return; 111 112 tzc380_init(IMX_TZASC_BASE); 113 /* 114 * Need to substact offset 0x40000000 from CPU address when 115 * programming tzasc region for i.mx8mq. Enable 1G-5G S/NS RW 116 */ 117 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 118 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 119 } 120 121 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 122 u_register_t arg2, u_register_t arg3) 123 { 124 int i; 125 /* enable CSU NS access permission */ 126 for (i = 0; i < 64; i++) { 127 mmio_write_32(IMX_CSU_BASE + i * 4, 0xffffffff); 128 } 129 130 imx_aipstz_init(aipstz); 131 132 /* config CAAM JRaMID set MID to Cortex A */ 133 mmio_write_32(CAAM_JR0MID, CAAM_NS_MID); 134 mmio_write_32(CAAM_JR1MID, CAAM_NS_MID); 135 mmio_write_32(CAAM_JR2MID, CAAM_NS_MID); 136 137 #if DEBUG_CONSOLE 138 static console_uart_t console; 139 140 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 141 IMX_CONSOLE_BAUDRATE, &console); 142 #endif 143 /* 144 * tell BL3-1 where the non-secure software image is located 145 * and the entry state information. 146 */ 147 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 148 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 149 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 150 151 bl31_tz380_setup(); 152 } 153 154 void bl31_plat_arch_setup(void) 155 { 156 mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE), 157 MT_MEMORY | MT_RW | MT_SECURE); 158 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE), 159 MT_MEMORY | MT_RO | MT_SECURE); 160 161 mmap_add(imx_mmap); 162 163 #if USE_COHERENT_MEM 164 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, 165 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 166 MT_DEVICE | MT_RW | MT_SECURE); 167 #endif 168 /* setup xlat table */ 169 init_xlat_tables(); 170 /* enable the MMU */ 171 enable_mmu_el3(0); 172 } 173 174 void bl31_platform_setup(void) 175 { 176 generic_delay_timer_init(); 177 178 /* init the GICv3 cpu and distributor interface */ 179 plat_gic_driver_init(); 180 plat_gic_init(); 181 182 /* determine SOC revision for erratas */ 183 imx8mq_soc_info_init(); 184 185 /* gpc init */ 186 imx_gpc_init(); 187 } 188 189 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 190 { 191 if (type == NON_SECURE) 192 return &bl33_image_ep_info; 193 if (type == SECURE) 194 return &bl32_image_ep_info; 195 196 return NULL; 197 } 198 199 unsigned int plat_get_syscnt_freq2(void) 200 { 201 return COUNTER_FREQUENCY; 202 } 203 204 void bl31_plat_runtime_setup(void) 205 { 206 return; 207 } 208