1 /* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <drivers/arm/tzc380.h> 17 #include <drivers/console.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/mmio.h> 21 #include <lib/xlat_tables/xlat_tables.h> 22 #include <plat/common/platform.h> 23 24 #include <gpc.h> 25 #include <imx_aipstz.h> 26 #include <imx_uart.h> 27 #include <plat_imx8.h> 28 29 static const mmap_region_t imx_mmap[] = { 30 MAP_REGION_FLAT(GPV_BASE, GPV_SIZE, MT_DEVICE | MT_RW), /* GPV map */ 31 MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */ 32 MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), /* GIC map */ 33 {0}, 34 }; 35 36 static const struct aipstz_cfg aipstz[] = { 37 {AIPSTZ1_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 38 {AIPSTZ2_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 39 {AIPSTZ3_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 40 {AIPSTZ4_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 41 {0}, 42 }; 43 44 static entry_point_info_t bl32_image_ep_info; 45 static entry_point_info_t bl33_image_ep_info; 46 47 /* get SPSR for BL33 entry */ 48 static uint32_t get_spsr_for_bl33_entry(void) 49 { 50 unsigned long el_status; 51 unsigned long mode; 52 uint32_t spsr; 53 54 /* figure out what mode we enter the non-secure world */ 55 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 56 el_status &= ID_AA64PFR0_ELX_MASK; 57 58 mode = (el_status) ? MODE_EL2 : MODE_EL1; 59 60 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 61 return spsr; 62 } 63 64 static void bl31_tz380_setup(void) 65 { 66 unsigned int val; 67 68 val = mmio_read_32(IMX_IOMUX_GPR_BASE + IOMUXC_GPR10); 69 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 70 return; 71 72 tzc380_init(IMX_TZASC_BASE); 73 /* 74 * Need to substact offset 0x40000000 from CPU address when 75 * programming tzasc region for i.mx8mq. Enable 1G-5G S/NS RW 76 */ 77 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 78 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 79 } 80 81 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 82 u_register_t arg2, u_register_t arg3) 83 { 84 int i; 85 /* enable CSU NS access permission */ 86 for (i = 0; i < 64; i++) { 87 mmio_write_32(IMX_CSU_BASE + i * 4, 0xffffffff); 88 } 89 90 imx_aipstz_init(aipstz); 91 92 /* config CAAM JRaMID set MID to Cortex A */ 93 mmio_write_32(CAAM_JR0MID, CAAM_NS_MID); 94 mmio_write_32(CAAM_JR1MID, CAAM_NS_MID); 95 mmio_write_32(CAAM_JR2MID, CAAM_NS_MID); 96 97 #if DEBUG_CONSOLE 98 static console_uart_t console; 99 100 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 101 IMX_CONSOLE_BAUDRATE, &console); 102 #endif 103 /* 104 * tell BL3-1 where the non-secure software image is located 105 * and the entry state information. 106 */ 107 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 108 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 109 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 110 111 bl31_tz380_setup(); 112 } 113 114 void bl31_plat_arch_setup(void) 115 { 116 mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE), 117 MT_MEMORY | MT_RW | MT_SECURE); 118 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE), 119 MT_MEMORY | MT_RO | MT_SECURE); 120 121 mmap_add(imx_mmap); 122 123 #if USE_COHERENT_MEM 124 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, 125 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 126 MT_DEVICE | MT_RW | MT_SECURE); 127 #endif 128 /* setup xlat table */ 129 init_xlat_tables(); 130 /* enable the MMU */ 131 enable_mmu_el3(0); 132 } 133 134 void bl31_platform_setup(void) 135 { 136 generic_delay_timer_init(); 137 138 /* init the GICv3 cpu and distributor interface */ 139 plat_gic_driver_init(); 140 plat_gic_init(); 141 142 /* gpc init */ 143 imx_gpc_init(); 144 } 145 146 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 147 { 148 if (type == NON_SECURE) 149 return &bl33_image_ep_info; 150 if (type == SECURE) 151 return &bl32_image_ep_info; 152 153 return NULL; 154 } 155 156 unsigned int plat_get_syscnt_freq2(void) 157 { 158 return COUNTER_FREQUENCY; 159 } 160 161 void bl31_plat_runtime_setup(void) 162 { 163 return; 164 } 165