1 /* 2 * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <drivers/arm/tzc380.h> 17 #include <drivers/console.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/mmio.h> 21 #include <lib/xlat_tables/xlat_tables_v2.h> 22 #include <plat/common/platform.h> 23 24 #include <dram.h> 25 #include <gpc.h> 26 #include <imx_aipstz.h> 27 #include <imx_uart.h> 28 #include <imx8m_caam.h> 29 #include <plat_imx8.h> 30 31 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 32 33 /* 34 * Avoid the pointer dereference of the canonical mmio_read_8() implementation. 35 * This prevents the compiler from mis-interpreting the MMIO access as an 36 * illegal memory access to a very low address (the IMX ROM is mapped at 0). 37 */ 38 static uint8_t mmio_read_8_ldrb(uintptr_t address) 39 { 40 uint8_t reg; 41 42 __asm__ volatile ("ldrb %w0, [%1]" : "=r" (reg) : "r" (address)); 43 44 return reg; 45 } 46 47 static const mmap_region_t imx_mmap[] = { 48 MAP_REGION_FLAT(GPV_BASE, GPV_SIZE, MT_DEVICE | MT_RW), /* GPV map */ 49 MAP_REGION_FLAT(IMX_ROM_BASE, IMX_ROM_SIZE, MT_MEMORY | MT_RO), /* ROM map */ 50 MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */ 51 MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), /* GIC map */ 52 MAP_REGION_FLAT(IMX_DDRPHY_BASE, IMX_DDR_IPS_SIZE, MT_DEVICE | MT_RW), /* DDRMIX map */ 53 MAP_REGION_FLAT(IMX_DRAM_BASE, IMX_DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS), 54 {0}, 55 }; 56 57 static const struct aipstz_cfg aipstz[] = { 58 {AIPSTZ1_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 59 {AIPSTZ2_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 60 {AIPSTZ3_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 61 {AIPSTZ4_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 62 {0}, 63 }; 64 65 static entry_point_info_t bl32_image_ep_info; 66 static entry_point_info_t bl33_image_ep_info; 67 68 static uint32_t imx_soc_revision; 69 70 int imx_soc_info_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, 71 u_register_t x3) 72 { 73 return imx_soc_revision; 74 } 75 76 #define ANAMIX_DIGPROG 0x6c 77 #define ROM_SOC_INFO_A0 0x800 78 #define ROM_SOC_INFO_B0 0x83C 79 #define OCOTP_SOC_INFO_B1 0x40 80 81 static void imx8mq_soc_info_init(void) 82 { 83 uint32_t rom_version; 84 uint32_t ocotp_val; 85 86 imx_soc_revision = mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_DIGPROG); 87 rom_version = mmio_read_8_ldrb(IMX_ROM_BASE + ROM_SOC_INFO_A0); 88 if (rom_version == 0x10) 89 return; 90 91 rom_version = mmio_read_8_ldrb(IMX_ROM_BASE + ROM_SOC_INFO_B0); 92 if (rom_version == 0x20) { 93 imx_soc_revision &= ~0xff; 94 imx_soc_revision |= rom_version; 95 return; 96 } 97 98 /* 0xff0055aa is magic number for B1 */ 99 ocotp_val = mmio_read_32(IMX_OCOTP_BASE + OCOTP_SOC_INFO_B1); 100 if (ocotp_val == 0xff0055aa) { 101 imx_soc_revision &= ~0xff; 102 if (rom_version == 0x22) { 103 imx_soc_revision |= 0x22; 104 } else { 105 imx_soc_revision |= 0x21; 106 } 107 return; 108 } 109 } 110 111 /* get SPSR for BL33 entry */ 112 static uint32_t get_spsr_for_bl33_entry(void) 113 { 114 unsigned long el_status; 115 unsigned long mode; 116 uint32_t spsr; 117 118 /* figure out what mode we enter the non-secure world */ 119 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 120 el_status &= ID_AA64PFR0_ELX_MASK; 121 122 mode = (el_status) ? MODE_EL2 : MODE_EL1; 123 124 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 125 return spsr; 126 } 127 128 static void bl31_tz380_setup(void) 129 { 130 unsigned int val; 131 132 val = mmio_read_32(IMX_IOMUX_GPR_BASE + IOMUXC_GPR10); 133 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 134 return; 135 136 tzc380_init(IMX_TZASC_BASE); 137 /* 138 * Need to substact offset 0x40000000 from CPU address when 139 * programming tzasc region for i.mx8mq. Enable 1G-5G S/NS RW 140 */ 141 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 142 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 143 } 144 145 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 146 u_register_t arg2, u_register_t arg3) 147 { 148 static console_t console; 149 int i; 150 /* enable CSU NS access permission */ 151 for (i = 0; i < 64; i++) { 152 mmio_write_32(IMX_CSU_BASE + i * 4, 0xffffffff); 153 } 154 155 imx_aipstz_init(aipstz); 156 157 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 158 IMX_CONSOLE_BAUDRATE, &console); 159 /* This console is only used for boot stage */ 160 console_set_scope(&console, CONSOLE_FLAG_BOOT); 161 162 imx8m_caam_init(); 163 164 /* 165 * tell BL3-1 where the non-secure software image is located 166 * and the entry state information. 167 */ 168 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 169 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 170 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 171 172 #if defined(SPD_opteed) || defined(SPD_trusty) 173 /* Populate entry point information for BL32 */ 174 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 175 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 176 bl32_image_ep_info.pc = BL32_BASE; 177 bl32_image_ep_info.spsr = 0; 178 179 /* Pass TEE base and size to bl33 */ 180 bl33_image_ep_info.args.arg1 = BL32_BASE; 181 bl33_image_ep_info.args.arg2 = BL32_SIZE; 182 183 #ifdef SPD_trusty 184 bl32_image_ep_info.args.arg0 = BL32_SIZE; 185 bl32_image_ep_info.args.arg1 = BL32_BASE; 186 #else 187 /* Make sure memory is clean */ 188 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); 189 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 190 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 191 #endif 192 #endif 193 194 bl31_tz380_setup(); 195 } 196 197 void bl31_plat_arch_setup(void) 198 { 199 const mmap_region_t bl_regions[] = { 200 MAP_REGION_FLAT(BL31_START, BL31_SIZE, 201 MT_MEMORY | MT_RW | MT_SECURE), 202 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 203 MT_MEMORY | MT_RO | MT_SECURE), 204 #if USE_COHERENT_MEM 205 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 206 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 207 MT_DEVICE | MT_RW | MT_SECURE), 208 #endif 209 /* Map TEE memory */ 210 MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW), 211 {0}, 212 }; 213 214 setup_page_tables(bl_regions, imx_mmap); 215 /* enable the MMU */ 216 enable_mmu_el3(0); 217 } 218 219 void bl31_platform_setup(void) 220 { 221 generic_delay_timer_init(); 222 223 /* init the GICv3 cpu and distributor interface */ 224 plat_gic_driver_init(); 225 plat_gic_init(); 226 227 /* determine SOC revision for erratas */ 228 imx8mq_soc_info_init(); 229 230 /* gpc init */ 231 imx_gpc_init(); 232 233 dram_info_init(SAVED_DRAM_TIMING_BASE); 234 } 235 236 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 237 { 238 if (type == NON_SECURE) 239 return &bl33_image_ep_info; 240 if (type == SECURE) 241 return &bl32_image_ep_info; 242 243 return NULL; 244 } 245 246 unsigned int plat_get_syscnt_freq2(void) 247 { 248 return COUNTER_FREQUENCY; 249 } 250 251 #ifdef SPD_trusty 252 void plat_trusty_set_boot_args(aapcs64_params_t *args) 253 { 254 args->arg0 = BL32_SIZE; 255 args->arg1 = BL32_BASE; 256 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 257 } 258 #endif 259