1 /* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <drivers/arm/tzc380.h> 17 #include <drivers/console.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/mmio.h> 21 #include <lib/xlat_tables/xlat_tables.h> 22 #include <plat/common/platform.h> 23 24 #include <gpc.h> 25 #include <imx_uart.h> 26 #include <plat_imx8.h> 27 28 static const mmap_region_t imx_mmap[] = { 29 MAP_REGION_FLAT(GPV_BASE, GPV_SIZE, MT_DEVICE | MT_RW), /* GPV map */ 30 MAP_REGION_FLAT(IMX_ROM_BASE, IMX_ROM_SIZE, MT_MEMORY | MT_RO), /* ROM map */ 31 MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */ 32 MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), /* GIC map */ 33 {0}, 34 }; 35 36 static entry_point_info_t bl32_image_ep_info; 37 static entry_point_info_t bl33_image_ep_info; 38 39 static uint32_t imx_soc_revision; 40 41 int imx_soc_info_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, 42 u_register_t x3) 43 { 44 return imx_soc_revision; 45 } 46 47 #define ANAMIX_DIGPROG 0x6c 48 #define ROM_SOC_INFO_A0 0x800 49 #define ROM_SOC_INFO_B0 0x83C 50 #define OCOTP_SOC_INFO_B1 0x40 51 52 static void imx8mq_soc_info_init(void) 53 { 54 uint32_t rom_version; 55 uint32_t ocotp_val; 56 57 imx_soc_revision = mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_DIGPROG); 58 rom_version = mmio_read_8(IMX_ROM_BASE + ROM_SOC_INFO_A0); 59 if (rom_version == 0x10) 60 return; 61 62 rom_version = mmio_read_8(IMX_ROM_BASE + ROM_SOC_INFO_B0); 63 if (rom_version == 0x20) { 64 imx_soc_revision &= ~0xff; 65 imx_soc_revision |= rom_version; 66 return; 67 } 68 69 /* 0xff0055aa is magic number for B1 */ 70 ocotp_val = mmio_read_32(IMX_OCOTP_BASE + OCOTP_SOC_INFO_B1); 71 if (ocotp_val == 0xff0055aa) { 72 imx_soc_revision &= ~0xff; 73 imx_soc_revision |= 0x21; 74 return; 75 } 76 } 77 78 /* get SPSR for BL33 entry */ 79 static uint32_t get_spsr_for_bl33_entry(void) 80 { 81 unsigned long el_status; 82 unsigned long mode; 83 uint32_t spsr; 84 85 /* figure out what mode we enter the non-secure world */ 86 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 87 el_status &= ID_AA64PFR0_ELX_MASK; 88 89 mode = (el_status) ? MODE_EL2 : MODE_EL1; 90 91 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 92 return spsr; 93 } 94 95 static void bl31_tz380_setup(void) 96 { 97 unsigned int val; 98 99 val = mmio_read_32(IMX_IOMUX_GPR_BASE + IOMUXC_GPR10); 100 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 101 return; 102 103 tzc380_init(IMX_TZASC_BASE); 104 /* 105 * Need to substact offset 0x40000000 from CPU address when 106 * programming tzasc region for i.mx8mq. Enable 1G-5G S/NS RW 107 */ 108 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 109 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 110 } 111 112 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 113 u_register_t arg2, u_register_t arg3) 114 { 115 int i; 116 /* enable CSU NS access permission */ 117 for (i = 0; i < 64; i++) { 118 mmio_write_32(IMX_CSU_BASE + i * 4, 0xffffffff); 119 } 120 121 /* config CAAM JRaMID set MID to Cortex A */ 122 mmio_write_32(CAAM_JR0MID, CAAM_NS_MID); 123 mmio_write_32(CAAM_JR1MID, CAAM_NS_MID); 124 mmio_write_32(CAAM_JR2MID, CAAM_NS_MID); 125 126 #if DEBUG_CONSOLE 127 static console_uart_t console; 128 129 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 130 IMX_CONSOLE_BAUDRATE, &console); 131 #endif 132 /* 133 * tell BL3-1 where the non-secure software image is located 134 * and the entry state information. 135 */ 136 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 137 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 138 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 139 140 bl31_tz380_setup(); 141 } 142 143 void bl31_plat_arch_setup(void) 144 { 145 mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE), 146 MT_MEMORY | MT_RW | MT_SECURE); 147 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE), 148 MT_MEMORY | MT_RO | MT_SECURE); 149 150 mmap_add(imx_mmap); 151 152 #if USE_COHERENT_MEM 153 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, 154 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 155 MT_DEVICE | MT_RW | MT_SECURE); 156 #endif 157 /* setup xlat table */ 158 init_xlat_tables(); 159 /* enable the MMU */ 160 enable_mmu_el3(0); 161 } 162 163 void bl31_platform_setup(void) 164 { 165 generic_delay_timer_init(); 166 167 /* init the GICv3 cpu and distributor interface */ 168 plat_gic_driver_init(); 169 plat_gic_init(); 170 171 /* determine SOC revision for erratas */ 172 imx8mq_soc_info_init(); 173 174 /* gpc init */ 175 imx_gpc_init(); 176 } 177 178 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 179 { 180 if (type == NON_SECURE) 181 return &bl33_image_ep_info; 182 if (type == SECURE) 183 return &bl32_image_ep_info; 184 185 return NULL; 186 } 187 188 unsigned int plat_get_syscnt_freq2(void) 189 { 190 return COUNTER_FREQUENCY; 191 } 192 193 void bl31_plat_runtime_setup(void) 194 { 195 return; 196 } 197