1 /* 2 * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <drivers/arm/tzc380.h> 17 #include <drivers/console.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/mmio.h> 21 #include <lib/xlat_tables/xlat_tables_v2.h> 22 #include <plat/common/platform.h> 23 24 #include <dram.h> 25 #include <gpc.h> 26 #include <imx_aipstz.h> 27 #include <imx_uart.h> 28 #include <imx8m_caam.h> 29 #include <plat_imx8.h> 30 31 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 32 33 static const mmap_region_t imx_mmap[] = { 34 MAP_REGION_FLAT(GPV_BASE, GPV_SIZE, MT_DEVICE | MT_RW), /* GPV map */ 35 MAP_REGION_FLAT(IMX_ROM_BASE, IMX_ROM_SIZE, MT_MEMORY | MT_RO), /* ROM map */ 36 MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */ 37 MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), /* GIC map */ 38 MAP_REGION_FLAT(IMX_DDRPHY_BASE, IMX_DDR_IPS_SIZE, MT_DEVICE | MT_RW), /* DDRMIX map */ 39 MAP_REGION_FLAT(IMX_DRAM_BASE, IMX_DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS), 40 {0}, 41 }; 42 43 static const struct aipstz_cfg aipstz[] = { 44 {AIPSTZ1_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 45 {AIPSTZ2_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 46 {AIPSTZ3_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 47 {AIPSTZ4_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 48 {0}, 49 }; 50 51 static entry_point_info_t bl32_image_ep_info; 52 static entry_point_info_t bl33_image_ep_info; 53 54 static uint32_t imx_soc_revision; 55 56 int imx_soc_info_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, 57 u_register_t x3) 58 { 59 return imx_soc_revision; 60 } 61 62 #define ANAMIX_DIGPROG 0x6c 63 #define ROM_SOC_INFO_A0 0x800 64 #define ROM_SOC_INFO_B0 0x83C 65 #define OCOTP_SOC_INFO_B1 0x40 66 67 static void imx8mq_soc_info_init(void) 68 { 69 uint32_t rom_version; 70 uint32_t ocotp_val; 71 72 imx_soc_revision = mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_DIGPROG); 73 rom_version = mmio_read_8(IMX_ROM_BASE + ROM_SOC_INFO_A0); 74 if (rom_version == 0x10) 75 return; 76 77 rom_version = mmio_read_8(IMX_ROM_BASE + ROM_SOC_INFO_B0); 78 if (rom_version == 0x20) { 79 imx_soc_revision &= ~0xff; 80 imx_soc_revision |= rom_version; 81 return; 82 } 83 84 /* 0xff0055aa is magic number for B1 */ 85 ocotp_val = mmio_read_32(IMX_OCOTP_BASE + OCOTP_SOC_INFO_B1); 86 if (ocotp_val == 0xff0055aa) { 87 imx_soc_revision &= ~0xff; 88 if (rom_version == 0x22) { 89 imx_soc_revision |= 0x22; 90 } else { 91 imx_soc_revision |= 0x21; 92 } 93 return; 94 } 95 } 96 97 /* get SPSR for BL33 entry */ 98 static uint32_t get_spsr_for_bl33_entry(void) 99 { 100 unsigned long el_status; 101 unsigned long mode; 102 uint32_t spsr; 103 104 /* figure out what mode we enter the non-secure world */ 105 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 106 el_status &= ID_AA64PFR0_ELX_MASK; 107 108 mode = (el_status) ? MODE_EL2 : MODE_EL1; 109 110 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 111 return spsr; 112 } 113 114 static void bl31_tz380_setup(void) 115 { 116 unsigned int val; 117 118 val = mmio_read_32(IMX_IOMUX_GPR_BASE + IOMUXC_GPR10); 119 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 120 return; 121 122 tzc380_init(IMX_TZASC_BASE); 123 /* 124 * Need to substact offset 0x40000000 from CPU address when 125 * programming tzasc region for i.mx8mq. Enable 1G-5G S/NS RW 126 */ 127 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 128 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 129 } 130 131 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 132 u_register_t arg2, u_register_t arg3) 133 { 134 static console_t console; 135 int i; 136 /* enable CSU NS access permission */ 137 for (i = 0; i < 64; i++) { 138 mmio_write_32(IMX_CSU_BASE + i * 4, 0xffffffff); 139 } 140 141 imx_aipstz_init(aipstz); 142 143 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 144 IMX_CONSOLE_BAUDRATE, &console); 145 /* This console is only used for boot stage */ 146 console_set_scope(&console, CONSOLE_FLAG_BOOT); 147 148 imx8m_caam_init(); 149 150 /* 151 * tell BL3-1 where the non-secure software image is located 152 * and the entry state information. 153 */ 154 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 155 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 156 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 157 158 #if defined(SPD_opteed) || defined(SPD_trusty) 159 /* Populate entry point information for BL32 */ 160 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 161 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 162 bl32_image_ep_info.pc = BL32_BASE; 163 bl32_image_ep_info.spsr = 0; 164 165 /* Pass TEE base and size to bl33 */ 166 bl33_image_ep_info.args.arg1 = BL32_BASE; 167 bl33_image_ep_info.args.arg2 = BL32_SIZE; 168 169 #ifdef SPD_trusty 170 bl32_image_ep_info.args.arg0 = BL32_SIZE; 171 bl32_image_ep_info.args.arg1 = BL32_BASE; 172 #else 173 /* Make sure memory is clean */ 174 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); 175 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 176 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 177 #endif 178 #endif 179 180 bl31_tz380_setup(); 181 } 182 183 void bl31_plat_arch_setup(void) 184 { 185 const mmap_region_t bl_regions[] = { 186 MAP_REGION_FLAT(BL31_START, BL31_SIZE, 187 MT_MEMORY | MT_RW | MT_SECURE), 188 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 189 MT_MEMORY | MT_RO | MT_SECURE), 190 #if USE_COHERENT_MEM 191 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 192 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 193 MT_DEVICE | MT_RW | MT_SECURE), 194 #endif 195 /* Map TEE memory */ 196 MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW), 197 {0}, 198 }; 199 200 setup_page_tables(bl_regions, imx_mmap); 201 /* enable the MMU */ 202 enable_mmu_el3(0); 203 } 204 205 void bl31_platform_setup(void) 206 { 207 generic_delay_timer_init(); 208 209 /* init the GICv3 cpu and distributor interface */ 210 plat_gic_driver_init(); 211 plat_gic_init(); 212 213 /* determine SOC revision for erratas */ 214 imx8mq_soc_info_init(); 215 216 /* gpc init */ 217 imx_gpc_init(); 218 219 dram_info_init(SAVED_DRAM_TIMING_BASE); 220 } 221 222 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 223 { 224 if (type == NON_SECURE) 225 return &bl33_image_ep_info; 226 if (type == SECURE) 227 return &bl32_image_ep_info; 228 229 return NULL; 230 } 231 232 unsigned int plat_get_syscnt_freq2(void) 233 { 234 return COUNTER_FREQUENCY; 235 } 236 237 #ifdef SPD_trusty 238 void plat_trusty_set_boot_args(aapcs64_params_t *args) 239 { 240 args->arg0 = BL32_SIZE; 241 args->arg1 = BL32_BASE; 242 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 243 } 244 #endif 245