1 /* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <drivers/arm/tzc380.h> 17 #include <drivers/console.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/mmio.h> 21 #include <lib/xlat_tables/xlat_tables.h> 22 #include <plat/common/platform.h> 23 24 #include <gpc.h> 25 #include <imx_aipstz.h> 26 #include <imx_uart.h> 27 #include <imx8m_caam.h> 28 #include <plat_imx8.h> 29 30 static const mmap_region_t imx_mmap[] = { 31 MAP_REGION_FLAT(GPV_BASE, GPV_SIZE, MT_DEVICE | MT_RW), /* GPV map */ 32 MAP_REGION_FLAT(IMX_ROM_BASE, IMX_ROM_SIZE, MT_MEMORY | MT_RO), /* ROM map */ 33 MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */ 34 MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), /* GIC map */ 35 {0}, 36 }; 37 38 static const struct aipstz_cfg aipstz[] = { 39 {AIPSTZ1_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 40 {AIPSTZ2_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 41 {AIPSTZ3_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 42 {AIPSTZ4_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 43 {0}, 44 }; 45 46 static entry_point_info_t bl32_image_ep_info; 47 static entry_point_info_t bl33_image_ep_info; 48 49 static uint32_t imx_soc_revision; 50 51 int imx_soc_info_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, 52 u_register_t x3) 53 { 54 return imx_soc_revision; 55 } 56 57 #define ANAMIX_DIGPROG 0x6c 58 #define ROM_SOC_INFO_A0 0x800 59 #define ROM_SOC_INFO_B0 0x83C 60 #define OCOTP_SOC_INFO_B1 0x40 61 62 static void imx8mq_soc_info_init(void) 63 { 64 uint32_t rom_version; 65 uint32_t ocotp_val; 66 67 imx_soc_revision = mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_DIGPROG); 68 rom_version = mmio_read_8(IMX_ROM_BASE + ROM_SOC_INFO_A0); 69 if (rom_version == 0x10) 70 return; 71 72 rom_version = mmio_read_8(IMX_ROM_BASE + ROM_SOC_INFO_B0); 73 if (rom_version == 0x20) { 74 imx_soc_revision &= ~0xff; 75 imx_soc_revision |= rom_version; 76 return; 77 } 78 79 /* 0xff0055aa is magic number for B1 */ 80 ocotp_val = mmio_read_32(IMX_OCOTP_BASE + OCOTP_SOC_INFO_B1); 81 if (ocotp_val == 0xff0055aa) { 82 imx_soc_revision &= ~0xff; 83 imx_soc_revision |= 0x21; 84 return; 85 } 86 } 87 88 /* get SPSR for BL33 entry */ 89 static uint32_t get_spsr_for_bl33_entry(void) 90 { 91 unsigned long el_status; 92 unsigned long mode; 93 uint32_t spsr; 94 95 /* figure out what mode we enter the non-secure world */ 96 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 97 el_status &= ID_AA64PFR0_ELX_MASK; 98 99 mode = (el_status) ? MODE_EL2 : MODE_EL1; 100 101 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 102 return spsr; 103 } 104 105 static void bl31_tz380_setup(void) 106 { 107 unsigned int val; 108 109 val = mmio_read_32(IMX_IOMUX_GPR_BASE + IOMUXC_GPR10); 110 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 111 return; 112 113 tzc380_init(IMX_TZASC_BASE); 114 /* 115 * Need to substact offset 0x40000000 from CPU address when 116 * programming tzasc region for i.mx8mq. Enable 1G-5G S/NS RW 117 */ 118 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 119 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 120 } 121 122 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 123 u_register_t arg2, u_register_t arg3) 124 { 125 int i; 126 /* enable CSU NS access permission */ 127 for (i = 0; i < 64; i++) { 128 mmio_write_32(IMX_CSU_BASE + i * 4, 0xffffffff); 129 } 130 131 imx_aipstz_init(aipstz); 132 133 imx8m_caam_init(); 134 135 #if DEBUG_CONSOLE 136 static console_t console; 137 138 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 139 IMX_CONSOLE_BAUDRATE, &console); 140 #endif 141 /* 142 * tell BL3-1 where the non-secure software image is located 143 * and the entry state information. 144 */ 145 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 146 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 147 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 148 149 #ifdef SPD_opteed 150 /* Populate entry point information for BL32 */ 151 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 152 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 153 bl32_image_ep_info.pc = BL32_BASE; 154 bl32_image_ep_info.spsr = 0; 155 156 /* Pass TEE base and size to bl33 */ 157 bl33_image_ep_info.args.arg1 = BL32_BASE; 158 bl33_image_ep_info.args.arg2 = BL32_SIZE; 159 #endif 160 161 bl31_tz380_setup(); 162 } 163 164 void bl31_plat_arch_setup(void) 165 { 166 mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE), 167 MT_MEMORY | MT_RW | MT_SECURE); 168 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE), 169 MT_MEMORY | MT_RO | MT_SECURE); 170 171 mmap_add(imx_mmap); 172 173 #if USE_COHERENT_MEM 174 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, 175 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 176 MT_DEVICE | MT_RW | MT_SECURE); 177 #endif 178 /* setup xlat table */ 179 init_xlat_tables(); 180 /* enable the MMU */ 181 enable_mmu_el3(0); 182 } 183 184 void bl31_platform_setup(void) 185 { 186 generic_delay_timer_init(); 187 188 /* init the GICv3 cpu and distributor interface */ 189 plat_gic_driver_init(); 190 plat_gic_init(); 191 192 /* determine SOC revision for erratas */ 193 imx8mq_soc_info_init(); 194 195 /* gpc init */ 196 imx_gpc_init(); 197 } 198 199 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 200 { 201 if (type == NON_SECURE) 202 return &bl33_image_ep_info; 203 if (type == SECURE) 204 return &bl32_image_ep_info; 205 206 return NULL; 207 } 208 209 unsigned int plat_get_syscnt_freq2(void) 210 { 211 return COUNTER_FREQUENCY; 212 } 213 214 void bl31_plat_runtime_setup(void) 215 { 216 return; 217 } 218