1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdlib.h> 8 #include <stdint.h> 9 #include <stdbool.h> 10 11 #include <common/debug.h> 12 #include <lib/mmio.h> 13 #include <lib/psci/psci.h> 14 #include <platform_def.h> 15 #include <services/std_svc.h> 16 17 #include <gpc.h> 18 19 /* use wfi power down the core */ 20 void imx_set_cpu_pwr_off(unsigned int core_id) 21 { 22 bakery_lock_get(&gpc_lock); 23 24 /* enable the wfi power down of the core */ 25 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | 26 (1 << (core_id + 20))); 27 28 bakery_lock_release(&gpc_lock); 29 30 /* assert the pcg pcr bit of the core */ 31 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); 32 }; 33 34 /* if out of lpm, we need to do reverse steps */ 35 void imx_set_cpu_lpm(unsigned int core_id, bool pdn) 36 { 37 bakery_lock_get(&gpc_lock); 38 39 if (pdn) { 40 /* enable the core WFI PDN & IRQ PUP */ 41 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | 42 (1 << (core_id + 20)) | COREx_IRQ_WUP(core_id)); 43 /* assert the pcg pcr bit of the core */ 44 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); 45 } else { 46 /* disable CORE WFI PDN & IRQ PUP */ 47 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | 48 COREx_IRQ_WUP(core_id)); 49 /* deassert the pcg pcr bit of the core */ 50 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); 51 } 52 53 bakery_lock_release(&gpc_lock); 54 } 55 56 void imx_pup_pdn_slot_config(int last_core, bool pdn) 57 { 58 if (pdn) { 59 /* SLOT0 for A53 PLAT power down */ 60 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(0), SLT_PLAT_PDN); 61 /* SLOT1 for A53 PLAT power up */ 62 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(1), SLT_PLAT_PUP); 63 /* SLOT2 for A53 primary core power up */ 64 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(2), SLT_COREx_PUP(last_core)); 65 /* ACK setting: PLAT ACK for PDN, CORE ACK for PUP */ 66 mmio_clrsetbits_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, 0xFFFFFFFF, 67 A53_PLAT_PDN_ACK | A53_PLAT_PUP_ACK); 68 } else { 69 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(0), 0xFFFFFFFF); 70 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(1), 0xFFFFFFFF); 71 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(2), 0xFFFFFFFF); 72 mmio_clrsetbits_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, 0xFFFFFFFF, 73 A53_DUMMY_PDN_ACK | A53_DUMMY_PUP_ACK); 74 } 75 } 76 77 void imx_set_cluster_powerdown(unsigned int last_core, uint8_t power_state) 78 { 79 uint32_t val; 80 81 if (is_local_state_off(power_state)) { 82 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC); 83 val |= A53_LPM_STOP; /* enable C0-C1's STOP mode */ 84 val &= ~CPU_CLOCK_ON_LPM; /* disable CPU clock in LPM mode */ 85 mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val); 86 87 /* enable C2-3's STOP mode */ 88 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, A53_LPM_STOP); 89 90 /* enable PLAT/SCU power down */ 91 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD); 92 val &= ~EN_L2_WFI_PDN; 93 val |= L2PGE | EN_PLAT_PDN; 94 val &= ~COREx_IRQ_WUP(last_core); /* disable IRQ PUP for last core */ 95 val |= COREx_LPM_PUP(last_core); /* enable LPM PUP for last core */ 96 mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val); 97 98 imx_pup_pdn_slot_config(last_core, true); 99 100 /* enable PLAT PGC */ 101 mmio_setbits_32(IMX_GPC_BASE + A53_PLAT_PGC, 0x1); 102 } else { 103 /* clear PLAT PGC */ 104 mmio_clrbits_32(IMX_GPC_BASE + A53_PLAT_PGC, 0x1); 105 106 /* clear the slot and ack for cluster power down */ 107 imx_pup_pdn_slot_config(last_core, false); 108 109 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC); 110 val &= ~A53_LPM_MASK; /* clear the C0~1 LPM */ 111 val |= CPU_CLOCK_ON_LPM; /* disable cpu clock in LPM */ 112 mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val); 113 114 /* set A53 LPM to RUN mode */ 115 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, A53_LPM_MASK); 116 117 /* clear PLAT/SCU power down */ 118 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD); 119 val |= EN_L2_WFI_PDN; 120 val &= ~(L2PGE | EN_PLAT_PDN); 121 val &= ~COREx_LPM_PUP(last_core); /* disable C0's LPM PUP */ 122 mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val); 123 } 124 } 125 126 void imx_gpc_init(void) 127 { 128 uint32_t val; 129 int i; 130 /* mask all the interrupt by default */ 131 for (i = 0; i < 4; i++) { 132 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, ~0x0); 133 mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, ~0x0); 134 mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53 + i * 4, ~0x0); 135 mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0); 136 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0); 137 } 138 /* Due to the hardware design requirement, need to make 139 * sure GPR interrupt(#32) is unmasked during RUN mode to 140 * avoid entering DSM mode by mistake. 141 */ 142 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53, 0xFFFFFFFE); 143 mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53, 0xFFFFFFFE); 144 mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53, 0xFFFFFFFE); 145 mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53, 0xFFFFFFFE); 146 147 /* use external IRQs to wakeup C0~C3 from LPM */ 148 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC); 149 val |= IRQ_SRC_A53_WUP; 150 /* clear the MASTER0 LPM handshake */ 151 val &= ~MASTER0_LPM_HSK; 152 mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val); 153 154 /* mask M4 DSM trigger if M4 is NOT enabled */ 155 mmio_setbits_32(IMX_GPC_BASE + LPCR_M4, DSM_MODE_MASK); 156 157 /* set all mix/PU in A53 domain */ 158 mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0xfffd); 159 160 /* set SCU timming */ 161 mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING, 162 (0x59 << 10) | 0x5B | (0x2 << 20)); 163 164 /* set DUMMY PDN/PUP ACK by default for A53 domain */ 165 mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, A53_DUMMY_PUP_ACK | 166 A53_DUMMY_PDN_ACK); 167 168 /* disable DSM mode by default */ 169 mmio_clrbits_32(IMX_GPC_BASE + SLPCR, DSM_MODE_MASK); 170 171 /* 172 * USB PHY power up needs to make sure RESET bit in SRC is clear, 173 * otherwise, the PU power up bit in GPC will NOT self-cleared. 174 * only need to do it once. 175 */ 176 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1); 177 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1); 178 179 /* enable all the power domain by default */ 180 mmio_write_32(IMX_GPC_BASE + PU_PGC_UP_TRG, 0x3fcf); 181 } 182