1 /*
2 * Copyright 2021 NXP
3 * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <assert.h>
9 #include <stdbool.h>
10
11 #include <arch_helpers.h>
12 #include <common/bl_common.h>
13 #include <common/debug.h>
14 #include <common/desc_image_load.h>
15 #include <common/tbbr/tbbr_img_def.h>
16 #include <context.h>
17 #include <drivers/arm/tzc380.h>
18 #include <drivers/console.h>
19 #include <drivers/generic_delay_timer.h>
20 #include <drivers/mmc.h>
21 #include <lib/el3_runtime/context_mgmt.h>
22 #include <lib/mmio.h>
23 #include <lib/optee_utils.h>
24 #include <lib/xlat_tables/xlat_tables_v2.h>
25
26 #include <imx8m_caam.h>
27 #include "imx8mp_private.h"
28 #include <imx_aipstz.h>
29 #include <imx_rdc.h>
30 #include <imx_uart.h>
31 #include <plat/common/platform.h>
32 #include <plat_imx8.h>
33 #include <platform_def.h>
34
35
36 static const struct aipstz_cfg aipstz[] = {
37 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
38 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
39 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
40 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
41 {0},
42 };
43
bl2_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)44 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
45 u_register_t arg2, u_register_t arg3)
46 {
47 static console_t console;
48 unsigned int i;
49
50 /* Enable CSU NS access permission */
51 for (i = 0U; i < 64; i++) {
52 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff);
53 }
54
55 imx_aipstz_init(aipstz);
56
57 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
58 IMX_CONSOLE_BAUDRATE, &console);
59
60 generic_delay_timer_init();
61
62 /* select the CKIL source to 32K OSC */
63 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1);
64
65 /* Open handles to a FIP image */
66 plat_imx_io_setup();
67 }
68
bl2_plat_arch_setup(void)69 void bl2_plat_arch_setup(void)
70 {
71 }
72
bl2_platform_setup(void)73 void bl2_platform_setup(void)
74 {
75 }
76
bl2_plat_handle_post_image_load(unsigned int image_id)77 int bl2_plat_handle_post_image_load(unsigned int image_id)
78 {
79 int err = 0;
80 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
81 bl_mem_params_node_t *pager_mem_params = NULL;
82 bl_mem_params_node_t *paged_mem_params = NULL;
83
84 assert(bl_mem_params);
85
86 switch (image_id) {
87 case BL32_IMAGE_ID:
88 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
89 assert(pager_mem_params);
90
91 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
92 assert(paged_mem_params);
93
94 err = parse_optee_header(&bl_mem_params->ep_info,
95 &pager_mem_params->image_info,
96 &paged_mem_params->image_info);
97 if (err != 0) {
98 WARN("OPTEE header parse error.\n");
99 }
100
101 break;
102 default:
103 /* Do nothing in default case */
104 break;
105 }
106
107 return err;
108 }
109
plat_get_syscnt_freq2(void)110 unsigned int plat_get_syscnt_freq2(void)
111 {
112 return COUNTER_FREQUENCY;
113 }
114
bl2_plat_runtime_setup(void)115 void bl2_plat_runtime_setup(void)
116 {
117 return;
118 }
119