1 /* 2 * Copyright (c) 2019-2022 ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <drivers/arm/tzc380.h> 17 #include <drivers/console.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/mmio.h> 21 #include <lib/xlat_tables/xlat_tables_v2.h> 22 #include <plat/common/platform.h> 23 24 #include <dram.h> 25 #include <gpc.h> 26 #include <imx_aipstz.h> 27 #include <imx_uart.h> 28 #include <imx_rdc.h> 29 #include <imx8m_caam.h> 30 #include <imx8m_ccm.h> 31 #include <imx8m_csu.h> 32 #include <imx8m_snvs.h> 33 #include <plat_imx8.h> 34 35 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 36 37 /* 38 * Note: DRAM region is mapped with entire size available and uses MT_RW 39 * attributes. 40 * See details in docs/plat/imx8m.rst "High Assurance Boot (HABv4)" section 41 * for explanation of this mapping scheme. 42 */ 43 static const mmap_region_t imx_mmap[] = { 44 MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), 45 MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */ 46 MAP_REGION_FLAT(OCRAM_S_BASE, OCRAM_S_SIZE, MT_DEVICE | MT_RW), /* OCRAM_S */ 47 MAP_REGION_FLAT(IMX_DDRPHY_BASE, IMX_DDR_IPS_SIZE, MT_DEVICE | MT_RW), /* DDRMIX */ 48 MAP_REGION_FLAT(IMX_VPUMIX_BASE, IMX_VPUMIX_SIZE, MT_DEVICE | MT_RW), /* VPUMIX */ 49 MAP_REGION_FLAT(IMX_CAAM_RAM_BASE, IMX_CAAM_RAM_SIZE, MT_MEMORY | MT_RW), /* CAMM RAM */ 50 MAP_REGION_FLAT(IMX_NS_OCRAM_BASE, IMX_NS_OCRAM_SIZE, MT_MEMORY | MT_RW), /* NS OCRAM */ 51 MAP_REGION_FLAT(IMX_ROM_BASE, IMX_ROM_SIZE, MT_MEMORY | MT_RO), /* ROM code */ 52 MAP_REGION_FLAT(IMX_DRAM_BASE, IMX_DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS), /* DRAM */ 53 {0}, 54 }; 55 56 static const struct aipstz_cfg aipstz[] = { 57 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 58 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 59 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 60 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 61 {0}, 62 }; 63 64 static const struct imx_rdc_cfg rdc[] = { 65 /* Master domain assignment */ 66 RDC_MDAn(RDC_MDA_M4, DID1), 67 68 /* peripherals domain permission */ 69 RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W), 70 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), 71 72 /* memory region */ 73 74 /* Sentinel */ 75 {0}, 76 }; 77 78 static const struct imx_csu_cfg csu_cfg[] = { 79 /* peripherals csl setting */ 80 CSU_CSLx(0x1, CSU_SEC_LEVEL_0, UNLOCKED), 81 82 /* master HP0~1 */ 83 84 /* SA setting */ 85 CSU_SA(CSU_SA_M4, NON_SEC_ACCESS, LOCKED), 86 CSU_SA(CSU_SA_SDMA1, NON_SEC_ACCESS, LOCKED), 87 CSU_SA(CSU_SA_PCIE_CTRL1, NON_SEC_ACCESS, LOCKED), 88 CSU_SA(CSU_SA_USB1, NON_SEC_ACCESS, LOCKED), 89 CSU_SA(CSU_SA_USB2, NON_SEC_ACCESS, LOCKED), 90 CSU_SA(CSU_SA_VPU, NON_SEC_ACCESS, LOCKED), 91 CSU_SA(CSU_SA_GPU, NON_SEC_ACCESS, LOCKED), 92 CSU_SA(CSU_SA_APBHDMA, NON_SEC_ACCESS, LOCKED), 93 CSU_SA(CSU_SA_ENET, NON_SEC_ACCESS, LOCKED), 94 CSU_SA(CSU_SA_USDHC1, NON_SEC_ACCESS, LOCKED), 95 CSU_SA(CSU_SA_USDHC2, NON_SEC_ACCESS, LOCKED), 96 CSU_SA(CSU_SA_USDHC3, NON_SEC_ACCESS, LOCKED), 97 CSU_SA(CSU_SA_HUGO, NON_SEC_ACCESS, LOCKED), 98 CSU_SA(CSU_SA_DAP, NON_SEC_ACCESS, LOCKED), 99 CSU_SA(CSU_SA_SDMA2, NON_SEC_ACCESS, LOCKED), 100 CSU_SA(CSU_SA_SDMA3, NON_SEC_ACCESS, LOCKED), 101 CSU_SA(CSU_SA_LCDIF, NON_SEC_ACCESS, LOCKED), 102 CSU_SA(CSU_SA_CSI, NON_SEC_ACCESS, LOCKED), 103 104 /* HP control setting */ 105 106 /* Sentinel */ 107 {0} 108 }; 109 110 static entry_point_info_t bl32_image_ep_info; 111 static entry_point_info_t bl33_image_ep_info; 112 113 /* get SPSR for BL33 entry */ 114 static uint32_t get_spsr_for_bl33_entry(void) 115 { 116 unsigned long el_status; 117 unsigned long mode; 118 uint32_t spsr; 119 120 /* figure out what mode we enter the non-secure world */ 121 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 122 el_status &= ID_AA64PFR0_ELX_MASK; 123 124 mode = (el_status) ? MODE_EL2 : MODE_EL1; 125 126 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 127 return spsr; 128 } 129 130 void bl31_tzc380_setup(void) 131 { 132 unsigned int val; 133 134 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28); 135 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 136 return; 137 138 tzc380_init(IMX_TZASC_BASE); 139 140 /* 141 * Need to substact offset 0x40000000 from CPU address when 142 * programming tzasc region for i.mx8mm. 143 */ 144 145 /* Enable 1G-5G S/NS RW */ 146 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 147 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 148 } 149 150 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 151 u_register_t arg2, u_register_t arg3) 152 { 153 unsigned int console_base = IMX_BOOT_UART_BASE; 154 static console_t console; 155 int i; 156 157 /* Enable CSU NS access permission */ 158 for (i = 0; i < 64; i++) { 159 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); 160 } 161 162 imx_aipstz_init(aipstz); 163 164 imx_rdc_init(rdc); 165 166 imx_csu_init(csu_cfg); 167 168 if (console_base == 0U) { 169 console_base = imx8m_uart_get_base(); 170 } 171 172 console_imx_uart_register(console_base, IMX_BOOT_UART_CLK_IN_HZ, 173 IMX_CONSOLE_BAUDRATE, &console); 174 /* This console is only used for boot stage */ 175 console_set_scope(&console, CONSOLE_FLAG_BOOT); 176 177 imx8m_caam_init(); 178 179 /* 180 * tell BL3-1 where the non-secure software image is located 181 * and the entry state information. 182 */ 183 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 184 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 185 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 186 187 #if defined(SPD_opteed) || defined(SPD_trusty) 188 /* Populate entry point information for BL32 */ 189 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 190 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 191 bl32_image_ep_info.pc = BL32_BASE; 192 bl32_image_ep_info.spsr = 0; 193 194 /* Pass TEE base and size to bl33 */ 195 bl33_image_ep_info.args.arg1 = BL32_BASE; 196 bl33_image_ep_info.args.arg2 = BL32_SIZE; 197 198 #ifdef SPD_trusty 199 bl32_image_ep_info.args.arg0 = BL32_SIZE; 200 bl32_image_ep_info.args.arg1 = BL32_BASE; 201 #else 202 /* Make sure memory is clean */ 203 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); 204 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 205 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 206 #endif 207 #endif 208 209 #if !defined(SPD_opteed) && !defined(SPD_trusty) 210 enable_snvs_privileged_access(); 211 #endif 212 213 bl31_tzc380_setup(); 214 } 215 216 #define MAP_BL31_TOTAL \ 217 MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE) 218 #define MAP_BL31_RO \ 219 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE) 220 #define MAP_COHERENT_MEM \ 221 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ 222 MT_DEVICE | MT_RW | MT_SECURE) 223 #define MAP_BL32_TOTAL \ 224 MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW) 225 226 void bl31_plat_arch_setup(void) 227 { 228 const mmap_region_t bl_regions[] = { 229 MAP_BL31_TOTAL, 230 MAP_BL31_RO, 231 #if USE_COHERENT_MEM 232 MAP_COHERENT_MEM, 233 #endif 234 #if defined(SPD_opteed) || defined(SPD_trusty) 235 /* Map TEE memory */ 236 MAP_BL32_TOTAL, 237 #endif 238 {0} 239 }; 240 241 setup_page_tables(bl_regions, imx_mmap); 242 enable_mmu_el3(0); 243 } 244 245 void bl31_platform_setup(void) 246 { 247 generic_delay_timer_init(); 248 249 /* select the CKIL source to 32K OSC */ 250 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); 251 252 /* Init the dram info */ 253 dram_info_init(SAVED_DRAM_TIMING_BASE); 254 255 plat_gic_driver_init(); 256 plat_gic_init(); 257 258 imx_gpc_init(); 259 } 260 261 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 262 { 263 if (type == NON_SECURE) 264 return &bl33_image_ep_info; 265 if (type == SECURE) 266 return &bl32_image_ep_info; 267 268 return NULL; 269 } 270 271 unsigned int plat_get_syscnt_freq2(void) 272 { 273 return COUNTER_FREQUENCY; 274 } 275 276 #ifdef SPD_trusty 277 void plat_trusty_set_boot_args(aapcs64_params_t *args) 278 { 279 args->arg0 = BL32_SIZE; 280 args->arg1 = BL32_BASE; 281 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 282 } 283 #endif 284