1 /* 2 * Copyright (c) 2019-2022 ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <drivers/arm/tzc380.h> 17 #include <drivers/console.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/mmio.h> 21 #include <lib/xlat_tables/xlat_tables_v2.h> 22 #include <plat/common/platform.h> 23 24 #include <dram.h> 25 #include <gpc.h> 26 #include <imx_aipstz.h> 27 #include <imx_uart.h> 28 #include <imx_rdc.h> 29 #include <imx8m_caam.h> 30 #include <imx8m_ccm.h> 31 #include <imx8m_csu.h> 32 #include <imx8m_snvs.h> 33 #include <plat_imx8.h> 34 35 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 36 37 /* 38 * Note: DRAM region is mapped with entire size available and uses MT_RW 39 * attributes. 40 * See details in docs/plat/imx8m.rst "High Assurance Boot (HABv4)" section 41 * for explanation of this mapping scheme. 42 */ 43 static const mmap_region_t imx_mmap[] = { 44 MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), 45 MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */ 46 MAP_REGION_FLAT(OCRAM_S_BASE, OCRAM_S_SIZE, MT_DEVICE | MT_RW), /* OCRAM_S */ 47 MAP_REGION_FLAT(IMX_DDRPHY_BASE, IMX_DDR_IPS_SIZE, MT_DEVICE | MT_RW), /* DDRMIX */ 48 MAP_REGION_FLAT(IMX_VPUMIX_BASE, IMX_VPUMIX_SIZE, MT_DEVICE | MT_RW), /* VPUMIX */ 49 MAP_REGION_FLAT(IMX_CAAM_RAM_BASE, IMX_CAAM_RAM_SIZE, MT_MEMORY | MT_RW), /* CAMM RAM */ 50 MAP_REGION_FLAT(IMX_NS_OCRAM_BASE, IMX_NS_OCRAM_SIZE, MT_MEMORY | MT_RW), /* NS OCRAM */ 51 MAP_REGION_FLAT(IMX_ROM_BASE, IMX_ROM_SIZE, MT_MEMORY | MT_RO), /* ROM code */ 52 MAP_REGION_FLAT(IMX_DRAM_BASE, IMX_DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS), /* DRAM */ 53 {0}, 54 }; 55 56 static const struct aipstz_cfg aipstz[] = { 57 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 58 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 59 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 60 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 61 {0}, 62 }; 63 64 static const struct imx_rdc_cfg rdc[] = { 65 /* Master domain assignment */ 66 RDC_MDAn(RDC_MDA_M4, DID1), 67 68 /* peripherals domain permission */ 69 RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W), 70 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), 71 72 /* memory region */ 73 74 /* Sentinel */ 75 {0}, 76 }; 77 78 static const struct imx_csu_cfg csu_cfg[] = { 79 /* peripherals csl setting */ 80 CSU_CSLx(CSU_CSL_RDC, CSU_SEC_LEVEL_3, LOCKED), 81 CSU_CSLx(CSU_CSL_TZASC, CSU_SEC_LEVEL_5, LOCKED), 82 CSU_CSLx(CSU_CSL_CSU, CSU_SEC_LEVEL_5, LOCKED), 83 84 /* master HP0~1 */ 85 86 /* SA setting */ 87 CSU_SA(CSU_SA_M4, NON_SEC_ACCESS, LOCKED), 88 CSU_SA(CSU_SA_SDMA1, NON_SEC_ACCESS, LOCKED), 89 CSU_SA(CSU_SA_PCIE_CTRL1, NON_SEC_ACCESS, LOCKED), 90 CSU_SA(CSU_SA_USB1, NON_SEC_ACCESS, LOCKED), 91 CSU_SA(CSU_SA_USB2, NON_SEC_ACCESS, LOCKED), 92 CSU_SA(CSU_SA_VPU, NON_SEC_ACCESS, LOCKED), 93 CSU_SA(CSU_SA_GPU, NON_SEC_ACCESS, LOCKED), 94 CSU_SA(CSU_SA_APBHDMA, NON_SEC_ACCESS, LOCKED), 95 CSU_SA(CSU_SA_ENET, NON_SEC_ACCESS, LOCKED), 96 CSU_SA(CSU_SA_USDHC1, NON_SEC_ACCESS, LOCKED), 97 CSU_SA(CSU_SA_USDHC2, NON_SEC_ACCESS, LOCKED), 98 CSU_SA(CSU_SA_USDHC3, NON_SEC_ACCESS, LOCKED), 99 CSU_SA(CSU_SA_HUGO, NON_SEC_ACCESS, LOCKED), 100 CSU_SA(CSU_SA_DAP, NON_SEC_ACCESS, LOCKED), 101 CSU_SA(CSU_SA_SDMA2, NON_SEC_ACCESS, LOCKED), 102 CSU_SA(CSU_SA_SDMA3, NON_SEC_ACCESS, LOCKED), 103 CSU_SA(CSU_SA_LCDIF, NON_SEC_ACCESS, LOCKED), 104 CSU_SA(CSU_SA_CSI, NON_SEC_ACCESS, LOCKED), 105 106 /* HP control setting */ 107 108 /* Sentinel */ 109 {0} 110 }; 111 112 static entry_point_info_t bl32_image_ep_info; 113 static entry_point_info_t bl33_image_ep_info; 114 115 /* get SPSR for BL33 entry */ 116 static uint32_t get_spsr_for_bl33_entry(void) 117 { 118 unsigned long el_status; 119 unsigned long mode; 120 uint32_t spsr; 121 122 /* figure out what mode we enter the non-secure world */ 123 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 124 el_status &= ID_AA64PFR0_ELX_MASK; 125 126 mode = (el_status) ? MODE_EL2 : MODE_EL1; 127 128 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 129 return spsr; 130 } 131 132 void bl31_tzc380_setup(void) 133 { 134 unsigned int val; 135 136 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28); 137 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 138 return; 139 140 tzc380_init(IMX_TZASC_BASE); 141 142 /* 143 * Need to substact offset 0x40000000 from CPU address when 144 * programming tzasc region for i.mx8mm. 145 */ 146 147 /* Enable 1G-5G S/NS RW */ 148 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 149 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 150 } 151 152 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 153 u_register_t arg2, u_register_t arg3) 154 { 155 unsigned int console_base = IMX_BOOT_UART_BASE; 156 static console_t console; 157 int i; 158 159 /* Enable CSU NS access permission */ 160 for (i = 0; i < 64; i++) { 161 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); 162 } 163 164 imx_aipstz_init(aipstz); 165 166 imx_rdc_init(rdc); 167 168 imx_csu_init(csu_cfg); 169 170 if (console_base == 0U) { 171 console_base = imx8m_uart_get_base(); 172 } 173 174 console_imx_uart_register(console_base, IMX_BOOT_UART_CLK_IN_HZ, 175 IMX_CONSOLE_BAUDRATE, &console); 176 /* This console is only used for boot stage */ 177 console_set_scope(&console, CONSOLE_FLAG_BOOT); 178 179 imx8m_caam_init(); 180 181 /* 182 * tell BL3-1 where the non-secure software image is located 183 * and the entry state information. 184 */ 185 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 186 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 187 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 188 189 #if defined(SPD_opteed) || defined(SPD_trusty) 190 /* Populate entry point information for BL32 */ 191 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 192 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 193 bl32_image_ep_info.pc = BL32_BASE; 194 bl32_image_ep_info.spsr = 0; 195 196 /* Pass TEE base and size to bl33 */ 197 bl33_image_ep_info.args.arg1 = BL32_BASE; 198 bl33_image_ep_info.args.arg2 = BL32_SIZE; 199 200 #ifdef SPD_trusty 201 bl32_image_ep_info.args.arg0 = BL32_SIZE; 202 bl32_image_ep_info.args.arg1 = BL32_BASE; 203 #else 204 /* Make sure memory is clean */ 205 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); 206 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 207 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 208 #endif 209 #endif 210 211 #if !defined(SPD_opteed) && !defined(SPD_trusty) 212 enable_snvs_privileged_access(); 213 #endif 214 215 bl31_tzc380_setup(); 216 } 217 218 #define MAP_BL31_TOTAL \ 219 MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE) 220 #define MAP_BL31_RO \ 221 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE) 222 #define MAP_COHERENT_MEM \ 223 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ 224 MT_DEVICE | MT_RW | MT_SECURE) 225 #define MAP_BL32_TOTAL \ 226 MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW) 227 228 void bl31_plat_arch_setup(void) 229 { 230 const mmap_region_t bl_regions[] = { 231 MAP_BL31_TOTAL, 232 MAP_BL31_RO, 233 #if USE_COHERENT_MEM 234 MAP_COHERENT_MEM, 235 #endif 236 #if defined(SPD_opteed) || defined(SPD_trusty) 237 /* Map TEE memory */ 238 MAP_BL32_TOTAL, 239 #endif 240 {0} 241 }; 242 243 setup_page_tables(bl_regions, imx_mmap); 244 enable_mmu_el3(0); 245 } 246 247 void bl31_platform_setup(void) 248 { 249 generic_delay_timer_init(); 250 251 /* select the CKIL source to 32K OSC */ 252 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); 253 254 /* Init the dram info */ 255 dram_info_init(SAVED_DRAM_TIMING_BASE); 256 257 plat_gic_driver_init(); 258 plat_gic_init(); 259 260 imx_gpc_init(); 261 } 262 263 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 264 { 265 if (type == NON_SECURE) 266 return &bl33_image_ep_info; 267 if (type == SECURE) 268 return &bl32_image_ep_info; 269 270 return NULL; 271 } 272 273 unsigned int plat_get_syscnt_freq2(void) 274 { 275 return COUNTER_FREQUENCY; 276 } 277 278 #ifdef SPD_trusty 279 void plat_trusty_set_boot_args(aapcs64_params_t *args) 280 { 281 args->arg0 = BL32_SIZE; 282 args->arg1 = BL32_BASE; 283 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 284 } 285 #endif 286